Datasheet DS1033Z-30, DS1033Z-25-T-R, DS1033Z-25, DS1033Z-20-T-R, DS1033Z-20 Datasheet (Dallas Semiconductor)
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FEATURES
All-silicon timing circuit
Three independent buffered delays
Initial delay tolerance ±1.5 ns
Stable and precise over temperature and
voltage
Leading and trailing edge precision preserves
the input symmetry
Standard 8-pin DIP, 8-pin SOIC
Vapor phasing, IR and wave solderable
Available in Tape and Reel
PIN ASSIGNMENT
PIN DESCRIPTION
IN1-IN3 - Input Signals
OUT1-OUT3 - Output Signals
NC - No Connection
VCC - Supply Voltage
GND - Ground
(Sub) - Internal substrate
connection, do not make
any external connections
to these pins
DESCRIPTION
The DS1033 series is a low-power +3.3 Volt version of the DS1035. It is characterized for operation
over the range of 2.7V to 3.6V.
The DS1033 series of delay lines have three independent logic buffered delays in a single package. It is
available in a standard 8-pin DIP, 150-mil 8-pin mini-SOIC.
The device features precise leading and trailing edge accuracies. It has the inherent reliability of an allsilicon delay line solution. The DS1033’s nominal tolerance is ±1.5 ns and an additional tolerance over
temperature and voltage of ±1.0 ns for the faster delays. Detailed specifications are shown in Table 1.
Standard delay values are indicated in Table 1. Customers may contact Dallas Semiconductor at (972)
371-4348 for further information.
DS1033
3-in-1 Low Voltage Silicon Delay Line
www.dalsemi.com
DS1033Z 8-Pin SOIC (150-mil)
See Mech. Drawings Section
IN1
IN2
IN3
GND
V
CC
OUT3
OUT1
OUT2
1
2348765
DS1033M 8-Pin DIP
See Mech. Drawings Section
V
CC
OUT3
OUT1
OUT2
IN1
IN2
IN3
GND
1
2348765
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DS1033
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LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (t
PLH
, t
PHL
) Table 1
TOLERANCE OVER TEMPERATURE
AND VOLTAGE (note 2)
PART NUMBER
DELAY PER
OUTPUT (ns)
(note 1)
INITIAL
TOLERANCE
(note 1)
VCC=3.3V ±±±±====0.3V
VCC=2.7V
DS1033-80 8/8/8
±1.5 ns ±1.0 ns ±1.5 ns
DS1033-10 10/10/10
±1.5 ns ±1.0 ns ±1.5 ns
DS1033-12 12/12/12
±1.5 ns ±1.0 ns ±1.5 ns
DS1033-15 15/15/15
±1.5 ns ±1.5 ns ±2.0 ns
DS1033-20 20/20/20
±1.5 ns ±1.5 ns ±2.5 ns
DS1033-25 25/25/25
±2.0 ns ±2.0 ns ±3.5 ns
DS1033-30 30/30/30 ±2.0 ns ±2.0 ns ±5.0 ns
NOTES:
1. Nominal conditions are +25°C and VCC=+3.3 volts.
2. Temperature range of 0°C to 70°C.
3. Delay accuracy is for both leading and trailing edges.
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DS1033
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TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1033.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution ) connected to the output. The DS1033 output taps
are selected and connected to the interval counter by a VHF switch control unit. All measurements are
fully automated with each instrument controlled by the computer over an IEEE 488 bus.
DS1033 TEST CIRCUIT Figure 2
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DS1033
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ABSOLUTE MAXIMUM RA TINGS*
Voltage on Any Pin Relative to Ground -1.0V to +6.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds
Short Circuit Output Current 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or an y other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (TA =0°C to 70°C)
PARAMETER SYMBOL TEST
CONDITION
MIN TYP MAX UNITS
Supply Voltage V
CC
2.7 3.3 3.6 V
Active Current I
CC
VCC=3.6V
Period=1µs
25 mA
High Level Input Voltage V
IH
2.0
V
CC
+0.5
V
Low Level Input Voltage V
IL
-0.5 0.8 V
Input Leakage I
L
0V≤VI≤V
CC
-1.0 1.0
µA
High Level Output Current I
OH
VCC=2.7V
VOH=2V
-1.0 mA
Low Level Output Current I
OL
VCC=2.7V
VOL=0.4V
8mA
AC ELEC TRICAL CHARACTERISTICS (TA =+25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Period t
PERIOD
2 (tWI)ns2
Input Pulse Width t
WI
100% of
Tap Delay
ns 2
Input-to-Tap Output Delay t
PLH, tPHL
Table 1 ns
Output Rise or Fall Time t
OR, tOF
2.0
3.0
2.5
3.5
ns
ns
3
4
Power-up Time t
PU
100 ms
CAPACITANCE (TA =+25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
IN
10 pF
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DS1033
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TEST CONDITIONS
Ambient Temperature: 25°C ±=3°C
Supply Voltage (VCC): 3.3V ±=0.1V
Input Pulse:
High: 3.0V ±=0.1V
Low: 0.0V ±=0.1V
Source Impedance: 50Ω=max.
Rise and Fall Time: 3.0 ns max. - Measured between 0.6V and 2.4V.
Pulse Width: 500 ns
Pulse Period: 1 µs
Output Load Capacitance: 15 pF
Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
Note: The above conditions are for test only and do not restrict the devices under other data sheet
conditions.
TIMING DIAGRAM
NOTES:
1. All voltages are referenced to ground.
2. Pulse width and duty cycle specifications may be exceeded; however, accu racy will be application-
sensitive with respect to de-coupling, layout, etc.
3. V
CC
=3.3V ±=10%.
4. V
CC
=2.7V.
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DS1033
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TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI(Pulse Width): The elapsed time on the pulse between the 1.5 volt point on the leading edge and the
1.5 volt point on the trailing edge, or the 1.5 volt point on the trailing edge and the 1.5 volt point on the
leading edge.
t
RISE
(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge on the
input pulse.
t
PLH
(Time Delay, Rising): The elapsed time between the 1.5 volt point on the leading edge of the input
pulse and the 1.5 volt point on the leading edge of the output pulse.
t
PHL
(Time Delay, Falling): The elapsed time between the 1.5 volt point on the falling edge of the input
pulse and the 1.5 volt point on the falling edge of the output pulse.
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