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www.dalsemi.com
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DS1004
5-Tap High Speed
Silicon Delay Line
FEATURES
All-silicon timing circuit
Five delayed clock phases per input
Precise tap-to-tap nominal delay tolerances of
±0.75 and ±1 ns
Input-to-tap 1 delay of 5 ns
Nominal Delay tolerances of ±1.5 ns
Leading and trailing edge precision preserves
the input symmetry
CMOS design with TTL compatibility
Standard 8-pin DIP and 150 mil 8-pin SOIC
Vapor phase, IR and wave solderable
Available in Tape and Reel
PIN ASSIGNMENT
1
IN
IN
2
3
4
1
2
3
4
TAP 2
TAP 4
GND
DS1004M 8-Pin DIP (300-mil)
See Mech. Drawings Sectio
TAP 2
TAP 4
GND
DS1004Z 8-Pin SOIC (150-mil)
See Mech. Drawings Sectio
V
8
CC
TAP 1
7
TAP 3
6
5
TAP 5
8
V
CC
7
TAP 1
6
TAP 3
5
TAP 5
PIN DESCRIPTION
TAP 1-5 - TAP Output Number
V
CC
GND - Ground
IN - Input
- +5V Supply
DESCRIPTION
The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a
standard part family. The device is Dallas Semiconductor’s fastest 5-tap delay line. It is available in a
standard 8-pin DIP and 150 mil 8-pin mini-SOIC. The device features precise leading and trailing ed ge
accuracies and has the inherent reliability of an all-silicon delay line solution.
The DS1004 is specified for tap-to-tap tolerances as shown in Table 1. Each device has a minimum
input-to-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns.
See Table 1 for details. Input to Tap Tolerance over temperature and voltage is ±1.5 ns in addition to the
nominal delay tolerance. Nominal tap-to-tap tolerances range from ±0.75 ns to ±1.0 ns. Each output is
capable of driving up to 10 LS loads.
For customers needing non-standard delay values, the Late Package Program (LPP) is available.
Customers may contact Dallas Semiconductor at (972) 371–4348 for further details.
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DS1004
PART NUMBER TOLERANCE TABLE Table 1
PART
NUMBER
DS1004M-2 1.5 ns ±3.0 ns ±0.75 ns ±1.5 ns
DS1004M-3 1.5 ns ±3.0 ns ±0.75 ns ±1.5 ns
DS1004M-4 1.5 ns ±3.0 ns ±1.0 ns ±1.75 ns
DS1004M-5 1.5 ns ±3.0 ns ±1.0 ns ±1.75 ns
DS1004Z-2 1.5 ns ±3.0 ns ±0.75 ns ±1.5 ns
DS1004Z-3 1.5 ns ±3.0 ns ±0.75 ns ±1.5 ns
DS1004Z-4 1.5 ns ±3.0 ns ±1.0 ns ±1.75 ns
DS1004Z-5 1.5 ns ±3.0 ns ±1.0 ns ±1.75 ns
INPUT-TO-TAP TOLERANCE TAP-TO-TAP TOLERANCE
NOMINAL
1
OVER TEMP &
VOLTAGE
2
NOMINAL
1
OVER TEMP &
VOLTAGE
2
NOTES:
1. Nominal conditions are +25°C and VCC = +5.0V
2. Temperature and voltage variations cover the range from VCC=5.0V ±=5% and temperature range from
0°C to +70°C.
3. Delay accuracy for both leading and trailing edges.
PART NUMBER DELAY TABLE Table 2
PART
NUMBER
INPUT-TO-
TAP1
DS1004M-2 5 ns 7 ns 9 ns 11 ns 13 ns
DS1004M-3 5 ns 8 ns 11 ns 14 ns 17 ns
DS1004M-4 5 ns 9 ns 13 ns 17 ns 21 ns
DS1004M-5 5 ns 10 ns 15 ns 20 ns 25 ns
DS1004Z-2 5 ns 7 ns 9 ns 11 ns 13 ns
DS1004Z-3 5 ns 8 ns 11 ns 14 ns 17 ns
DS1004Z-4 5 ns 9 ns 13 ns 17 ns 21 ns
DS1004Z-5 5 ns 10 ns 15 ns 20 ns 25 ns
NOMINAL VALUES (FOR REFERENCE ONLY)
INPUT-TO-
TAP2
INPUT-TO-
TAP3
INPUT-TO-
TAP4
INPUT-TO-
TAP5
LOGIC DIAGRAM
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DS1004 TEST CIRCUIT Figure 1
DS1004
TEST SETUP DESCRIPTION
Figure 1 illustrates the hardware configuration used for measuring the timing parameters of the DS1004.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1004 output taps
are selected and connected to the interval counter by a VHF switch control unit. All measurements ar e
fully automated with each instrument controlled by the computer over an IEEE 488 bus.
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DS1004
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -1.0V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature See J-STD-020A Specification
Short Circuit Output Current 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ± 5%)
PARAMETER SYM TEST
CONDITION
Supply Voltage V
Active Current I
CC
CC
VCC=5.25V
Period=1 µs
High Level Input
V
IH
Voltage
Low Level Input
V
IL
Voltage
Input Leakage I
High Level Output
I
Current
Low Level Output
I
Current
I
OH
OL
0.0V ≤ VI ≤ V
VCC=4.75V
VOH=4V
VCC=4.75V
VOL=0.5V
CC
MIN TYP MAX UNITS NOTES
4.75 5.00 5.25 V 1
35 75 mA
2.2 VCC + 0.5 V 1
-0.5 0.8 V 1
-1.0 1.0 µA
-1.0 mA
12 mA
AC ELECTRICAL CH ARAC TERIST ICS (TA = 25°C; VCC = 5V ± 5%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Period t
PERIOD
Input Pulse Width t
Input to Tap 1
Output Delay
Tap-to-Tap Delays t
Output Rise or
Fall Time
Power-up Time t
WI
t
PLH
t
PHL
PLH
tOR,
t
OF
PU
,
4 (tWI)ns3
40% of Tap 5 t
PLH
ns 3
Table 1 ns 2
Table 1 ns 2
2.0 2.5 ns
100 ms
CAPACITANCE (TA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
IN
10 pF
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DS1004
NOTES:
1. All voltages are referenced to ground.
2. VCC=5V and 25°C. Delay accuracy on both the rising and falling edges within tolerances given in
Table 1.
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
TEST CONDITIONS
INPUT:
Ambient Temperature: 25°C ±=3°C
Supply Voltage (VCC): 5.0V ±=0.1V
Input Pulse: High = 3.0V ±=0.1V
Low = 0.0V ±=0.1V
Source Impedance: 50 ohm max.
Rise and Fall Time: 3.0 ns max. (measured between 0.6V and 2.4V)
Pulse Width: 500 ns
Pulse Period: 1 µs
Output Load
Capacitance: 15 pF
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS
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DS1004
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
t
RISE
input pulse.
t
(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
FALL
input pulse.
t
(Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
PLH
pulse and the 1.5V point on the leading edge of the output pulse.
t
(Time Delay, Falling): The elapsed time between the 1.5V point on the falling edge of the input
PHL
pulse and the 1.5V point on the falling edge of the output pulse.
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