Datasheet DS0026CN Datasheet (NSC)

DS0026
Dual High-Speed MOS Driver

DS0026 Dual High-Speed MOS Driver

February 2000

General Description

DS0026 is a low cost monolithic high speed two phase MOS
clock driver and interface circuit. Unique circuit design pro­vides both very high speed operation and the ability to drive
large capacitiveloads.The deviceaccepts standard TTLout­puts and converts themto MOS logic levels. The device may
be driven from standard 54/74 series and 54S/74S series
gates and flip-flops or from drivers such as the DS8830 or
DM7440. The DS0026 is intended for applications in which
the output pulse width is logically controlled; i.e., the output
pulse width is equal to the input pulse width.

The DS0026 is designed to fulfill a wide variety of MOS inter­face requirements. Information on the correct usage of the
DS0026 in these as well as other systems is included in the
application note AN-76.

Connection Diagrams (Top Views)

Dual-In-Line Package

Features

n Fast rise and fall times— 20 ns 1000 pF load
n High output swing —20V
n High output current drive—
n TTL compatible inputs
n High rep rate —5 to 10 MHz depending on power

dissipation

n Low power consumption in MOS “0” state— 2 mW
n Drives to 0.4V of GND for RAM address drive

±

1.5 amps

DS005853-2

Order Number DS0026CN

See NS Package Number N08E

© 2000 National Semiconductor Corporation DS005853 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

DS0026

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

+−V−

V

Differential Voltage 22V
Input Current 100 mA
Input Voltage (V

−V−) 5.5V

IN

Peak Output Current 1.5A

Electrical Characteristics (Notes 2, 3, 4)

=

*

Maximum Power Dissipation
25˚C 420mW

at T

A

Operating Temperature Range 0˚C to +70˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature

(Soldering, 10 sec.) 300˚C

Note:*Derate N08E package 9.3 mW/˚C for TAabove 25˚C.θJ

A

=

107˚C/W

Symbol Parameter Conditions Min Typ Max Units

−

V

IH

I

IH

V

IL

I

IL

V

OL

V

OH

I

CC(ON)

I

CC(OFF)

Logic “1” Input Voltage V
Logic “1” Input Current VIN−V
Logic “0” Input Voltage V
Logic “0” Input Current VIN−V
Logic “1” Output Voltage VIN−V
Logic “0” Output Voltage VIN−V

“ON” Supply Current
(one side on)

“OFF” Supply Current V+−V

=

0V 2 1.5 V

−

=

−

=

I

OH

V+−V

V

IN

2.4V 10 15 mA

0V 0.6 0.4 V

−

=

0V −3 −10 µA

−

−

=

−1mA

−

−

−

−V

=
=

=

20V, V

=

20V,

=

2.4V, I

0.4V, V

0V

=

1mA V

OL

≥ V++ 1.0V

SS

−

=

−V

IN

2.4V

V

+

− 1.0 V+−0.8 V

−

+0.7 V−+1.0 V

30 40 mA

10 100 µA

Switching Characteristics

=

(T

25˚C) (Notes 5, 6)

A

Symbol Parameter Conditions Min Typ Max Units

t

ON

t

OFF

t

r

t

f

Note 1: “Absolute Maximum Ratings”are those values beyond which the safety of the device cannot beguaranteed. Except for “Operating Temperature Range” they
are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics provides conditions for actual device operation.

Note 2: These specifications apply for V
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown

as max or min on absolute value basis.

Note 4: All typical values for T
Note 5: Rise and fall time are given for MOS logic levels; i.e., rise time is transition from logic “0” to logic “1” which is voltage fall.
Note 6: The high current transient (as high as 1.5A) through the resistance of the internal interconnecting V

the low state can appear as negative feedback to the input. If the external interconnecting lead from the driving circuit to V
resistance, it can subtract from the switching response.

Turn-On Delay

Turn-Off Delay

Rise Time

Fall Time

=

A

25˚C.

+−V−

(Figure 1)
(Figure 2)
(Figure 1)
(Figure 2)

(Figure 1),

(Note 5)

(Figure 2),

(Note 5)

(Figure 1),

(Note 5)

(Figure 2),

(Note 5)

=

10V to 20V, C

5 7.5 12 ns

11 ns
12 15 ns
13 ns

=

C

500 pF 15 18 ns

L

=

C

1000 pF 20 35 ns

L

=

C

500 pF 30 40 ns

L

=

C

1000 pF 36 50 ns

L

=

C

500 pF 12 16 ns

L

=

C

1000 pF 17 25 ns

L

=

C

500 pF 28 35 ns

L

=

C

1000 pF 31 40 ns

L

=

1000 pF, over the temperature range of 0˚C to +70˚C for the DS0026CN.

L

−

lead during the output transition from the high state to

−

is electrically long, or has significant dc

www.national.com 2

Typical VBBConnection

Typical Performance Characteristics

DS0026

DS005853-8

Input Current vs Input Voltage

DS005853-22

Rise Time vs Load
Capacitance

Supply Current vs Temperature

DS005853-23

Fall Time vs Load
Capacitance

Turn-On and Turn-Off Delay
vs Temperature

DS005853-24

DS005853-25

DS005853-26

www.national.com3

Typical Performance Characteristics (Continued)

DS0026

Recommended Input Coding
Capacitance

DS005853-27

Schematic Diagram

1/2 DS0026

DC Power (PDC)vs
Duty Cycle

DS005853-28

www.national.com 4

DS005853-10

AC Test Circuits and Switching Time Waveforms

DS005853-12

FIGURE 1.

DS0026

DS005853-13

DS005853-15

DS005853-14

FIGURE 2.

Typical Applications Application Hints

AC Coupled MOS Clock Driver

DS005853-16

DC Coupled RAM Memory Address or Precharge

Driver (Positive Supply Only)

DS005853-17

DRIVING THE MM5262 WITH THE
DS0026 CLOCK DRIVER

The clock signals for the MM5262 have three requirements
which have the potential of generating problems for the user.
These requirements, high speed, large voltage swing and
large capacitive loads, combine to provide ampleopportunity
for inductive ringing on clock lines, coupling clock signals to
other clocks and/or inputs and outputs and generating noise
on the power supplies.All of these problems have the poten­tial of causing the memory system to malfunction. Recogniz­ing the source and potential of these problems early in the
design of a memory system is the most critical step. The ob­ject here is to point out the source of these problems and
give a quantitative feel for their magnitude.

Line ringing comes from the fact that at a high enough fre­quency any line must be considered as a transmission line
with distributed inductance and capacitance. To see how
much ringing can be tolerated we must examine the clock
voltage specification.

Figure 3

in diagram form, with idealized ringing sketched in. The ring­ing of the clock about the V
the V

−1VOHis not maintained, at

SS

tion stored in the memory could be altered. Referring to

ure 1

, if the threshold voltage of a transistor were −1.3V, the

clock going to V

− 1 would mean that all the devices,

SS

whose gates are tied to that clock, would be only 300 mV
from turning on. The internal circuitry needs this noise mar­gin and from the functional description of the RAM it is easy
to see that turning a clock on at the wrong time can have di­sastrous results.

shows the clock specification,

level is particularly critical. If

SS

all

times, the informa-

Fig-

www.national.com5

Application Hints (Continued)

DS0026

FIGURE 3. Clock Waveform

Controlling theclock ringing is particularly difficult because of
the relative magnitude of the allowable ringing, compared to
magnitude of the transition. In this case it is 1V out of 20V or
only 5%. Ringing can be controlled by damping the clock
driver and minimizing the line inductance.

Damping the clock driver by placing a resistance in series
with its output is effective, but there is a limit since it also
slows downthe rise and fall time of theclock signal. Because
the typical clock driver can be much faster than the worst
case driver, the damping resistor serves the useful function
of limiting the minimum rise and fall time. This is very impor­tant because the faster the rise and fall times, the worse the
ringing problem becomes. The size of the damping resistor
varies because it is dependent on the details of the actual
application. It must be determined empirically. In practice a
resistance of 10Ω to 20Ω is usually optimum.

Limiting the inductance of the clock lines can be accom­plished by minimizing their length and by laying out the lines
such that the return current is closely coupled to the clock
lines. When minimizing the length of clock lines it is impor­tant to minimize the distance from the clock driver output to
the furthest point being driven. Because of this, memory
boards are usually designed with clock drivers in the center
of the memory array, rather than on one side, reducing the
maximum distance by a factor of 2.

Using multilayer printed circuit boards with clock lines sand­wiched between the V
the inductance of the clock lines. It also serves the function
of preventing the clocks from coupling noise into input and
output lines. Unfortunately multilayer printed circuit boards
are more expensive than two sided boards. The user must
make the decision as to the necessity of multilayer boards.
Suffice itto say here, thatreliable memory boards can bede­signed using two sided printed circuit boards.

and VSSpower plains minimizes

DD

DS005853-18

DS005853-19

FIGURE 4. Clock Waveforms (Voltage and Current)

Because of the amount of current that the clock driver must
supply to its capacitive load, the distribution of power to the
clock driver must be considered.

Figure 4

gives the idealized
voltage and current waveforms for a clock driver driving a
1000 pF capacitor with 20 ns rise and fall time.

As can be seen the current is significant. This current flows
in the V

and VSSpower lines.Any significant inductance in

DD

the lines will produce large voltage transients on the power
supplies. A bypass capacitor, as close as possible to the
clock driver, is helpful in minimizing this problem. This by­pass is most effectivewhen connected between the V
V

supplies. The size of the bypass capacitor depends on

DD

and

SS

the amount of capacitance being driven. Using a low induc­tance capacitor, such as a ceramic or silver mica, is most ef­fective. Another helpful technique is to run the V

DD

and V

SS

lines, tothe clock driver,adjacent to eachother. This tends to
reduce the lines inductance and therefore the magnitude of
the voltage transients.

While discussing the clock driver, it should be pointed out
that the DS0026 is a relatively low input impedance device.
It is possible to couple current noise into the input without
seeing a significant voltage. Since the noise is difficult to de­tect with an oscilloscope it is often overlooked.

Lastly, the clock lines must be considered as noise genera­tors.

Figure 5

pling capacitor, C

shows a clockcoupled through a parasitic cou-

, to eight data input lines being driven by

C

a 7404. Aparasitic lumped line inductance, L, is also shown.
Let us assume, for the sake of argument, that C

is1pFand

C

that the rise time of the clock is high enough to completely
isolate the clock transient from the 7404 because of the in­ductance, L.

www.national.com 6

Application Hints (Continued)

DS0026

tance could cause system malfunction, because a 7404
without apull up resistor has typically only 0.3Vof noise mar­gin in the “1” state at 25˚C. Of course it is stretching things to
assume that the inductance, L, completely isolates the clock
transient from the 7404. However, it does point out the need
to minimize inductance in input/output as well as clock lines.

The output is current, so it is more meaningful to examine
the current that is coupled througha1pFparasitic capaci­tance. The current would be:

DS005853-20

FIGURE 5. Clock Coupling

With a clock transition of 20V the magnitude of the voltage
generated across C

is:

L

This has been a hypothetical example to emphasize that
with 20V low rise/fall time transitions, parasitic elements can
not be neglected. In this example, 1 pF of parasitic capaci-

This exceeds the total output current swing so it is obviously
significant.

Clock coupling to inputs and outputs can be minimized by
using multilayer printed circuit boards, as mentioned previ­ously, physically isolating clock lines and/or running clock
lines at right angles to input/output lines. All of these tech­niques tend to minimize parasitic coupling capacitance from
the clocks to the signals in question.

In considering clock coupling it is also important to have a
detailed knowledge of the functional characteristics of the
device being used. As an example, for the MM5262, cou­pling noisefrom the φ2 clockto the address lines is of nopar­ticular consequence. On the other hand the address inputs
will be sensitive to noise coupled from φ1 clock.

www.national.com7

Packaging Information
Physical Dimensions

DS0026 Dual High-Speed MOS Driver

inches (millimeters) unless otherwise noted

Molded Dual-In-Line Package (N)

Order Number DS0026CN

NS Package Number N08E

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the

2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.

labeling, can be reasonably expected to result in a
significant injury to the user.

National Semiconductor
Corporation

Americas
Tel: [phone]
Fax: [phone]
Email: [e-mail]

www.national.com

National Semiconductor
Europe

Fax: [phone]

Email: [e-mail]
Deutsch Tel: [phone]
English Tel: [phone]
Français Tel: [phone]

National Semiconductor
Asia Pacific Customer
Response Group

Tel: [phone]
Fax: [phone]
Email: [e-mail]

National Semiconductor
Japan Ltd.

Tel: [phone]
Fax: [phone]

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.