Datasheet DP83848HSQ, DP83848H Datasheet (NSC)

DP83848H PHYTER® Mini - Extreme Temperature Single 10/100 Ethernet Transceiver

© 2006 National Semiconductor Corporation

www.national.com

DP83848H PHYTER® Mini - Extreme Temperature
Single 10/100 Ethernet Transceiver

September 2006

Features

• Low-power 3.3V, 0.18µm CMO S techn ol ogy

• 3.3V MAC Interface

• Auto-MDIX for 10/100 Mb/s

• Energy Detection Mode

• MII Interface and MII serial management interface (MDC

and MDIO)

• IEEE 802.3u Auto-Negotiation and Parallel Detection

• IEEE 802.3u ENDEC, 10BASE-T transceivers and filters

• IEEE 802.3u PCS, 100BASE-TX transceivers and filters

• Integrated ANSI X3.263 co mp lia nt TP-PM D ph ys ic al s ub -

layer with adaptive equalization and Baseline Wander
compensation

• Error-free Operation up to 137 meters

• ESD protection - 4KV Human body model

• LED support for Link

• Supports system clock from oscillator

• Single register access for complete PHY status

• 10/100 Mb/s packet BIST (Built in Self Test)

• 40 pin LLP package (6mm) x (6mm) x (0.8mm)

Applications

• Peripheral devices

• Mobile devices

• Factory and building automation

• Basestations

General Description

The DP83848H PHYTER® Mini Extreme addresses the
high quality, high reliability and small form factor required
for rugged operation in space sensitive and thermally
demanding environments. This device is ideally suited for
industrial and motor control, building/factory automation,
automotive and test equipment applications.

The DP83848H is designed from ground up for extreme
temperature performance, with a thermally efficient pack­age ensuring reliable operation over an operating range of

-40C to 125C. Rigorously tested at both low temperature
and high temperature extremes, the device is ideal for out­door environment s and dem anding factory floor co nditio ns.

The device offers performance beyond the IEEE specifica­tions, with superior interoperability and industry leading
performance. The DP83848H offers Auto-MDIX to remove
cabling complications, superior ESD protection of greater
than 4KV HBM for greater reliability, and superior cable
length operation (greater than 137m) to provide a high
level of performance in all applications.

A number of system cost-reducing features have been
integrated that are not commonly found in other Ethernet
Physical layer products (PHYs). For example, the
DP83848H offers a 25MHz clock out that eliminates the
need and hence the space and cost, of an additional
Media Access Control (MAC) clock source component.

DP83848H is offered in a small 6mm x 6mm LLP 40-pin
package.

System Diagram

PHYTER® is a registered trademark of National Semiconductor Corporation.

Status

10BASE-T

or

100BASE-TX

MII

Typical Ethernet Application

Magnetics

RJ-45

Clock

LED

DP83848H

10/100 Ethernet

Transceiver

Media Access Controller

MPU/CPU

Source

2 www.national.com

N

A

T

I

O

N

A

L

S

E

M

I

C

O

N

D

U

C

T

O

R

C

O

N

F

I

D

E

N

T

I

A

L

SERIAL

MANAGEMENT

TX_CLK

TXD[3:0]

TX_EN

MDIO

MDC

COL

CRS

RX_ER

RX_DV

RXD[3:0]

RX_CLK

Auto-Negotiation

State Machine

Clock

RX_DATA

RX_CLK

TX_DATA TX_CLK

REFERENCE CLOCK

TD±

RD±

LED

Generation

MII INTERFACE

Figure 1. DP83848H Functional Block Diagram

MII

Registers

Transmit Block

10BASE-T &

100BASE-TX

10BASE-T &

100BASE-TX

Receive Block

Auto-MDIX

DAC

ADC

LED

Driver

MII

3 www.national.com

DP83848H

Table of Contents

1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.2 MAC Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.6 Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.7 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.8 Special Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.9 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.10 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.1.1 Auto-Negotiation Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1.2 Auto-Negotiation Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.5 Enabling Auto-Negotiation via Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2 Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.3 PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.3.1 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.4.1 LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.2 LED Direct Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.6 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.7 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.0 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.1.1 Nibble-wide MII Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.2 Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.3 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 802.3u MII Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.2.1 Serial Management Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.2 Serial Management Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.3 Serial Management Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.0 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1.1 Code-group Encoding and Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.4 Binary to MLT-3 Convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.2.1 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.2 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.2.1 Digital Adaptive Equalization and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.2.2 Base Line Wander Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.3 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.4 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.5 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.6 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.7 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.8 Code-group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.9 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

www.national.com 4

DP83848H

4.2.10 100BASE-TX Link Integrity Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.11 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3 10BASE-T TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4.3.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.3 Collision Detection and SQE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.4 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.5 Normal Link Pulse Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.6 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.7 Automatic Link Polarity Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.0 Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.3 Clock In (X1) Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.4 Power Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.5 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.6 Energy Detect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

7.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

7.1.1 Basic Mode Control Register (BMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1.2 Basic Mode Status Register (BMSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1.3 PHY Identifier Register #1 (PHYIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1.4 PHY Identifier Register #2 (PHYIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1.5 Auto-Negotiation Advertisement Register (ANAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) . . . . . . . . . . . . . . . . 42

7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) . . . . . . . . . . . . . . . . . 43

7.1.8 Auto-Negotiate Expansion Register (ANER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.2 Extended Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

7.2.1 PHY Status Register (PHYSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.2 False Carrier Sense Counter Register (FCSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.2.3 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.2.4 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.2.5 LED Direct Control Register (LEDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2.6 PHY Control Register (PHYCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.2.7 10Base-T Status/Control Register (10BTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2.8 CD Test and BIST Extensions Register (CDCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.2.9 Energy Detect Control (EDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.1 DC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

8.2 AC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

8.2.1 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.2.3 MII Serial Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.2.4 100 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.2.5 100 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.2.6 100BASE-TX Transmit Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.2.7 100BASE-TX Transmit Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.2.9 100BASE-TX Receive Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.2.10 100BASE-TX Receive Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.2.13 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5 www.national.com

DP83848H

8.2.14 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.2.15 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.2.16 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.2.17 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2.18 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2.19 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.2.21 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.2.22 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.2.23 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.2.24 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.2.25 25 MHz_OUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6 www.national.com

DP83848H

List of Figures

Figure 1. DP83848H Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3. AN0 Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 5. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . .25

Figure 9. 100BASE-TX BLW Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10. 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 11. 10/100 Mb/s Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 12. Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 13. Power Feeback Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 www.national.com

DP83848H

List of Tables

Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 2. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 3. LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 4. Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 5. 4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 6. 25 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 7. 25 MHz Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 8. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 9. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 10. Basic Mode Control Register (BMCR), address 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 11. Basic Mode Status Register (BMSR), address 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 12. PHY Identifier Register #1 (PHYIDR1), address 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 13. PHY Identifier Register #2 (PHYIDR2), address 0x03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 14. Negotiation Advertisement Register (ANAR), address 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 15. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 . . . . . . . .42

Table 16. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 . . . . . . . . .43

Table 17. Auto-Negotiate Expansion Register (ANER), address 0x06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 18. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 . . . . . . . . . . . . . . . . . . . 44

Table 19. PHY Status Register (PHYSTS), address 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 20. False Carrier Sense Counter Register (FCSCR), address 0x14 . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 21. Receiver Error Counter Register (RECR), address 0x15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 22. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 . . . . . . . . . . . . . . . . . . . .48

Table 23. LED Direct Control Register (LEDCR), address 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 24. PHY Control Register (PHYCR), address 0x19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 25. 10Base-T Status/Control Register (10BTSCR), address 0x1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 26. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 27. Energy Detect Control (EDCR), address 0x1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

www.national.com 8

DP83848H

Pin Layout

PFBIN2
DGND
X1
X2
IOVDD33
MDC
MDIO
RESET_N
LED_LNK
25MHz_OUT

RBIAS

PFBOUT

AVDD33

AGND

PFBIN1

TD +

TD -

AGND

RD +

RD -

IOVDD33

TX_CLK

TX_EN

TXD_0
TXD_1
TXD_2

TXD_3
RESERVED
RESERVED
RESERVED

RX_CLK

RX_DV

CRS/LED_CFG

RX_ER/MDIX_EN

COL/PHYAD0

RXD_0/PHYAD1

RXD_1/PHYAD2

RXD_2/PHYAD3

RXD_3/PHYAD4

IOGND

1
2
3
4
5
6
7
8
9
10

20

19

18

17

16

15

14

13

12

11

30
29
28
27
26
25
24
23
22
21

31

32

33

34

35

36

37

38

39

40

Top View

Order Number DP83848H

NS Package Number NSQAU040

9 www.national.com

DP83848H

1.0 Pin Descriptions

The DP83848H pins are classified into the following inter­face categories (each interface is described in the sections
that follow):

— Serial Management Interface
— MAC Data Interface
— Clock Interface
— LED Interface
—Reset
— Strap Options
— 10/100 Mb/s PMD Interface
— Special Connect Pins
— Power and Ground pins

Note: Strapping pin option. Please see Se ction 1.6 for strap
definitions.

All DP83848H signal pins are I/O cells regardless of the
particular use. The defi nition s below defi ne the func tiona lity
of the I/O cells for each pin.

1.1 Serial Managemen t Interface

1.2 MAC Data Interface

Type: I Input
Type: O Output
Type: I/O Input/Output
Type: PD,PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins have weak in-

ternal pu ll-ups or pull- downs. If the default
strap value is needed to b e changed then an
external 2.2 kΩ resistor should be used.
Please see Section 1.6 for details.)

Signal Name Type Pin # Description

MDC I 25 MANAGEMENT DATA CLOCK: Synchronous clock to the M DIO

management data input/output serial interface which may be
asynchronous to transmit and receive clocks. The maximum clock
rate is 25 MHz with no minimum clock rate.

MDIO I/O 24 MANAGEMENT DATA I/O: Bi-dir ectional management instru c-

tion/data signal th at may be s ourc ed by th e st atio n m ana gem en t
entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.

Signal Name Type Pin # Description

TX_CLK O 2 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100

Mb/s mode or 2.5 MHz in 10 Mb/s mode de rived from t he 25 MHz
reference clock.

TX_EN I, PD 3 MII TRANSMIT ENABLE: Active high input indicates the pres-

ence of valid data inputs on TXD[3:0].
TXD_0
TXD_1

TXD_2
TXD_3

I

I, PD

4
5
6
7

MII TRANSMIT DATA: Transmit dat a MII input pins , TXD[3:0],

that accept data sync hronous to the TX_CL K (2.5 MHz in 10 Mb/s

mode or 25 MHz in 100 Mb/s mode).

RX_CLK O 31 MII RECEIVE CLOCK: Provides th e 25 MHz recover ed receive

clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
RX_DV O, PD 32 MII RECEIVE DATA VALID: Asserted high to indic ate tha t vali d

data is present on the corresponding RXD[3:0].
RX_ER S, O, PU 34 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK

to indicate that an invalid symbol has been detected within a re-

ceived packet in 100 Mb/s mode.
RXD_0
RXD_1
RXD_2

RXD_3

S, O, PD 36

37
38
39

MII RECEIVE DATA: Nibble wide receiv e data signals d riven syn-

chronously to the RX_CL K , 25 MH z for 1 00 M b/s mod e, 2. 5 MHz

for 10 Mb/s mode). RXD[3:0] signals contain valid data when

RX_DV is asserted.

CRS/LED_CFG S, O, PU 33 MII CARRIER SENSE: Asserted high to indicate the receive me-

dium is non-idle.

www.national.com 10

DP83848H

1.3 Clock Interface

1.4 LED Interface

See Table 3 for LED Mode Selection.

1.5 Reset

COL S, O, PU 35 MII COLLISION DETECT: Asserted high to indica te de tec t io n of

a collision condition (simultaneous transmit and receive activity)
in 10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Dup lex mode with hea rtbeat enabled t his
pin is also asserted f or a duration of a pproximately 1µs at the end
of transmission to indicate heartbeat (SQE test).

In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig­nal is always logic 0. There is no heartbeat function during 10
Mb/s full duplex operation.

Signal Name Type Pin # Description

Signal Name Type Pin # Description

X1 I 28 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock

reference input for t he DP83848H a nd must be c onnected to a 25
MHz 0.005% (+

50 ppm) clock source. The DP83848H supports
either an external crystal res onator connected across pins X1 and
X2, or an external CMOS-level oscillator source connected to pin
X1 only.

X2 O 27 CRYSTAL OUTPUT: This pin is the primary clock reference out-

put to connect to an external 25 MHz crystal resonator device.
This pin must be l eft unc on nec ted if an external CMOS osc il la t or
clock source is used.

25MHz_OUT O 21 25 MHz CLOCK OUTPUT:

This pin provides a 25 MHz clock output to the system.
This allows other devices to use the reference clock from the

DP83848H without requiring additional clock sources.

Signal Name Type Pin # Description

LED_LINK S, O, PU 22 LINK LED: In Mode 1, this pin indicates the status of the LINK.

The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2, this pin indicates trans mit and receive

activity in addition to the status of the Link. The LED will be ON
when Link is good. It will blink when the transmitter or receiver is
active.

Signal Name Type Pin # Description

RESET_N I, PU 23 RESET: Active Low input that initializes or re-initializes the

DP83848H. Asserting th is pin low for at least 1 µs will f orce a reset
process to occur. All internal registers will re-initialize to their de­fault states as specified fo r each bit in the Register Blo ck sectio n.
All strap options are re-initialized as well.

11 www.national.com

DP83848H

1.6 Strap Options

DP83848H uses many functional pins as strap options.
The values of these pins are sampled during reset and
used to strap the device into specific modes of operation.
The strap option pin assignments are defined below. The
functional pin name is indicated in parentheses.

A 2.2 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is
required, then there is no need for external pull-up or pull
down resistors. Since these pins may have alternate func­tions after reset is deasserted, they should not be con­nected directly to VCC or GND.

Signal Name Type Pin # Description

PHYAD0 (COL)
PHYAD1 (RXD_0)
PHYAD2 (RXD_1)
PHYAD3 (RXD_2)
PHYAD4 (RXD_3)

S, O, PU
S, O, PD

35
36
37
38
39

PHY ADDRESS [4:0]: The DP83848H provides five PHY ad­dress pins, the state of w hi ch ar e la tch ed in to th e PH YCTR L reg ­ister at system Hardware-Reset.

The DP83848H supports PHY Address strapping values 0
(<00000>) through 31 (<11111 >). A PHY Address of 0 puts the
part into the MII Isolate Mode. The MII isolate mod e must be se ­lected by strapping Phy Addres s 0; changing to Addres s 0 by reg­ister write will not p ut the Phy in the MII is olate mode. Plea se refer
to section 2.3 for additional information.

PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.

AN0 (LED_LINK) S, O, PU 22 This input pin controls the advertised operating mode of the

DP83848H accordin g to the followin g table. The value on thi s pin
is set by connecting it to GND (0) or V

CC

(1) through 2.2 kΩ resis-

tors. This pin should NEVER be connected directly to GND or

VCC.

The value set at this input is latched into the DP83848H at Hard­ware-Reset.

The float/pull-down status of this pin is latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset.

The default is 1 since this pin has an internal pull-up.

LED_CFG (CRS) S, O, PU 33 LED CONFIGURATION: This strapping option determines the

mode of operation of the LED pins . Default is Mode 1. Mode 1 and
Mode 2 can be controlled via the s trap opti on. All m odes are con­figurable via register ac cess.

SeeTable 3 for LED Mode Selection.

MDIX_EN (RX_ER) S, O, PU 34 MDIX ENABLE: Default is to enable MDIX. This strapping option

disables Auto-MDIX. An external pull-down will disable Auto­MDIX mode.

AN0 Advertised Mode

0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

www.national.com 12

DP83848H

1.7 10 Mb/s and 100 Mb/s PMD Interface

1.8 Special Connections

1.9 Power Supply Pins

Signal Name Type Pin # Description

TD-, TD+ I/O 14, 15 Differential common driver transmit output (PMD Output Pair).

These differential outputs are automatically configured to either
10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of operati on, this pair can be used as th e Re­ceive Input pair.

These pins require 3.3V bias for operation.

RD-, RD+ I/O 11, 12 Differential receive input (PMD Input Pair). These differential in-

puts are automatically configured to accept either 100BASE-TX
or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the
Transmit Output pair.

These pins require 3.3V bias for operation.

Signal Name Type Pin # Description

RBIAS I 20 Bias Resist or Con nectio n. A 4 .87 kΩ 1% resistor should be con-

nected from RBIAS to GND.

PFBOUT O 19 Power Feedback Output. Parallel caps, 10µ F (Tantalum pre-

ferred) and 0.1µF, should be placed close to the PFBOUT. Con­nect this pin to PFBIN1 (pin 16) and PFBIN2 (pin 30). See
Section 5.4 for proper placement pin.

PFBIN1
PFBIN2

I1630Power Feedback Input. These pins are fed with power from

PFBOUT pi n. A small capaci tor of 0.1µF should be connected
close to each pin.

Note: Do not supply power to these pins other than from
PFBOUT.

RESERVED I/O 8,9,10 RESERVED: These pins must be left unconnected.

Signal Name Pin # Description

IOVDD33 1, 26 I/O 3.3V Supply
IOGND 40 I/O Ground
DGND 29 Digital Ground
AVDD33 18 Analog 3.3V Supply
AGND 13, 17 Analog Ground

13 www.national.com

DP83848H

1.10 Package Pin Assignments

NSQAu040

Pin #

Pin Name

1IO_VDD
2TX_CLK
3 TX_EN
4TXD_0
5TXD_1
6TXD_2
7TXD_3
8 RESERVED

9 RESERVED
10 RESERVED
11 RD­12 RD+
13 AGND
14 TD ­15 TD +
16 PFBIN1
17 AGND
18 AVDD33
19 PFBOUT
20 RBIAS
21 25MHz_OUT
22 LED_LINK/AN0
23 RESET_N
24 MDIO
25 MDC
26 IOVDD33
27 X2
28 X1
29 DGND
30 PFBIN2
31 RX_CLK
32 RX_DV
33 CRS/LED_CFG
34 RX_ER/MDIX_EN
35 COL/PHYAD0
36 RXD_0/PHYAD1
37 RXD_1/PHYAD2
38 RXD_2/PHYAD3
39 RXD_3/PHYAD4
40 IOGND

www.national.com 14

DP83848T

2.0 Configuration

This section include s infor mat ion on t he vari ous co nfigura ­tion options available with the DP83848H. The configura­tion options described below include:

— Auto-Negotiation
— PHY Address and LED
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
—BIST

2.1 Auto-Negotiation

The Auto-N egotiation fu nction provid es a mechanism for
exchanging configuration information between two ends
of a link segment and automatically selecting the highest
performance mode of operation supported by both
devices. Fast Link Pulse (FLP) Bursts provide the signal­ling used to communicate Auto-Negotiation abilities
between two devices at each end of a link segment. For
further detail regarding Auto-Negotiation, refer to Clause
28 of the IEEE 802.3u specification. The DP83848H sup­ports four different Ethernet protocols (10 Mb/s Half
Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and
100 Mb/s Full Duplex), so the inclusion of Auto-Negotia­tion ensures that the highest performance protocol will be
selected based on the advertised ability of the Link Part­ner. The Auto-Negotiation function within the DP83848H
can be controlled either by internal register access or by
the use of the AN0 pin.

2.1.1 Auto-Negotiation Pin Control

The state of AN0 determine s the spe cif ic mode adverti se d
by DP83848H as given in Table 1. The state of AN 0 , upo n
power-up/reset, determines the state of bits [8:5] of the
ANAR register.

The Auto-Negotiation function selected at power-up or
reset can be changed at any time by writing to the Basic
Mode Control Register (BMCR) at address 0x00h

2.1.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83848H trans­mits the abilities programmed into the Auto-Negotiation
Advertisement register (ANAR) at address 04h via FLP
Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half­Duplex, and Full Duplex modes may be selected.

Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)

— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h

provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is dis­abled, the Speed Selection bit in the BMCR controls
switching between 10 Mb/s or 100 Mb/s operation, and
the Duplex Mode bit controls switching between full
duplex operation and half duplex operation. The Speed
Selection and Duplex Mode bits have no effect on the
mode of operation when the Auto-Negotiation Enable bit
is set.

The Link Speed can be examined through the PHY Status
Register (PHYSTS) at address 10h after a Link is
achieved.

The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotia­tion ability, and Extended Register Capability. These bits
are permanently set to indicate the full functionality of the
DP83848H (only the 100BASE-T4 bit is not set since the
DP83848H does not support that function).

The BMSR also provides status on:
— Completion of Auto-Negotiation
— Occurence of a remote fault as advertised by the Link

Partner
— Establishment of a valid link
— Support for Management Frame Preamble suppr ession
The Auto-Negotiation Advertisement Register (ANAR)

indicates the Auto-Neg otia tio n ab ili ties to be advertised by
the DP83848H. All available abilities are transmitted by
default, but any ability can be s uppressed by writing to the
ANAR. Updating the ANAR to suppress an ability is one
way for a management ag en t to cha nge (restrict) the tech­nology that is used.

The Auto-Negotiation Link Partner Ability Register
(ANLPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indi­cates additional Auto-Negotiation status. The ANER pro­vides status on:

— Occurance of a Parallel Detect Fault
— Next Page function support by the Link Partner
— Next page support function by DP83848H
— Reception of the current page that is exchanged by

Auto-Negotiation
— Auto-Negotiation support by the Link Partner

Table 1. Auto-Negotiation Modes

AN0 Advertised Mode

0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

15 www.national.com

DP83848H

2.1.3 Auto-Negotiation Parall el Detection

The DP83848H supports the Parallel Detection function as
defined in the IEEE 802.3u specifi ca tio n. Para lle l Detec tion
requires both the 10 Mb/s and 100 Mb/s receivers to moni­tor the receive signal and report link status to the Auto­Negotiation function. Auto-Negotiation uses this informa­tion to configure th e correct t echno logy i n the e vent that th e
Link Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASE­T PMAs recognize as valid link signa ls .

If the DP83848H completes Auto-Negotiation as a result of
Parallel Detection, bit 5 or bit 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may deter­mine that negotiation completed via Parallel Detection by
reading a zero in the Link Partn er Au to-Neg oti ati on Ab le b it
once the Auto-Negotiatio n Com pl ete b it i s s et. I f co nfi gure d
for parallel detect mode and any condition other than a sin­gle good link occurs then the parallel detect fault bit will be
set.

2.1.4 Auto-Negotiat ion Restart

Once Auto-Negotiation has completed, it may be restarted
at any time by setting bit 9 (Res tart Auto-Ne gotiat ion) of th e
BMCR to one. If the mode confi gured b y a su ccessfu l Auto­Negotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configu­ration for the link. This function ensures that a valid config­uration is maintained if the cable becomes disconnected.

A renegotiation requ es t fro m any en tity, such as a manage­ment agent, will cause the DP83848H to halt any transmit
data and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83848H will resume Auto-Negotiation after the
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.

2.1.5 Enabling Auto-Negotiation via Software

It is important t o no te t hat if the DP83848H has be en initial­ized upon power-up as a non-auto-negotiating device
(forced technology), and it is then requ ire d that Auto-Nego­tiation or re-Auto-Negotiation be initiated via software,
bit 12 (Auto-Negotiation Enable) of the Basic Mode Control
Register (BMCR) must first be cleared and then set for any
Auto-Negotiation function to take effect.

2.1.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately
2-3 seconds to co mp let e. In addition, Auto-Negotia tio n w i th
next page should take approximately 2-3 seconds to com­plete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full
description of the individual timers related to Auto-Negotia­tion.

2.2 Auto-MDIX

When enabled, this function utilizes Auto-Negotiation to
determine the proper configuration for transmission and
reception of data and subsequently selects the appropriate
MDI pair for MD I/ MD IX o per a ti on. T h e fu nc t io n us es a r an ­dom seed to control switching of the crossover circuitry.
This implementati on co mpl ie s with the corres po ndi ng IEEE

802.3 Auto-Negotiation and Crossover Specifications.
Auto-MDIX is enabled by default and can be configu r ed vi a

strap or via PHYCR (0x19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be

enabled in forcing crossover of the MDI pairs. Forced
crossover can be achieved through the FORCE_MDIX bit,
bit 14 of PHYCR (0x19h) register.

Note: Auto-MDIX will not work in a forced mode of opera­tion.

www.national.com 16

DP83848T

2.3 PHY Address

The 5 PHY address inputs pins are shared with the
RXD[3:0] pins and COL pin as shown below.

The DP83848 H can be set to res pond to an y of 32 po ssi­ble PHY addresses via strap pins. The information is
latched into the PHYCR register (address 19h, bits [4:0])
at device power-up and hardware reset. The PHY
Address pins are shared with the RXD and COL pins.
Each DP83848H or port sharin g an MD I O bu s in a syst em
must have a unique physical address.

The DP83848H support s PHY Address strapping values 0
(<00000>) through 31 (<11111>). S trapp in g PHY Ad dress
0 puts the p art into I solate Mode . It s hould al so be note d
that selecting PHY Address 0 via an MDIO write to
PHYCR will not put the device in Isolate Mode. See
Section 2.3.1 for more information.

For further detail relating to the latch-in timing require­ments of the PHY Address pins, as well as the oth er hard ­ware configuration pins, refer to the Reset summary in
Section 6.0.

Since the PHYAD[0] pin has weak internal pull-up resistor
and PHYAD[4:1] pins have weak internal pull-down resis­tors, the default setting for the PHY address is 00001
(01h).

Refer to Figure 2 for an example of a PHYAD connection
to external components. In this example, the PHYAD
strapping results in address 00011 (03h).

2.3.1 MII Isolate Mode

The DP83848H can be put into MII Isolate mode by writ­ing to bit 10 of the BMCR register or by strapping in Phys­ical Address 0. It should be noted that selecting Physical
Address 0 via an MDIO write to PHYCR will not put the
device in the MII isolate mode.

When in the MII isolate mode, the DP83848H does not
respond to packet dat a p resent a t TXD[3:0], T X_EN in put s
and presents a high imp edanc e on the TX_C LK, RX_ CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When
in Isolate mode, the DP83848H will continue to respond to
all management transactions.

While in Isolate mode, the PMD output pair will not trans­mit packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.

The DP83848 H can Auto -Nego tiate or parall el dete ct to a
specific technology depending on the receive signal at the
PMD input pair. A valid link can be established for the
receiver even when the DP83848H is in Isolate mode.

Table 2. PHY Address Mapping

Pin # PHYAD Function RXD Function

35 PHYAD0 COL
36 PHYAD1 RXD_0
37 PHYAD2 RXD_1
38 PHYAD3 RXD_2
39 PHYAD4 RXD_3

Figure 2. PHYAD Strapping Example

COL

RXD_0

RXD_1

RXD_2

RXD_3

VCC

2.2kΩ

PHYAD0 = 1

PHYAD1 = 1

PHYAD2 = 0PHY AD3 = 0

PHYAD4= 0

17 www.national.com

DP83848H

2.4 LED Interface

The DP83848H supports a configurable Light Emitting
Diode (LED) pin for configuring the link. The PHY Control
Register (PHYCR) for the LED can also be selected
through address 19h, bit [5].

See Table 3 for LED Mode selection.

The LED_LINK pin in Mode 1 indicates the link status of
the port. In 100BASE-T mode, link is established as a
result of input receive amplitude compliant with the TP­PMD specifications which will result in internal generation
of signal detect. A 10 Mb/s Link is est abli shed as a result of
the reception of at least seven consecutive normal Link
Pulses or the reception of a valid 10BASE-T packet. This
will cause the as se rtion of LED_LINK. L E D_LIN K w il l d ea s­sert in accordance with the Link Loss Timer as specified in
the IEEE 802.3 specification.

The LED_LINK p in in Mo de 1 w ill be OF F w h en no LI NK is
present.

The LED_LINK pin in Mode 2 will be ON to indicate Link is
good and BLINK to indicate activity is present on either
transmit or receive activity.

Since the LED_LINK pin is also used as a strap option, the
polarity of the LED is dependent on whether the pin is
pulled up or down.

2.4.1 LED

Since the Auto-Negotiation (AN0) strap option shares the
LED_LINK output pin, the external components required
for strapping and LED usage must be considered in order
to avoid contention.

Specifically, when the LED output is used to drive the LED
directly, the active state of the output driver is dependent
on the logic level sampled by the AN0 input upon power­up/reset. For example, if the AN0 input is resistively pulled
low then the corresponding output will be configured as an
active high driver. Conversely, if the AN0 input is resistively
pulled high, then the corresponding output will be config­ured as an active low driver.

Refer to Figure 3 for an example of AN0 connection to
external components. In this example, the AN0 strapping
results in Auto-Negotiation with 10/100 Half/Full-Duplex
advertised.

The adaptive nature of the LED output helps to simplify
potential implementation issues of this dual purpose pin..

2.4.2 LED Direct Control

The DP83848H provides another option to directly control
thel LED output through the LED Direct Control Register
(LEDCR), address 18h. The register does not provide read
access to the LED.

Table 3. LED Mode Select

Mode LED_CFG[0]

(bit 5)

or (pin40)

LED_LINK

1 1 ON for Good Link

OFF for No Link

2 0 ON for Good Link

BLINK for Activity

LED_LINK

VCC

110Ω

AN0 = 1

2.2kΩ

Figure 3. AN0 Strapping and LED Loading Example

www.national.com 18

DP83848T

2.5 Half Duplex vs. Full Duplex

The DP83848H supports both half and full duplex opera­tion at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex relies on th e CSMA/CD pro tocol to handle col­lisions and network access. In Half-Duplex mode, CRS
responds to both transmit and receive activity in order to
maintain compliance with the IEEE 802.3 specification.

Since the DP83848H is designed to support simultaneous
transmit and receive ac tivity it is cap abl e of sup porting full­duplex switched applications with a throughput of up to
200 Mb/s per port when operating in 100BASE-TX mode.
Because the CSMA/CD protocol does not apply to full­duplex operation, the DP83848H disables its own internal
collision sensing and reporting functions and modifies the
behavior of Carrier Sense (CRS) such that it indicates
only receive activity. This allows a full-duplex capable
MAC to operate properly.

All modes of operation (100BASE-TX and 10BASE- T) ca n
run either half-duplex or full-duplex. Additionally, other
than CRS and Collision rep orti ng, al l rem ai nin g MII signal­ing remains the same regardless of the selected duplex
mode.

It is important to understand that while Auto-Negotiation
with the use of Fast Link Pulse code words can interpret
and configure to full-duplex operation, parallel detection
can not recognize the difference between full and half­duplex from a fixed 10 Mb/s or 100 Mb/s link partner over
twisted pair. As specif ied in the 802.3u specification , if a
far-end link partner is configured to a forced full duplex
100BASE-TX ability, the parallel detection state machine
in the partner would be unable to detect the full duplex
capability of the far-end link partner. This link segment
would negotiate to a half duplex 100BASE-TX configura­tion (same scenario for 10 Mb/s).

2.6 Internal Loopback

The DP83848H includes a Loopback Test mode for facili­tating system diagnostics. The Loopback mode is
selected through bit 14 (Loopback) of the Basic Mode
Control Register (BMCR). Writing 1 to this bit enables MII
transmit data to be routed to the MII receive outputs.
Loopback status may be checked in bit 3 of the PHY Sta­tus Register (PHYSTS). While in Loop bac k m ode the data
will not be transmitted onto the media. To ensure that the

desired operating mode is maintained, Auto-Negotiation
should be disabled before selecting the Loopback mode.

2.7 BIST

The DP83848H incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diag­nostics. The BIST circuit can be utilized to test the integ­rity of the transmit and receive data paths. BIST testing
can be performed with the part in the internal loopback
mode or externally looped back using a loopback cable
fixture.

The BIST is implemented with independent transmit and
receive paths, with the transmit block generating a contin­uous stream of a pseudo ran dom seq uen ce . The us er ca n
select a 9 bit or 15 bit pseudo random sequence from the
PSR_15 bit in the PHY Control Register (PHYCR). The
received data is compared to the generated pseudo-ran­dom data by the BIST Linear Feedback Shift Register
(LFSR) to determine the BIST pass/fail status.

The pass/fail status of the BIST is stored in the BIST sta­tus bit in the PHYCR register. The status bit defaults to 0
(BIST fail) and will transition on a successful comparison.
If an error (mis-compare) occurs, the status bit is latched
and is cleared upon a subsequent write to the Start/Stop
bit.

For transmit VOD testing, the Packet BIST Continuous
Mode can be used to allow continuous data transmission,
setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).

The number of BIST errors can be monitored through the
BIST Error Count in the CDCTRL1 (0x1Bh), bits [15:8].

19 www.national.com

DP83848H

3.0 Functional Description

The DP83848H supports MII mode of operation using the
MII interface pins. The MII mode uses 25 MHz clock.

In the MII mode, the IEEE 802.3 serial management inter­face is operational for device configuration and status. The
serial management interface of the MII allows for the con­figuration and control of multiple PHY devices, gathering of
status, error information, and the determination of the type
and capabilities of the attached PHY(s).

3.1 MII Interface

The DP83848H incorporates the Media Independent Inter­face (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describes the nibble wide MII data interface.

The nibble wide MII data interface c ons is t s of a receive bus
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC).

3.1.1 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface includes a
dedicated recei ve bu s an d a d edicated transmit b us . These
two data buses, along with various control and status sig­nals, allow for the simultaneous exchange of data between
the DP83848H and the upper layer agent (MAC).

The receive interface consists of a nibble wide data bus
RXD[3:0], a receive error signal RX_ER, a receive data
valid flag RX_DV, and a receive clock RX_CLK for syn­chronous transfer of the data. The receive clock operates
at either 2.5 MHz to su pport 10 Mb/s operation mo des or at
25 MHz to support 100 Mb/s operational modes.

The transmit interface consists of a nibble wide data bus
TXD[3:0], a transmit enable control signal TX_EN, and a
transmit cloc k TX_CL K which runs at ei ther 2. 5 MHz or 25
MHz.

Additionally, the MII includes the carrier sense signal CRS,
as well as a collision detect signal COL. The CRS signal
asserts to ind icate the re ception of d ata from the ne twork
or as a function of transmit data in Half Duplex mode. The
COL signal asse rt s as an ind ic atio n of a collision which can
occur during half-duplex operation when both a transmit
and receive operation occur simultaneously.

3.1.2 Collision Detect

For Half Duplex, a 10BASE-T or 100BASE-TX collision is
detected when the receive and transmit channels are
active simu ltaneously. Collisions are reported by the COL
signal on the MII.

If the DP83848H is transmitting in 10 Mb/s mode when a
collision is dete ct ed, the c ollision is not repo rted un til s eve n
bits have been received while in the collision state. This
prevents a collision being reported incorrectly due to noise
on the network. The COL signal remains set for the dura­tion of the collision.

If a collision occ urs du ring a rec eiv e o pera tio n, it is immedi­ately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1µs after the transmission of
each packet, a Si gn al Q u ali ty Error (SQE) signal of approx ­imately 10 bit times is generated (internally) to indicate
successful transmiss io n. SQ E is repo rted as a pul se on th e
COL signal of the MII.

3.1.3 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity,
once valid data is detected via the squelch function during
10 Mb/s operation. During 100 Mb/s operation CRS is
asserted when a valid link (SD) and two non-contiguous
zeros are detected on the line.

For 10 or 100 Mb/s Half Duple x op era tio n, C RS is a sserte d
during either packet trans mission or re ception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.

CRS is deasserted following an end of packet.

3.2 802.3u MII Serial Management Interface

3.2.1 Serial Management Register Access

The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are acces­sible through the management interface pins MDC and
MDIO. The DP83848H implements all the required MII reg­isters as well as several optional registers. These registers
are fully described in Sect ion 7.0. A description of the serial
management access protocol follows.

3.2.2 Serial Management Access Protocol

The serial control interface consists of two pins, Manage­ment Data Clock (MDC) and Management Data Input/Out­put (MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame for­mat is shown below in Table 4.

The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during IDLE and turnaro und, will pull M DIO hi gh. In o rder to
initialize the MDIO int erface , the st atio n manag ement entit y
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83848H with a sequence that can be used
to establish sy nchr oniz ati on. Th is pr eamb le may be gene r­ated either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pull-up resis­tor to pull the MDIO pin high during which time 32 MDC
clock cycles are provided. In addition, 32 MDC clock cycles
should be used to re-sync the device if an invalid start,
opcode, or turnaround bit is detected.

The DP83848H waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83848H serial management port has been ini­tialized no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.

The St art co de is in dic ate d by a <01> p atte rn. Th is assures
the MDIO line transitions from the default idle line state.

www.national.com 20

DP83848T

Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid
contention during a read transaction, no device shall
actively drive the MDIO signal during the first bit of Turn­around. The addressed DP83848H drives the MDIO with
a zero for the second bit of turnaround and follows this
with the required data. Figure 4 shows the timing relation­ship between MDC and the MDIO as driven/received by
the Station (STA) and the DP83848H (PHY) for a typical
register read access.

For write transactions, the station management entity
writes data to the addressed DP83848H thus eliminating
the requirement for MDIO Turnaround. The Turnaround
time is filled by the management entity by inserting <10>.
Figure 5 shows the timing relationship for a typical MII
register write access.

3.2.3 Serial Management Preamble Suppression

The DP83848H supports a Preamble S uppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, addre ss 01 h.) If the station mana gem en t
entity (i.e. MAC or other management controller) deter­mines that all PHYs in the system support Preamble Sup­pression by returning a one in this bit, then the station
management entity need not generate preamble for each
management transaction.

The DP83848H requires a single initializa tion sequence of
32 bits of preamble following hardware/software reset.
This requirement is generally met by the mandatory pull­up resistor on MDIO in conjunction with a continuous
MDC, or the management access made to determine
whether Preamble Suppression is supported.

While the DP83848H requires an initial preamble
sequence of 32 bits for management initialization, it does
not require a full 32-bit sequence between each subse­quent transaction. A minimum of one idle bit between
management transactions is required as specified in the
IEEE 802.3u specification.

Table 4. Typical MDIO Frame Format

MII Management

Serial Protocol

<idle><start><op code><device addr><reg addr><turnaround><data><idle>

Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>

Figure 4. Typical MDC/MDIO Read Operation

Figure 5. Typical MDC/MDIO Write Operation

MDC

MDIO

00011 110000000

(STA)

Idle Start

Opcode

(Read)

PHY Address

(PHYAD = 0Ch)

Register Address

(00h = BMCR)

TA

Register Data

Z

MDIO

(PHY)

Z

Z

Z

0 0 011000100000000

Z

Idle

Z

Z

MDC

MDIO

00011110000000

(STA)

Idle Start

Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

Register Address

(00h = BMCR)

TA

Register Data

Z

0 0 0 000 00000000

Z

Idle

1000

ZZ

21 www.national.com

DP83848H

4.0 Architecture

This section describes the operations within each trans­ceiver module, 100BASE-TX and 10BASE-T. Each opera­tion consists of several functional blocks and described in
the following:

— 100BASE-TX Transmitter
— 100BASE-TX Receiver
— 10BASE-T Transceiver Module

4.1 100BASE-TX TRANSMITTER

The 100BASE-TX transmitter consists of several functional
blocks which conver t sync hronous 4-bit ni bble d at a, as p ro­vided by the MII, to a scrambled MLT-3 125 Mb/s serial
data stream. Because the 100BASE-TX TP-PMD is inte­grated, the differential output pins, PMD Output Pair, can
be directly routed to the magnetics.

The block diagram in Figure 6. provides an overview of
each functional block within the 100BASE-TX transmit sec­tion.

The Transmitter section consists of the following functional
blocks:

— Code-group Encoder and Injection block
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
The bypass option for the functional blocks within the

100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The
DP83848H implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Stan­dard, Clause 24.

Figure 6. 100BASE-TX Transmit Block Diagram

4B5B CODE-GROUP

ENCODER &

INJECTOR

SCRAMBLER

NRZ TO NRZI

ENCODER

5B PARALLEL

TO SERIAL

PMD OUTPUT PAIR

TX_CLK

TXD[3:0] /

TX_EN

BINARY TO

MLT-3 /

COMMON

DRIVER

125MHZ CLOCK

BP_SCR

MUX

100BASE-TX

LOOPBACK

MLT[1:0]

DIVIDE

BY 5

www.national.com 22

DP83848T

Table 5. 4B5B Code-Group Encoding/Decoding

DATA CODES

0 11110 0000
1 01001 0001
2 10100 0010
3 10101 0011
4 01010 0100
5 01011 0101
6 01110 0110
7 01111 0111
8 10010 1000

9 10011 1001
A 10110 1010
B 10111 1011
C 11010 1100
D 11011 1101
E 11100 1110
F 11101 1111

IDLE AND CONTROL CODES

H 00100 HALT code-group - Error code

I 11111 Inter-Packet IDLE - 0000 (

Note 1)

J 11000 First Start of Packet - 0101 (Note 1)
K 10001 Second Start of Packet - 0101 (Note 1)
T 01101 First End of Packet - 0000 (Note 1)
R 00111 Second End of Packet - 0000 (Note 1)

INVALID CODES

V 00000
V 00001
V 00010
V 00011
V 00101
V 00110
V 01000
V 01100

Note: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER as­serted.

23 www.national.com

DP83848H

4.1.1 Code-group Encoding and Injection

The code-group encoder converts 4-bit (4B) nibble data
generated by the MAC into 5-bit (5B) code-groups for
transmission. This conversion is required to allow control
data to be combined with packet data code-groups. Refer
to Table 5 for 4B to 5B code-group mapping details.

The code-group encoder substitutes the first 8-bits of the
MAC preamble with a J/K code-group pair (11000 10001)
upon transmission. The code-group encoder continues to
replace subsequent 4B preamble and data nibbles with
corresponding 5B code-groups. At the end of the transmit
packet, upon the deassertion of Transmit Enable signal
from the MAC, the code-group encoder injects the T/R
code-group pair (01101 00111) indicating the end of the
frame.

After the T/R code-group pair, the code-group encoder
continuously injects IDLEs into the transmit data stream
until the next transmit packet is detected (reassertion of
Transmit Enable).

4.1.2 Scrambler

The scrambler is required to control the radiated emissions
at the media connector and on the twisted pair cable (for
100BASE-TX applications). By scrambling the data, the
total energy launched onto the cable is randomly distrib­uted over a wide frequency range. Without the scrambler,
energy levels at the PMD and on the cable could peak
beyond FCC limitations at frequencies related to repeating
5B sequences (i.e., continuous transmission of IDLEs).

The scrambler is configured as a closed loop linear feed­back shift register (LFSR) with an 11-bit polynomial. The
output of the closed loop LFSR is X-ORd with the serial
NRZ data from the code-group encoder. The result is a
scrambled data stream with sufficient randomization to
decrease radiated emissions at certain frequencies by as
much as 20 dB. The DP83848H uses the PHY_ID (pins
PHYAD [4:0]) to set a unique seed value.

4.1.3 NRZ to NRZI Encoder

After the transmit data stream has been serialized and
scrambled, the data must be NRZI encoded in order to
comply with the TP-PMD standard for 100BASE-TX trans­mission over Category-5 Unshielded twisted pair cable.

4.1.4 Binary to MLT-3 Convertor

The Binary to MLT-3 conversion is accomplished by con­verting the serial binary data stream output from the NRZI
encoder into two binary data streams with alternately
phased logic one events. These two binary streams are
then fed to the twisted pair output driver which convert s the
voltage to current and alternately drives either side of the

transmit transformer primary winding, resulting in a MLT-3
signal.

The 100BASE-TX MLT-3 signal sourced by the PMD Out­put Pair common driver is slew rate controlled. This should
be considered when selecting AC coupling magnetics to
ensure TP-PMD Standard compliant transition times (3 ns
< Tr < 5 ns).

The 100BASE-TX transmit TP-PMD function within the
DP83848H is capable of sourcing only MLT-3 encoded
data. Binary output from the PMD Output Pair is not possi­ble in 100 Mb/s mode.

4.2 100BASE-TX RECEIVER

The 100BASE-TX receiver consists of several functional
blocks which convert the scrambled MLT-3 125 Mb/s serial
data stream to synchronous 4-bit nibble data that is pro­vided to the MII. Because the 100BASE-TX TP-PMD is
integrated, the differential input pins, RD±, can be direct ly
routed from the AC coupling magnetics.

See Figure 7 for a block diagram of the 100BASE-TX
receive function. This provides an overview of each func­tional block within the 100BASE-TX receive section.

The Receive section consists of the following functional
blocks:

— Analog Front End
— Digital Signal Processor
— Signal Detect
— MLT-3 to Binary Decoder
— NRZI to NRZ Decoder
— Serial to Parallel
— Descrambler
— Code Group Alignment
—4B/5B Decoder
— Link Integrity Monitor
— Bad SSD Detection

4.2.1 Analog Front End

In addition to the Digital Equalization and Gain Control, the
DP83848H includes Analog Equalization and Gain Control
in the Analog Front End. The Analog Equalization reduces
the amount of Digital Equalization required in the DSP.

4.2.2 Digital Signal Processor

The Digital Signal Processor includes Adaptive Equaliza­tion with Gain Control and Base Line Wander Compensa­tion.

www.national.com 24

DP83848T

4B/5B DECODER

DESCRAMBLER

MLT - 3 TO BINARY

DECODER

RX_CLK RXD[3:0] / RX_ER

NRZI TO NRZ

DECODER

CODE GROUP

ALIGNMENT

SERIAL TO

PARALLEL

RX_DV/CRS

RX_DAT A VALID

SSD DETECT

RD +/−

SIGNAL

DETECT

LINK

INTEGRITY

MONITOR

DIGITAL

SIGNAL

PROCESSOR

ANALOG

FRONT

END

Figure 7. 100BASE-TX Receive Block Diagram

25 www.national.com

DP83848H

4.2.2.1 Digital Adaptive Equalization and Gain Control

When transmitting data at high speeds over copper twisted
pair cable, frequency dependent attenuation becomes a
concern. In high-speed twisted pair signalling, the fre­quency content of the transmitted signal can vary greatly
during normal operation based primarily on the random­ness of the scrambled data stream. This variation in signal
attenuation caused by frequency variations must be com­pensated to ensure the integrity of the transmission.

In order to ensure quality transmission when employing
MLT-3 encoding, the co mpensation mus t be able to adapt
to various cable lengths and cable types depending on the
installed env ironment. The se lection of long cable lengths
for a given implementation, requires significant compensa­tion which will over-compensate for shorter, less attenuat­ing lengths. Conversely, the selection of short or
intermediate cable lengths requiring less compensation will
cause serious under-compensation for longer length
cables. The compensation or equalization must be adap-

tive to ensure proper conditioning of the received signal
independent of the cable length.

The DP83848H utilizes an extremely robust equalization
scheme referred as ‘Digital Adaptive Equalization.’

The Digital Equalizer removes ISI (inter symbol interfer­ence) from the receive data stream by continuously adapt­ing to provide a filter with the inverse frequency response
of the channel. Equalization is combined with an adaptive
gain control stage. This enables the receive 'eye pattern' to
be opened sufficiently to allow very reliable data recovery.

The curves given in Fig ure 8 illustrate attenuation at certai n
frequencies for given cable lengths. This is derived from
the worst case frequency vs. attenuation figures as speci­fied in the EIA/TIA Bulletin TSB-36. These curves indicate
the signific ant vari ations in signal at tenua tion that must be
compensated f or by the receive ad aptive equaliz ation cir­cuit.

Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50 ,

100, 130 & 150 meters of CAT 5 cable

www.national.com 26

DP83848T

4.2.2.2 Base Line Wander Compensation

The DP83848H is completely ANSI TP-PMD compliant
and includes Base Line Wander (BLW) compensation.
The BLW compensation block can successfully recover
the TP-PMD defined “killer” pattern.

BLW can generally be defined as the change in the aver­age DC content, relatively short period o ver tim e, of an AC
coupled digital transmission over a given transmission
medium. (i.e., copper wire).

BLW results from the interaction between the low fre­quency components of a transmitted bit stream and the
frequency response of the AC coupling component(s)
within the transmission system. If the low frequency con­tent of the digital bit stream goes below the low frequency
pole of the AC coupling transformers then the droop char­acteristics of the transformers will dominate resulting in
potentially serious BLW.

The digital oscilloscope plot provided in Figure 9 illus­trates the severity of the BLW event that can theoretically
be generated during 100BASE-TX packet transmission.
This event consists of approximately 800 mV of DC offset
for a period of 120 µs. Left uncompensated, events such
as this can cause packet loss.

4.2.3 Signal Detect

The signal detect function of the DP83848H is incorpo­rated to meet the specifications mandated by the ANSI
FDDI TP-PMD Standard as well as the IEEE 802.3
100BASE-TX Standard for both voltage thresholds and
timing parameters.

Note that the reception of normal 10BASE-T link pulses
and fast link pulses per IEEE 802.3u Auto-Negotiation by

the 100BASE-TX receiver do not cause the DP83848H to
assert signal detect.

4.2.4 MLT-3 to NRZI Decoder

The DP83848H decodes the MLT-3 information from the
Digital Adaptive Equalizer block to binary NRZI data.

4.2.5 NRZI to NRZ

In a typical application, the NRZI to NRZ decoder is
required in order to present NRZ formatted data to the
descrambler.

4.2.6 Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel
converter which supplies 5-bit wide data symbols to the
PCS Rx state machine.

Figure 9. 100BASE-TX BLW Event

27 www.national.com

DP83848H

4.2.7 Descrambler

A serial descrambler is used to de-scramble the received
NRZ data. The descrambler has to generate an identical
data scrambling sequence (N) in order to recover the origi­nal unscrambled data (UD) from the scrambled data (SD)
as represented in the equations:

Synchronization of the descrambler to the original scram­bling sequence (N) is achieved based on the knowledge
that the incoming scrambled data stream consists of
scrambled IDLE data. After the descrambler has recog­nized 12 consecutive IDLE code-groups, where an
unscrambled I DLE code-group in 5B N RZ is equal to five
consec utive ones ( 1111 1), it wil l sync hroniz e to th e rec eive
data stream and generate unscrambled data in the form of
unaligned 5B code-groups .

In order to maintain synchronization, the descrambler must
continuously monitor the validity of the unscrambled data
that it generates. To ensure this, a line state monitor and a
hold timer are used to constantly monitor the synchroniza­tion status. Upon synchronization of the descrambler the
hold timer star ts a 722 µs countdown. Upon detection of
sufficient IDLE code-groups (58 bit times) w ith in th e 72 2 µs
period, the hold timer will reset and begin a new count­down. This monitoring operation will continue indefinitely
given a properly operating network connection with good
signal integrity. If the line state monitor does not recognize
sufficient unscrambled IDLE code-groups within the 722 µs
period, the entire descrambler will be forced out of the cur­rent state of synchronization and reset in order to re­acquire synchronization.

4.2.8 Code-group Alignment

The code-group alignment module operates on unaligned
5-bit data from the descrambler (or, if the descrambler is
bypassed, directly from the NRZI/NRZ decoder) and con­verts it into 5B code-group data (5 bits). Code-group align­ment occurs after the J/K code-group pair is detected.
Once the J/K code-group pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.

4.2.9 4B/5B Decoder

The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Specifically, the J/K 10-bit code-group pair
is replaced by the nibble pair (0101 0101). All subsequent
5B code-groups are converted to the corresponding 4B
nibbles for the duration of the entire packet. This conver­sion ceases upon the detection of the T/R code-group pair
denoting the End of Stream Delimiter (ESD) or with the
reception of a minimum of two IDLE code-groups.

4.2.10 100BASE-TX Link Integrity Monitor

The 100 Base TX Lin k monito r ensur es that a v alid and st a­ble link is established before enabling both the Transmit
and Receive PCS layer.

Signal detect must be vali d for 395u s to all ow the lin k mon­itor to enter the 'Lin k Up ' s tate, and enable t he tr ans mi t an d
receive functions.

4.2.11 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K.

If this condition is detected, the DP83848H will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the
cycles that correspond to received 5B code-groups until at
least two IDLE code groups are detected. In addition, the
False Carrier Sense Counter register (FCSCR) will be
incremented by one.

Once at least tw o IDLE co de groups are detec ted, RX_ER
and CRS become de-asserted.

4.3 10BASE-T TRANSCEIVER MODULE

The 10BASE-T Transceiver Module is IEEE 802.3 compli­ant. It includes the receiver, transmitter, collision, heart­beat, loopback, jabber, and link integrity functions, as
defined in the standard. An external filter is not required on
the 10BASE-T interface since this is integrated inside the
DP83848H. This section focuses on the genera l 10BASE-T
system level operation.

4.3.1 Operational Modes

The DP83848H has two basic 10BASE-T operational
modes:

— Half Duplex mode
— Full Duplex mode

Half Duplex Mode

In Half Duplex mode the DP83848H functions as a stan­dard IEEE 802.3 10BASE-T transceiver supporting the
CSMA/CD protocol.

Full Duplex Mode

In Full Duplex mode the DP83848H is capable of simulta­neously transmitting and receiving without asserting the
collision signal. The DP83848H's 10 Mb/s ENDEC is
designed to encode and decode simultaneously.

UD SD N⊕()=

SD UD N⊕()=

www.national.com 28

DP83848T

4.3.2 Smart Squelch

The smart squelch is responsible for determining when
valid data is present on the differential receive inputs. The
DP83848H implements an intelligent receive squelch to
ensure that impulse noise on the receive inputs will not be
mistaken for a valid signal. Smart squelch operation is
independent of the 10BASE-T operational mode.

The squelch circuitry employs a combination of amplitude
and timing measurements (as specified in the IEEE 802.3
10BSE-T standard) to determine the vali dity o f d ata on the
twisted pair inputs (refer to Figure 10).

The signal at th e sta rt of a pack et is ch ecke d by th e smart
squelch and any pulses not exceeding the squelch level
(either positive or negative, depending upon polarity) will
be rejected. Once this first squelch level is overcome cor­rectly, the opposite squelch level must then be exceeded

within 150 ns. Finally the signal must again exceed the
original squelch level within a 150 ns to ensure that the
input waveform will not be rejected. This checking proce­dure results in the loss of typically three preamble bits at
the beginning of each packet.

Only after all these conditions have been satisfied will a
control signal be generated to indicate to the remainder of
the circuitry that valid data is present. At this time, the
smart squelch circuitry is reset.

Valid data is considered to be present until the squelch
level has not been generated for a time longer than 150
ns, indicating the End of Packet. Once good data has
been detected, the squelc h leve ls are red uced to minim ize
the effect of noise causing premature End of Packet
detection.

4.3.3 Collision Detection and SQE

When in Half Duplex, a 10BASE-T collision is detected
when the receive and transmit channels are active simul­taneously. Collisions are reported by the COL signal on
the MII. Collisions are also reported when a jabber condi­tion is detected.

The COL signal remains set for the duration of the colli­sion. If the PHY is receiving when a collision is detected it
is reported immediately (through the COL pin).

When heartbeat is enabled, approximately 1 µs after the
transmission of each packet, a Signal Quality Error (SQE)
signal of approximately 10-bit times is generated to indi­cate successful transmission. SQE is reported as a pulse
on the COL signal of the MII.

The SQE test is inhibited when the PHY is set in full
duplex mode. SQE can also be inhibited by setting the
HEARTBEAT_DIS bit in the 10BTSCR register.

4.3.4 Carrier Sense

Carrier Sense (CRS) may be asserted due to receive
activity once valid data is detected via the squelch func­tion.

For 10 Mb/s Half Duplex operation, CRS is asserted dur­ing either packet transmission or reception.

For 10 Mb/s Full Duplex operation, CRS is asserted only
during receive activity.

CRS is deasserted following an end of packet.

4.3.5 Normal Link Pulse Detection/Generation

The link pulse generator produces pulses as defined in
the IEEE 802.3 10BASE-T standard. Each link pulse is
nominally 100 ns in duration and transmitted every 16 ms
in the absence of trans mit data.

Link pulses are used to check the integrity of the connec­tion with the remote end. If valid link pulses are not
received, the link detector disables the 10BASE-T twisted
pair transmitter, receiver and collision detection functions.

When the link integrity function is disabled
(FORCE_LINK_10 of the 10BTSCR register), a good link
is forced and the 10BASE-T transceiver will operate
regardless of the presence of link pulses.

end of packet

start of packet

V

SQ-(reduced)

V

SQ-

V

SQ+(reduced)

V

SQ+

<150 ns

<150 ns

>150 ns

Figure 10. 10BASE-T Twisted Pair Smart Squelch Operation

29 www.national.com

DP83848H

4.3.6 Jabber Function

The jabber function monitors the DP83848H's output and
disables the transmitte r if it att empts to transmit a pac ke t of
longer than legal s iz e. A ja bbe r ti me r m oni tors th e transmit­ter and disables the transmission if the transmitter is active
for approximately 85 ms.

Once disabled by the Jabber function, the transmitter stays
disabled for the entire time that the ENDEC module's inter­nal transmit enable is asserted. This signal has to be de­asserted for approximately 500 ms (the “unjab” time)
before the Jabber function re-enables the transmit outputs.

The Jabber function is only relevant in 10BASE-T mode.

4.3.7 Automatic Link Polarity Detection and Correction

The DP83848H's 10BASE-T transceiver module incorpo­rates an automatic link polarity detection circuit. When
three consecutive inverted link pulses are received, bad
polarity is reported.

A polarity reversal can be cau sed by a wiring error a t either
end of the cable, usually at the Main Distribution Frame
(MDF) or patc h panel in the wiring closet.

The bad polarity conditi on is la tched in the 10BT SCR regi s­ter. The DP83848H's 10BASE-T transceiver module cor­rects for this error internally and will continue to decode
received data correctly. This eliminates the need to correct
the wiring error immediately.

4.3.8 Transmit and Receive Filtering

External 10BASE-T filters are not required when using the
DP83848H, as the required signal conditioning is inte­grated into the device.

Only isolation transformers and impedance matching resis­tors are required for the 10BASE-T transmit and receive
interface. The internal transmit filtering ensures that all the
harmonics in the transmit signal are attenuated by at least
30 dB.

4.3.9 Transmitter

The encoder begins operation when the Transmit Enable
input (TX_EN) goes high and converts NRZ data to pre­emphasized Manchester data for the transceiver. For the
duration of TX_EN, the serialized Transmit Data (TXD) is
encoded for the transmit-driver pair (PMD Output Pair).
TXD must be valid on the rising edge of Transmit Clock
(TX_CLK). Transmission ends when TX_EN deasserts.
The last transition is always positive; it occurs at the center
of the bit cell if the last bit is a one, or at the end of the bit
cell if the last bit is a zero.

4.3.10 Receiver

The decoder detects the en d of a fra me wh en n o add iti ona l
mid-bit transitions are detected. Within one and a half bit
times after the last bit, carrier sense is de-asserted.
Receive clock st ays active for five more bi t times after CRS
goes low, to guarantee the receive timings of the controller.

www.national.com 30

DP83848T

5.0 Design Guidelines

5.1 TPI Network Circuit

Figure 11 shows the recommended circuit for a 10/100
Mb/s twisted pair interface. To the right is a partial list of
recommended transformers. It is important that the user
realize that variations w ith PCB and compo nent chara cter­istics requires that the application be tested to ensure that
the circuit meet s th e req ui rem ents of the intended ap pl ica ­tion.

Pulse H1102
Pulse H2019
Pulse J0011D21
Pulse J0011D21B

Figure 11. 10/100 Mb/s Twisted Pair Interface

RJ45

RD-

RD+

TD-

TD+

RD­RD+

TD­TD+

1:1

0.1µF*
T1

1:1

COMMON MODE CHOKES

MAY BE REQUIRED.

49.9Ω

49.9

Ω

0.1µF*

Vdd

NOTE: CENTER TAP IS PULLED TO VDD

*PLACE CAPACITORS CLOSE TO THE

TRANSFORMER CENTER TAPS

0.1µF

All values are typical and are +/- 1%

PLACE RESISTORS AND
CAPACITORS CLOSE TO

THE DEVICE.

Vdd

49.9Ω

49.9

Ω

0.1µF

Vdd

31 www.national.com

DP83848H

5.2 ESD Protection

Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a system. In those cases, strict handling procedures
need be implemented during the manufacturing process to
greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal compo­nents are less sensitive from ESD events.

See Section 8.0 for ESD rating.

5.3 Clock In (X1) Requirements

The DP83848H support s an ex tern al C MOS level os cil lator
source or a crystal resonator device.

Oscillator

If an external clock sour ce i s us ed, X1 sho uld be ti ed to the
clock source and X2 should be left floating.

Specifications for CMOS oscillator: 25 MHz in MII Mode is
listed in Table 6.

Crystal

A 25 MHz, parallel, 20 pF load crystal resonator should be
used if a crystal source is desired. Figure 12 shows a typi­cal connection for a crystal resonator circuit. The load
capacitor value s will vary with the crysta l vendors; check
with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel reso­nance AT cut crystal with a minimum drive level of 100µW

and a maximum of 500µW. If a crystal is specified for a
lower drive level, a current limiting resistor should be
placed in series between X2 and the crystal.

As a starting p oint fo r evalu ating an o scillat or circ uit, if t he
requirements for the crystal are not known, C

L1

and C

L2

should be set at 33 pF, and R1 should be set at 0Ω.
Specification for 25 MHz crystal are listed in Table 7.

Figure 12. Crystal Oscillator Circuit

X1

X2

C

L2

C

L1

R

1

Table 6. 25 MHz Oscillator Specification

Parameter Min Typ Max Units Condition

Frequency 25 MHz
Frequency

Tolerance

+

50 ppm Operational Tem-

perature

Frequency

Stability

+

50 ppm 1 year aging

Rise / Fall Time 6 nsec 20% - 80%

Jitter 50 psec Short term
Jitter 200 psec Long term

Symmetry 40% 60% Duty Cycle

Table 7. 25 MHz Crystal Specification

Parameter Min Typ Max Units Condition

Frequency 25 MHz
Frequency

Tolerance

+

50 ppm Operational Tem-

perature

Frequency

Stability

+

50 ppm 1 year aging

Load Capacitance 25 40 pF

www.national.com 32

DP83848T

5.4 Power Feedback Circuit

To ensure correct operation for the DP83848H, parallel
caps with values of 10 µF (Tantalum) and 0.1 µF should
be placed close to pin 19 (PFBOUT) of the device.

Pin 16 (PFBIN1) and pin 30 (PFBIN2) must be connected
to pin 19 (PFBOUT), each pin requires a small capacitor
(0.1 µF). See Figure 13 below for proper connections.

5.5 Power Down

The device can be put in a Power Down mode by setting
bit 11 (Power Down) in the Basic Mode Control Register,
BMCR (0x00h).

5.6 Energy Detect Mode

When Energy Detect is enabled and there is no activity on
the cable, the DP83848H will remain in a low power mode
while monitoring the transmission line. Activity on the line
will cause the DP83848H to go through a normal power
up sequence. Regardless of cable activity, the DP83848H
will occasionally wake up the transmitter to put ED pulses
on the line, but will o therw ise dra w as li ttle pow er as poss i­ble. Energy detect functionality is controlled via register
Energy Detect Control (EDCR), address 0x1Dh.

6.0 Reset Operation

The DP83848H includes an internal power-on reset
(POR) function and does not need to be explicitly reset for
normal operation after power up. If required during normal
operation, the device can be reset by a hardware or soft­ware reset.

6.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse
(TTL level), with a duration of at least 1 µs, to the
RESET_N. This will reset the device such that all registers
will be reinitialized to default values and the hardware
configuration values will be re-latched into the device
(similar to the power-up/reset operatio n).

6.2 Software Reset

A software reset is accomplished by setting the reset bit
(bit 15) o f the B asic M ode Cont rol Re gister ( BMCR). The
period from the point in time when the reset bit i s set to th e
point in time when software reset has concluded is
approximately 1 µs.

The software reset will rese t the dev ic e su ch that all regis ­ters will be reset to default values and the hardware con­figuration values will be maintained. Software driver code
must wait 3 µs followi ng a software re set before al lowing
further serial MII operations with the DP83848H.

0.1µ

F

10 µF

Pin 19 (

PFBOUT

)

0.1 µF

0.1 µF

Pin 16 (PFBIN1)

Pin 30 (PFBIN2)

+

-

Figure 13. Power Feeback Connection

33 www.national.com

DP83848H

7.0 Register Block

Table 8. Register Map

Offset

Access Tag Description

Hex Decimal

00h 0 RW BMCR Basic Mode Control Register
01h 1 RO BMSR Basic Mode Status Register
02h 2 RO PHYIDR1 PHY Identifier Register #1
03h 3 RO PHYIDR2 PHY Identifier Register #2
04h 4 RW ANAR Auto-Negotiation Advertisement Register
05h 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page)
05h 5 RW ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page)
06h 6 RW ANER Auto-Negotiation Expansion Register
07h 7 RW ANNPTR Auto-Negotiation Next Page TX

08h-Fh 8-15 RW RESERVED RESERVED

Extended Registers

10h 16 RO P HYSTS PHY Status Register
11h 17 RW RESERVED RESERVED
12h 18 RO RESERVED RESERVED
13h 19 RW RESERVED RESERVED
14h 20 RW FCSCR False Carrier Sense Counter Register
15h 21 RW RECR Receive Error Counter Register
16h 22 RW PCSR PCS Sub-Layer Configuration and Status Register
17h 23 RW RESERVED RESERVED
18h 24 RW LEDCR LED Direct Control Register

19h 25 RW PHYCR PHY Control Register
1Ah 26 RW 10BTSCR 10Base-T Status/Control Register
1Bh 27 RW CDCTRL1 CD Test Control Register and BIST Extensions Register
1Ch 28 RW RESERVED RESERVED
1Dh 29 RW EDCR Energy Detect Control Register

1Eh-1Fh 30-31 RW RESERVED RESERVED

34 www.national.com

Table 9. Register Table

Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Basic Mode Control Register

00h BMCR Reset Loop-

back

Speed

Selection

Auto-

Neg

Enable

Power

Down

Isolate Restart

Auto-

Neg

Duplex

Mode

Collision

Test

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Basic Mode Status Register

01h BMSR 100Base

-T4

100Base

-TX FDX

100Base

-TX HDX

10Base-

T

FDX

10Base-

T

HDX

Re-

served

Re-

served

Re-

served

Re-

served

MF Pre-

amble

Sup-

press

Auto-

Neg

Com-

plete

Remote

Fault

Auto-

Neg

Ability

Link

Status

Jabber

Detect

Extend-

ed Capa-

bility

PHY Identifier Register 1

02h PHYIDR

1

OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB

PHY Identifier Register 2

03h PHYIDR

2

OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB VNDR_

MDL

VNDR_

MDL

VNDR_

MDL

VNDR_

MDL

VNDR_

MDL

VNDR_

MDL

MDL_

REV

MDL_

REV

MDL_

REV

MDL_

REV

Auto-Negotiation Advertisement Register

04h ANAR Next

Page Ind

Re-

served

Remote

Fault

Re-

served

ASM_DI

R

PAUSE T4 TX_FD TX 10_FD 10 Protocol

Selection

Protocol

Selection

Protocol

Selection

Protocol

Selection

Protocol

Selection

Auto-Negotiation Link Partner Ability Regis-

ter (Base Page)

05h ANLPAR Next

Page Ind

ACK Remote

Fault

Re-

served

ASM_DI

R

PAUSE T4 TX_FD TX 10_FD 10 Protocol

Selection

Protocol

Selection

Protocol

Selection

Protocol

Selection

Protocol

Selection

Auto-Negotiation Link Partner Ability Regis-

ter Next Page

05h AN-

LPARNP

Next

Page Ind

ACK Mes-

sage

Page

ACK2 Toggle Code Code Code Code Code Code Code Code Code Code Code

Auto-Negotiation Expansion Register

06h ANER Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

PDF LP_NP_

ABLE

NP_

ABLE

PAGE_

RX

LP_AN_

ABLE

Auto-Negotiation Next Page TX Register

07h ANNPTR Next

Page Ind

Re-

served

Mes-

sage

Page

ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE

RESERVED

08-0fh Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

EXTENDED REGISTERS

PHY Status Register

10h PHYSTS Re-

served

MDI-X

mode

Rx Err

Latch

Polarity

Status

False

Carrier

Sense

Signal

Detect

De-

scram

Lock

Page

Receive

Re-

served

Remote

Fault

Jabber

Detect

Auto-

Neg

Com-

plete

Loop-

back Sta-

tus

Duplex

Status

Speed

Status

Link

Status

RESERVED

11h Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

RESERVED

12h Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

RESERVED

13h Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

False Carrier Sense Counter Register

14h FCSCR Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT

Receive Error Counter Register

15h RECR Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

RXER-

CNT

RXER-

CNT

RXER-

CNT

RXER-

CNT

RXER-

CNT

RXER-

CNT

RXER-

CNT

RXER-

CNT

PCS Sub-Layer Configuration and Status

Register

16h PCSR Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

TQ_EN SD_FOR

CE_PMA

SD_

OPTION

DESC_T

IME

Re-

served

FORCE_

100_OK

Re-

served

Re-

served

NRZI_

BYPASS

SCRAM_

BYPASS

DE

SCRAM_

BYPASS

35 www.national.com

RESERVED

17h Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

LED Direct Control Register

18h LEDCR Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

DRV_LN

KLED

Re-

served

Re-

served

LNKLED Re-

served

PHY Control Register

19h PHYCR MDIX_E

N

FORCE_

MDIX

PAUSE_

RX

PAUSE_

TX

BIST_fe PSR_15 BIST_

STATUS

BIST_ST

ART

BP_STR

ETCH

Re-

served

LED_

CNFG[0]

PHY

ADDR

PHY

ADDR

PHY

ADDR

PHY

ADDR

PHY

ADDR

10Base-T Status/Control Register

1Ah 10BT_S

CR

Re-

served

Re-

served

Re-

served

Re-

served

SQUELC

H

SQUELC

H

SQUELC

H

LOOPBA

CK_10_

DIS

LP_DIS FORC_

LINK_10

Re-

served

POLARI-

TY

Re-

served

Re-

served

HEART_

DIS

JABBER

_DIS

CD Test Control and BIST Extensions Reg-

ister

1Bh CDCTRL

1

BIST_ER

ROR_C

OUNT

BIST_ER

ROR_C

OUNT

BIST_ER

ROR_C

OUNT

BIST_ER

ROR_C

OUNT

BIST_ER

ROR_C

OUNT

BIST_ER

ROR_C

OUNT

BIST_ER

ROR_C

OUNT

BIST_ER

ROR_C

OUNT

Re-

served

Re-

served

BIST_C

ONT_M

ODE

CDPattE

N_10

Re-

served

10Meg_

Patt_Ga

p

CDPatt-

Sel

CDPatt-

Sel

RESERVED

1Ch Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Energy Detect Control Register

1Dh EDCR ED_EN ED_AUT

O_UP

ED_AUT

O_DOW

N

ED_MAN ED_BUR

ST_DIS

ED_PW

R_STAT

E

ED_ERR

_MET

ED_DAT

A_MET

ED_ERR

_COUNT

ED_ERR

_COUNT

ED_ERR

_COUNT

ED_ERR

_COUNT

ED_DAT

A_COUN

T

ED_DAT

A_COUN

T

ED_DAT

A_COUN

T

ED_DAT

A_COUN

T

RESERVED

1Eh-1Fh Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Table 9. Register Table

Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

www.national.com 36

DP83848H

7.1 Register Definition

In the register definitions under the ‘Default’ heading, the following definitions hold true:
— RW=Read Write access
— SC=Register sets on event occurrence and Self-Clears when event ends
— RW/SC =Read Write access/Self Clearing bit

— RO=Read Only access
— COR = Clear on Read
— RO/COR=Read Only, Clear on Read
— RO/P=Read Only, Permanently set to a default value
— LL=Latched Low and held until read, based upon the occurrence of the corresponding event
—LH=Latched High and held until read, based upon the occurrence of the corresponding event

37 www.national.com

DP83848H

7.1.1 Basic Mode Control Register (BMCR)

Table 10. Basic Mode Control Register (BMCR), address 0x00

Bit Bit Name Default Description

15 Reset 0, RW/SC Reset:

1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit, which is self-clearing, returns a value of one until the reset

process is complete. The configuration is re-strapped.

14 Loopback 0, RW Loopback:

1 = Loopback enabled.
0 = Normal operation.
The loopback functio n enables MII transmit dat a to be routed to the MII

receive data path.
Setting this bit may cause the descram bler to lose synchroni zation and

produce a 500 µs “dead ti me ” befo re any valid data will app ear a t the
MII receive outputs.

13 Speed Selection RW Speed Select:

When auto-negotiation is disabled writing to this bit allows the port
speed to be selected.

1 = 100 Mb/s.
0 = 10 Mb/s.

12 Auto-Negotiation

Enable

RW Auto-Negotiation Enable:

Strap controls initial value at reset.
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ig-

nored when this bit is set.
0 = Auto-Negotiati on Disabled - bits 8 and 13 determine t he port speed

and duplex mode.

11 Power Down 0, RW Power Down:

1 = Power down.
0 = Normal operation.
Setting this bit powers down the PHY. Only the register block is en-

abled during a power down condition.

10 Isolate 0, RW Isolate:

1 = Isolates the Port fro m t he M II wi th the exception of the se rial ma n­agement.

0 = Normal operation.

9 Restart Auto-

Negotiation

0, RW/SC Restart Auto-Negotiation:

1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation pro­cess. If Auto-Negotiati on is disabled (bit 12 = 0), this bit is ig nored. This
bit is self-clearing and w ill retu rn a val ue of 1 u nti l Au to-N eg oti ati on i s
initiated, whereupo n it will self-clear. Opera tion of the Auto-Negotiati on
process is not affected by the management entity clearing this bit.

0 = Normal operation.

8 Duplex Mode Strap, RW Duplex Mode:

When auto-negotiatio n is disabled wri ting to this bit allows the port Du­plex capability to be selected.

1 = Full Duplex operation.
0 = Half Duplex operation.

www.national.com 38

DP83848H

7 Collision Test 0, RW Collision Test:

1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL s ignal to be asserted in response

to the assertion of TX _EN within 5 12-bit time s. The COL s ignal will be
de-asserted within 4-bit times in response to the de-assertion of
TX_EN.

6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.

Table 10. Basic Mode Control Register (BMCR), address 0x00 (Continued)

Bit Bit Name Default Description

39 www.national.com

DP83848H

7.1.2 Basic Mode Status Register (BMSR)

Table 11. Basic Mode Status Register (BMSR), address 0x01

Bit Bit Name Default Description

15 100BASE-T4 0, RO/P 100BASE-T4 Capable:

0 = Device not able to perform 100BASE-T4 mode.

14 100BASE-TX

Full Duplex

1, RO/P 100BASE-TX Full Duplex Capable:

1 = Device able to perform 100BASE-TX in full duplex mode.

13 100BASE-TX

Half Duplex

1, RO/P 100BASE-TX Half Duplex Capable:

1 = Device able to perform 100BASE-TX in half duplex mode.

12 10BASE-T

Full Duplex

1, RO/P 10BASE-T Full Duplex Capable:

1 = Device able to perform 10BASE-T in full duplex mode.

11 10BASE-T

Half Duplex

1, RO/P 10BASE-T Half Duplex Capable:

1 = Device able to perform 10BASE-T in half duplex mode.

10:7 RESERVED 0, RO RESERVED: Write as 0, read as 0.

6MF Preamble

Suppression

1, RO/P Preamble suppression Capable:

1 = Device able to perform management transaction with preamble
suppressed, 32-bits of p reamble needed only o nce after reset, invali d
opcode or invalid turnaround.

0 = Normal management operation.

5 Auto-Negotiation Com-

plete

0, RO Auto-Negotiation Complete:

1 = Auto-Negotiation process complete.
0 = Auto-Negotiation process not complete.

4 Remote Fault 0, RO/LH Remote Fault:

1 = Remote Fault condition detected (cleared on read or by reset).
Fault criteria: Far End Fault Indication or notification from Link Part­ner of Remote Fault.

0 = No remote fault condition detected.

3 Auto-Negotiation Abili-ty1, RO/P Auto Negotiation Ability:

1 = Device is able to perform Auto-Negotiation.
0 = Device is not able to perform Auto-Negotiation.

2 Link Status 0, RO/LL Link Status:

1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
The criteria for link vali dity is implementation spec ific. The occurrence

of a link failure conditi on will cau ses the Link Status bit to clear. Onc e
cleared, this bit may onl y be set by est ablishin g a good link c ondition
and a read via the management interface.

1 Jabber Detect 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode.

1 = Jabber condition detected.
0 = No Jabber.
This bit is implemented with a latching function, such that the occur-

rence of a jabber condition c auses it to set until it is cleared by a rea d
to this register by the management interface or by a reset.

0 Extended Capability 1, RO/P Extended Capability:

1 = Extended register capabilities.
0 = Basic register set capabilities only.

www.national.com 40

DP83848H

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848H. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num­ber. A PHY may r etur n a val ue of zero in eac h of th e 32 bi ts of the PHY Identi fier if d esired . The PHY I dentifi er is i ntended
to support network management. National's IEEE assigned OUI is 080017h.

7.1.3 PHY Identifier Register #1 (PHYIDR1)

7.1.4 PHY Identifier Register #2 (PHYIDR2)

7.1.5 Auto-Negotiation Advertisement Register (ANAR)

This register cont ains the ad vertis ed abi lities of thi s dev ice a s they w ill b e transmi tted to its link pa rtner during Auto-Neg o­tiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register
(address 0x01) Auto-Negotiation complete bit, BMSR[5] ) should be followed by a renegotiation. This will ensure that the
new values are properly used in the Auto-Negotiation.

Table 12. PHY Identifier Register #1 (PHYIDR1), address 0x02

Bit Bit Name Default Description

15:0 OUI_MSB <0010 0000 0000

0000>, RO/P

OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are
stored in bits 15 to 0 of this register. The most significant two bits
of the OUI are ignored (the IEEE stan dard refe rs to these as bit s 1
and 2).

Table 13. PHY Identifier Register #2 (PHYIDR2), address 0x03

Bit Bit Name Default Description

15:10 OUI_LSB <0101 11>, RO/P OUI Least Significant Bits:

Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10
of this register respectively.

9:4 VNDR_MDL <00 1001>, RO/P Vendor Model Number:

The six bits of vendor model number are mapped from bits 9 to 4
(most significant bit to bit 9).

3:0 MDL_REV <0000>, RO/P Model Revision Number:

Four bits of the vendor model revision number are mapped from
bits 3 to 0 (most si gnificant bit to bi t 3). This field wil l be incremented
for all major device changes.

Table 14. Negotiation Advertisement Register (ANAR), address 0x04

Bit Bit Name Default Description

15 NP 0, RW Next Page Indication:

0 = Next Page Transfer not desired.

1 = Next Page Transfer desired.
14 RESERVED 0, RO/P RESERVED by IEEE: Writes ignored, Read as 0.
13 RF 0, RW Remote Fault:

1 = Advertises that this device has detected a Remote Fault.

0 = No Remote Fault detected.
12 RESERVED 0, RW RESERVED for Future IEEE use: Write as 0, Read as 0

41 www.national.com

DP83848H

11 ASM_DIR 0, RW Asymmetric PAUSE Support for Full Duplex Links:

The ASM_DIR bit indicates that asymmetric PAUSE is supported.

Encoding and resolution of PAUSE bits is defined in IEEE 802.3

Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolu-

tion status is reported in PHYCR[13:12].

1 = Advertise that the DTE (MAC) has implemented both the op-

tional MAC control su blaye r an d the p ause fu nctio n as s pecif ied in

clause 31 and annex 31B of 802.3u.

0= No MAC based full duplex flow control.
10 PAUSE 0, RW PAUSE Support for Full Duplex Links:

The PAUSE bit indicates that the device is capable of providing the

symmetric PAUSE functions as defined in Annex 31B.

Encoding and resolution of PAUSE bits is defined in IEEE 802.3

Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolu-

tion status is reported in PHYCR[13:12].

1 = Advertise that the DTE (MAC) has implemented both the op-

tional MAC control su blaye r an d the p ause fu nctio n as s pecif ied in

clause 31 and annex 31B of 802.3u.

0= No MAC based full duplex flow control.

9 T4 0, RO/P 100BASE-T4 Support:

1= 100BASE-T4 is supported by the local device.

0 = 100BASE-T4 not supported.

8 TX_FD Strap, RW 100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the local device.

0 = 100BASE-TX Full Duplex not supported.

7 TX Strap, RW 100BASE-TX Support:

1 = 100BASE-TX is supported by the local device.

0 = 100BASE-TX not supported.

6 10_FD RW 10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported by the local device.

0 = 10BASE-T Full Duplex not supported.

510 RW10BASE-T Support:

1 = 10BASE-T is supported by the local device.

0 = 10BASE-T not supported.

4:0 Selector <00001>, RW Protocol Selection Bits:

These bits contain the binary enc oded protoco l se lector supp orte d

by this port. <00001> indicates that this device supports IEEE

802.3u.

Table 14. Negotiation Advertisement Register (ANAR), address 0x04 (Continued)

Bit Bit Name Default Description

www.national.com 42

DP83848H

7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content
changes after the successful auto-negotiation if Next-pages are supported.

Table 15. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05

Bit Bit Name Default Description

15 NP 0, RO Next Page Indication:

0 = Link Partner does not desire Next Page Transfer.

1 = Link Partner desires Next Page Transfer.
14 ACK 0, RO Acknowledge:

1 = Link Partner acknowledges reception of the ability data word.

0 = Not acknowledged.

The Auto-Negotiation state machine will automatically control the

this bit based on the incoming FLP bursts.
13 RF 0, RO Remote Fault:

1 = Remote Fault indicated by Link Partner.

0 = No Remote Fault indicated by Link Partner.
12 RESERVED 0, RO RESERVED for Future IEEE use:

Write as 0, read as 0.
11 ASM_DIR 0, RO ASYMMETRIC PAUSE:

1 = Asymmetric pause is supported by the Link Partner.

0 = Asymmetric pause is not supported by the Link Partner.
10 PAUSE 0, RO PAUSE:

1 = Pause function is supported by the Link Partner.

0 = Pause function is not supported by the Link Partner.

9T4 0, RO100 BASE-T4 Suppo rt:

1 = 100BASE-T4 is supported by the Link Partner.

0 = 100BASE-T4 not supported by the Link Partner.

8TX_FD 0, RO100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the Link Partner.

0 = 100BASE-TX Full Duplex not supported by the Link Partner.

7TX 0, RO100BASE-TX Support:

1 = 100BASE-TX is supported by the Link Partner.

0 = 100BASE-TX not supported by the Link Partner.

6 10_FD 0, RO 10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported by the Link Partner.

0 = 10BASE-T Full Duplex not supported by the Link Partner.

510 0, RO10BASE-T Support:

1 = 10BASE-T is supported by the Link Partner.

0 = 10BASE-T not supported by the Link Partner.

4:0 Selector <0 0000>, RO Protocol Selection Bits:

Link Partner’s binary encoded protocol selector.

43 www.national.com

DP83848H

7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)

7.1.8 Auto-Negotiate Expansion Register (ANER)

This register contains additional Local Device and Link Partner status information.

Table 16. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05

Bit Bit Name Default Description

15 NP 0, RO Next Page Indication:

1 = Link Partner desires Next Page Transfer.

0 = Link Partner does not desire Next Page Transfer.
14 ACK 0, RO Acknowledge:

1 = Link Partner acknowledges reception of the ability data word.

0 = Not acknowledged.

The Auto-Negotiation state machine will automatically control the

this bit based on the incoming FLP bursts. Software should not at-

tempt to write to this bit.
13 MP 0, RO Message Page:

1 = Message Page.

0 = Unformatted Page.
12 ACK2 0, RO Acknowledge 2:

1 = Link Partner does have the abi lity to c omp ly to nex t page mes-

sage.

0 = Link Partner does not have the ability to comply to next page

message.
11 Toggle 0, RO Toggle:

1 = Previous value of the transmitted Link Code word equalled 0.

0 = Previous value of the transmitted Link Code word equalled 1.

10:0 CODE <000 0000 0000>, ROCode:

This field represents the code field of the next page transmission.

If the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a “Message Page,” as defined in annex 28C of

Clause 28. Otherwise, the code shall be interpreted as an “Unfor-

matted Page,” and the interpretation is application specific.

Table 17. Auto-Negotiate Expansion Register (ANER), address 0x06

Bit Bit Name Default Description

15:5 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.

4 PDF 0, RO Parallel Detection Fault:

1 = A fault has been detected via the Parallel Detection function.

0 = A fault has not been detected.

3 LP_NP_ABLE 0, RO Link Partner Next Page Able:

1 = Link Partner does support Next Page.

0 = Link Partner does not support Next Page.

2 NP_ABLE 1, RO/P Next Page Able:

1 = Indicates local device is able to send additional “Next Pages”.

1 PAGE_RX 0, RO/COR Link Code Word Page Received:

1 = Link Code Word has been received, cleared on a read.

0 = Link Code Word has not been received.

www.national.com 44

DP83848H

7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

0 LP_AN_ABLE 0, RO Link Partner Auto-Negotiation Able:

1 = indicates that the Link Partner supports Auto-Negotiation.

0 = indicates that the Link Partner does not support Auto-Negotia-

tion.

T a ble 18. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07

Bit Bit Name Default Description

15 NP 0, RW Next Page Indication:

0 = No other Next Page Transfer desired.

1 = Another Next Page desired.
14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
13 MP 1, RW Message Page:

1 = Message Page.

0 = Unformatted Page.
12 ACK2 0, RW Acknowledge2:

1 = Will comply with message.

0 = Cannot comply with message.

Acknowledge2 is used by th e next page functio n to indicate that Lo-

cal Device has the ability to comply with the message received.
11 TOG_TX 0, RO Toggle:

1 = Value of toggle bit in previously transmitted Link Code Word

was 0.

0 = Value of toggle bit in previously transmitted Link Code Word

was 1.

Toggle is used by the Arbitration function within Auto-Negotiation

to ensure synchronization with the Link Partner during Next Page

exchange. This bit shall alwa ys tak e the oppo site va lue of the Tog -

gle bit in the previously exchanged Link Code Word.

10:0 CODE <000 0000 0001>, RWThis field represents the code field of the next page transmission.

If the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a "Messag e Page”, as de fined in annex 28C of IEEE

802.3u. Otherwise, the code shall be interpreted as an "Unformat-

ted Page”, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined

in Annex 28C of IEEE 802.3u.

Table 17. Auto-Negotiate Expansion Register (ANER), address 0x06 (Continued)

Bit Bit Name Default Description

45 www.national.com

DP83848H

7.2 Extended Registers

7.2.1 PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed information.

Table 19. PHY Status Register (PHYSTS), address 0x10

Bit Bit Name Default Description

15 RESERVED 0, RO RESERVED: Write ignored, read as 0.
14 MDI-X mode 0, RO MDI-X mode as reported by the Auto-Negotiation logic:

This bit will be affected by the settings of the MDIX_EN and
FORCE_MDIX bits in the PHYCR register. When MDIX is en­abled, but not forced, this bit will update dynamically as the
Auto-MDIX algorithm swaps between MDI and MDI-X configu­rations.

1 = MDI pairs swapped

(Receive on TPTD pair, Transmit on TPRD pair)

0 = MDI pairs normal

(Receive on TRD pair, Transmit on TPTD pair)

13 Receive Error Latch 0, RO/LH Receive Error Latch:

This bit will be cleared upon a read of the RECR register.
1 = Receive error event h as occu rred since last read of RXERCNT

(address 0x15, Page 0).
0 = No receive error event has occurred.

12 Polarity Status 0, RO Polarity Status:

This bit is a duplic ation of bit 4 in the 10BTSCR register. This bit will
be cleared upon a read of the 10BTSCR register, but not upon a
read of the PHYSTS register.

1 = Inverted Polarity detected.
0 = Correct Polarity detected.

11 False Carrier Sense

Latch

0, RO/LH False Carrier Sense Latch:

This bit will be cleared upon a read of the FCSR register.
1 = False Carrier event h as occurred since last read of FCSCR (ad -

dress 0x14).
0 = No False Carrier event has occurred.

10 Signal Detect 0, RO/LL 100Base-TX unconditional Signal Detect from PMD.

9 Descrambler Lock 0, RO/LL 100Base-TX Descrambler Lock from PMD.
8 Page Received 0, RO Link Code Word Page Received:

This is a duplicate of the Page Received bit in the ANER register,
but this bit will not be cleared upon a read of the PHYSTS re gis te r .

1 = A new Link Code Word Page has been received. Cleared on
read of the ANER (address 0x06, bit 1).

0 = Link Code Word Page has not been received.
7 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
6 Remote Fault 0, RO Remote Fault:

1 = Remote Fault cond ition detected (cleared on read of BMSR (ad-

dress 01h) register or by reset). Fault c riteria: notifica tion from Link

Partner of Remote Fault via Auto-Negotiation.

0 = No remote fault condition detected.

www.national.com 46

DP83848H

5 Jabber Detect 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode

This bit is a dupl icate of the Jabber De tect bit in the BMSR register,

except that it is not cleared upon a read of the PHYSTS register.

1 = Jabber condition detected.

0 = No Jabber.
4 Aut o-Neg Complete 0, RO Auto-Negotiation Complete:

1 = Auto-Negotiation complete.

0 = Auto-Negotiation not complete.
3 Loopback Status 0, RO Loopback:

1 = Loopback enabled.

0 = Normal operation.
2 Duplex Status 0, RO Duplex:

This bit indicates duplex status and is determ ined from Auto -Nego-

tiation or Forced Modes.

1 = Full duplex mode.

0 = Half duplex mode.

Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid li nk or if Au to-Negoti ation i s disa bled an d

there is a valid link.
1 Speed Status 0, RO Speed10:

This bit indicates the status of the speed and is determined from

Auto-Negotiation or Forced Modes.

1 = 10 Mb/s mode.

0 = 100 Mb/s mode.

Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid li nk or if Au to-Negoti ation i s disa bled an d

there is a valid link.
0 Link Status 0, RO Link Status:

This bit is a duplicate of the Link Status bit in the BMSR register,

except that it will not be cleared upon a read of t he PHYSTS regis-

ter.

1 = Valid link established (for either 10 or 100 Mb/s operation)

0 = Link not established.

Table 19. PHY Status Register (PHYSTS), address 0x10 (Continued)

Bit Bit Name Default Description

47 www.national.com

DP83848H

7.2.2 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the “False Carriers” attribute within the MAU managed object
class of Clause 30 of the IEEE 802.3u specification.

7.2.3 Receiver Error Counter Register (RECR)

This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY man­aged object class of Clause 30 of the IEEE 802.3u specification.

Table 20. False Carrier Sense Counter Register (FCSCR), address 0x14

Bit Bit Name Default Description

15:8 RESERVED 0, RO RESERVED: Writes ignored, Re ad as 0

7:0 FCSCNT[7:0] 0, RO / COR False Carrier Event Counter:

This 8-bit counter increments on every false carrier event. This
counter sticks when it reaches its max count (FFh).

Table 21. Receiver Error Counter Register (RECR), address 0x15

Bit Bit Name Default Description

15:8 RESERVED 0, RO RESERVED: Writes ignored, Re ad as 0

7:0 RXERCNT[7:0] 0, RO / COR RX_ER Counter:

When a valid car rier is prese nt and there is at least o ne occur rence
of an invalid data symbo l, this 8-bit c ounter in cremen ts for e ach re­ceive error detected. Thi s even t can incr emen t only on ce per va lid
carrier event. If a collision is present, the attribute will not incre­ment. The counter sticks when it reaches its max count.

www.national.com 48

DP83848H

7.2.4 100 Mb/s PCS Configuration and Status Register (PCSR)

Table 22. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16

Bit Bit Name Default Description

15:13 RESERVED <00>, RO RESERVED: Writes ignored, Read as 0.

12 RESERVED 0 RESERVED:

Must be zero.

11 RESERVED 0 RESERVED:

Must be zero.

10 TQ_EN

0, RW

100Mbs True Quiet Mode Enable:

1 = Transmit True Quiet Mode.
0 = Normal Transmit Mode.

9 SD FORCE PMA

0,RW

Signal Detect Force PMA:

1 = Forces Signal Detection in PMA.
0 = Normal SD operation.

8 SD_OPTION 1, RW Signal Detect Option:

1 = Enhanced signal detect algorithm.
0 = Reduced signal detect algorithm.

7 DESC_TIME 0, RW Descrambler Timeout:

Increase the descrambler timeout. When set this should allow the
device to receive larger packets (>9k bytes) without loss of syn­chronization.

1 = 2ms
0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e)

6 RESERVED 0 RESERVED:

Must be zero.

5 FORCE_100_OK 0, RW Force 100Mb/s Good Link:

1 = Forces 100Mb/s Good Link.
0 = Normal 100Mb/s operation.

4 RESERVED 0 RESERVED:

Must be zero.

3 RESERVED 0 RESERVED:

Must be zero.

2 NRZI_BYPASS 0, RW NRZI Bypass Enable:

1 = NRZI Bypass Enabled.
0 = NRZI Bypass Disabled.

1 RESERVED 0 RESERVED:

Must be zero.

0 RESERVED 0 RESERVED:

Must be zero.

49 www.national.com

DP83848H

7.2.5 LED Direct Control Register (LEDCR)

This register provides the ability to directly control the LED output. It does not provide read access to the LED.

Table23. LED Direct Control Register (LEDCR), address 0x18

Bit Bit Name Default Description

15:6 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

5 RESERVED 0 RESERVED:

Must be zero.

4 DRV_LNKLED 0, RW 1 = Drive value of LNKLED bit onto LED_LNK output

0 = Normal operation

3 RESERVED 0 RESERVED:

Must be zero.

2 RESERVED 0 RESERVED:

Must be zero.
1 LNKLED 0, RW Value to force on LED_LNK output
0 RESERVED 0 RESERVED:

Must be zero.

www.national.com 50

DP83848H

7.2.6 PHY Control Register (PHYCR)

Table 24. PHY Control Register (PHYCR), address 0x19

Bit Bit Name Default Description

15 MDIX_EN Strap, RW Auto-MDIX Enable:

1 = Enable Auto-neg Auto-MDIX capability.

0 = Disable Auto-neg Auto-MDIX capability.

The Auto-MDIX algorithm requires that the Auto-Negotiation En-

able bit in the BMCR register to be set. If Auto-Negotiation is not

enabled, Auto-MDIX should be disabled as well.

14 FORCE_MDIX 0, RW Force MDIX:

1 = Force MDI pairs to cross.

(Receive on TPTD pair, Transmit on TPRD pair)

0 = Normal operation.

13 PAUSE_RX 0, RO Pause Receive Negotiated:

Indicates that pause re ceive shoul d be enabled i n the MAC. Based

on ANAR[11:10] and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Ann ex 28B

Table 28B-3, “Pause Resolutio n”, only if th e Auto-Negotia ted High-

est Common Denominator is a full duplex technology.

12 PAUSE_TX 0, RO Pause Transmit Negotiated:

Indicates that pau se transmit shoul d be enabled in t he MAC. Based

on ANAR[11:10] and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Ann ex 28B

Table 28B-3, “Pause Resolutio n”, only if th e Auto-Negotia ted High-

est Common Denominator is a full duplex technology.

11 BIST_FE 0, RW/SC BIST Force Error:

1 = Force BIST Error.

0 = Normal operation.

This bit forces a single error, and is self clearing.

10 PSR_15 0, RW BIST Sequence select:

1 = PSR15 selected.

0 = PSR9 selected.
9 BIST_STATUS 0, LL/RO BIST Test Status:

1 = BIST pass.

0 = BIST fail. Latched, cleared when BIST is stopped.

For a count number of BIST errors, se e the BIST Error Count in the

CDCTRL1 register.
8 BIST_START 0, RW BIST Start:

1 = BIST start.

0 = BIST stop.
7 BP_STRETCH 0, RW Bypass LED Stretching:

This will bypass the LED stretching and the LED will reflect the in-

ternal value.

1 = Bypass LE D stretchi ng.

0 = Normal operation.
6 RESERVED 0 RESERVED: Must be zero.

51 www.national.com

DP83848H

7.2.7 10Base-T Status/Control Register (10BTSCR)

5 LED_CNFG[0]

Strap, RW

LED Configuration

LED_ CNFG[0] Mode Description

1 Mode 1

0 Mode2

In Mode 1, LEDs are configured as follows:

LED_LINK = ON for Good Link, OFF for No Link

In Mode 2, LEDs are configured as follows:

LED_LINK = ON for good Link, BLINK for Activity

4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port.

Table 25. 10Base-T Status/Control Register (10BTSCR), address 0x1A

Bit Bit Name Default Description

15 RESERVED 0, RW RESERVED:

Must be zero.

14:12 RESERVED 0, RW RESERVED:

Must be zero.

11:9 SQUELCH 100, R W Squelch Configuration:

Used to set the Squelch ‘ON’ threshold for the receiver.
Default Squelch ON is 330mV peak.

8 LOOPBACK_10_D

IS

0, RW In half-duplex mode, default 10BASE-T operation loops Transmit

data to the Receive data in ad diti on to transmitting the da ta on the
physical medium. This is fo r consistency with earlier 10B ASE2 and
10BASE5 implementations which used a shared medium. Setting
this bit disables the loopback functi on.

This bit does not affect loopback due to setting BMCR[14].

7 LP_DIS 0, RW Normal Link Pulse Disable:

1 = Transmission of NLPs is disabled.
0 = Transmission of NLPs is enabled.

6 FORCE_LINK_10 0, RW Force 10Mb Good Link:

1 = Forced Good 10Mb Link.
0 = Normal Link Status.

5 RESERVED 0, RW RESERVED:

Must be zero.

4POLARITYRO/LH10Mb Polarity St atus :

This bit is a duplication of bit 12 in the PH YSTS regi ste r. Both bi ts
will be cleared upon a read of 10BTSCR register, but not upon a
read of the PHYSTS register.

1 = Inverted Polarity detected.
0 = Correct Polarity detected.

Table 24. PHY Control Register (PHYCR), address 0x19 (Continued)

Bit Bit Name Default Description

www.national.com 52

DP83848H

3 RESERVED 0, RW RESERVED:

Must be zero.

2 RESERVED 1, RW RESERVED:

Must be set to one.

1 HEARTBEAT_DIS 0, RW Heartbeat Disable: This bit only has infl uence in half-dupl ex 10Mb

mode.
1 = Heartbeat function disabled.
0 = Heartbeat function enabled.

When the device is operating at 100Mb or configured for full
duplex operation, this bit will be ignored - the heartbeat func­tion is disabled.

0 JABBER_DIS 0, RW Jabber Disable:

Applicable only in 10BASE-T.
1 = Jabber function disabled.
0 = Jabber function enabled.

Table 25. 10Base-T Status/Control Register (10BTSCR), address 0x1A

Bit Bit Name Default Description

53 www.national.com

DP83848H

7.2.8 CD Test and BIST Extensions Register (CDCTRL1)

Table 26. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B

Bit Bit Name Default Description

15:8 BIST_ERROR_CO

UNT

0, RO BIST ERROR Counter:

Counts number of errored data nibbles during Packet BIST. This

value will reset when Packet BIST is restarted. The counter sticks

when it reaches its max count.

7:6 RESERVED 0, RW RESERVED:

Must be zero.
5 BIST_CONT_MOD

E

0, RW Packet BIST Continuous Mode:

Allows continuous pseudo random data transmission without any

break in transmission. This can be used for transmit VOD testing.

This is used in conjunction with the BIST controls in the PHYCR

Register (0x19h). Fo r 10M b ope ration, jabb er function mu st be dis-

abled, bit 0 of the 10BTSCR (0x1Ah), JABBER_DIS = 1.
4 CDPATTEN_10 0, RW CD Pattern Enable for 10Mb:

1 = Enabled.

0 = Disabled.
3 RESERVED 0, RW RESERVED:

Must be zero.
2 10MEG_PATT_GA

P

0, RW Defines gap between data or NLP test sequences:

1 = 15 µs.

0 = 10 µs.

1:0 CDPATTSEL[1:0] 00, RW CD Pattern Select[1:0]:

If CDPATTEN_10 = 1:

00 = Data, EOP0 sequence

01 = Data, EOP1 sequence

10 = NLPs

11 = Constant Manche ster 1s (10MHz sin e wave ) for harmo nic dis-

tortion testing.

www.national.com 54

DP83848H

7.2.9 Energy Detect Control (EDCR)

Table 27. Energy Detect Control (EDCR), address 0x1D

Bit Bit Name Default Description

15 ED_EN 0, RW Energy Detect Enable:

Allow Energy Detect Mode.

When Energy Detect is enabled and Auto-Negotiation is disabled

via the BMCR register, Auto -MDIX should be d isabled via the PHY-

CR register.

14 ED_AUTO_UP 1, RW Energy Detect Automatic Power Up:

Automatically begin pow er up sequence when Energy Detect Data

Threshold value (EDCR[3:0]) is reached. Alternatively, device

could be powered up m an ual ly u si ng the ED _ MAN bi t (ECDR[12]).

13 ED_AUTO_DOWN 1, RW Energy Detect Automatic Power Down:

Automatically begin power down sequence when no energy is de-

tected. Alternatively, device could be powered down using the

ED_MAN bit (EDCR[12]).

12 ED_MAN 0, RW/SC Energy Detect Manual Power Up/Down:

Begin power up/down sequence when this bit is asserted. When

set, the Energy Detect algorithm will initi ate a change of Energ y De-

tect state regardless of threshold (error or data) and timer values.

11 ED_BURST_DIS 0, RW Energy Detect Bust Disable:

Disable bursting of energy detect data pulses. By default, Energy

Detect (ED) transmits a burst of 4 ED d ata pulses each time the CD

is powered up. When bursting is disabled, only a single ED data

pulse will be send each time the CD is powered up.

10 ED_PWR_STATE 0, RO Energy Detect Power State:

Indicates current Energy Detect Power state. When set, Energy

Detect is in the powered up state. When cleared , Energy Dete ct is

in the powered down state. This bit is inval id when Energy D etec t

is not enabled.
9 ED_ERR_MET 0, RO/COR Energy Detect Error Threshold Met:

No action is automatically tak en up on rec ei pt of erro r eve nts. This

bit is informational only and would be cleared on a read.
8 ED_DATA_MET 0, RO/COR Energy Detect Data Threshold Met:

The number of data events that occu rred met or surpas sed the En-

ergy Detect Data Threshold. This bit is cleared on a read.

7:4 ED_ERR_COUNT 0001, RW Energy Detect Error Threshold:

Threshold to determine the number of energy detect error events

that should cause the d evice to t ake a ction . Inten ded to allo w aver -

aging of noise that may be on the line. Counter will reset after ap-

proximately 2 seconds without any energy detect data events.

3:0 ED_DATA_COUNT 0001, RW Energy Detect Data Threshold:

Threshold to determine the number of energy detect events that

should cause the device to take actions. Intended to allow averag-

ing of noise that ma y be on th e line. Coun ter will reset after app rox-

imately 2 seconds without any energy detect data events.

55 www.national.com

DP83848H

8.0 Electrical Specifi cat ions

Note: All parameters are guaranteed by test, statistical analysis or design.

Absolute Maximum Ratings

Recommended Operating Conditions

Absolute maximum ratings are those values beyond which
the safety of the device cannot be guaranteed. They are
not meant to imply that the device should be operated at
these limits.

8.1 DC Specs

Supply Voltage (VCC) -0.5 V to 4.2 V
DC Input Voltage (V

IN

) -0.5V to VCC + 0.5V

DC Output Voltage (V

OUT

) -0.5V to VCC + 0.5V

Storage Temperature (T

STG

)

-65

o

C to 150°C
Max case temp 147.7 °C
Max. die temperature (Tj) 150 °C
Lead Temp. (TL)

(Soldering, 10 sec.)

260 °C

ESD Rating
(R

ZAP

= 1.5k, C

ZAP

= 120 pF)

4.0 kV

Supply voltage (VCC) 3.3 Volts + .3V
Extreme - Ambient Temperature (T

A

) -40°C to 125°C

Power Dissipation (P

D

)264 mW

Thermal Characteristic

Max Units

Theta Junction to Case (Tjc)

8.8 °C / W

Theta Junction to Ambient (T

ja

) degrees Celsius/Watt - No Airflow @ 1.0W

Note: This is done with a JEDEC (2 layer 2 oz CU.) thermal test board

31.7 °C / W

Symbol Pin Types Parameter Conditions Min Typ Max Units

V

IH

I

I/O

Input High Voltage Nominal V

CC

2.0 V

V

IL

I

I/O

Input Low Voltage 0.8 V

I

IH

I

I/O

Input High Current VIN = V

CC

10 µA

I

IL

I

I/O

Input Low Current VIN = GND 10 µA

V

OL

O,

I/O

Output Low
Voltage

IOL = 4 mA 0.4 V

V

OH

O,

I/O

Output High
Voltage

IOH = -4 mA Vcc - 0.5 V

V

ledOL

LED Output Low

Voltage

IOL = 2.5 mA 0.4 V

V

ledOH

LED Output High

Voltage

IOH = -2.5 mA Vcc - 0.5 V

I

OZ

I/O,

O

TRI-STATE
Leakage

V

OUT

= V

CC

+ 10 µA

V

TPTD_100

PMD Output

Pair

100M Transmit
Voltage

0.95 1 1.05 V

V

TPTDsym

PMD Output

Pair

100M Transmit
Voltage Symmetry

+ 2 %

V

TPTD_10

PMD Output

Pair

10M Transmit
Voltage

2.2 2.5 2.8 V

56 www.national.com

DP83848H

C

IN1

I CMOS Input

Capacitance

5pF

C

OUT1

O CMOS Output

Capacitance

5pF

SD

THon

PMD Input

Pair

100BASE-TX
Signal detect turn­on threshold

1000 mV diff pk-pk

SD

THoff

PMD Input

Pair

100BASE-TX
Signal detect turn­off threshold

200 mV diff pk-pk

V

TH1

PMD Input

Pair

10BASE-T Re­ceive Threshold

585 mV

I

dd100

Supply 100BASE-TX

(Full Duplex)

I

OUT

= 0 mA

See Note

81 mA

I

dd10

Supply 10BASE-T

(Full Duplex)

I

OUT

= 0 mA

See Note

92 mA

Symbol Pin Types Parameter Conditions Min Typ Max Units

57 www.national.com

DP83848H

8.2 AC Specs

8.2.1 Power Up Timing

Parameter Description Notes Min Typ Max Units

T2.1.1 Post Power Up Stabilization

time prior to MD C preamble for
register ac cesses

MDIO is pulled hig h fo r 32-bit serial man­agement initializat ion

X1 Clock must be stable for a min. of
167ms at power up.

167 ms

T2.1.2 Hardware Configuration Latch-

in Time from power up

Hardware Configuration Pins are de­scribed in the Pin Description sec tio n

X1 Clock must be stable for a min. of
167ms at power up.

167 ms

T2.1.3 Hardware Configuration pins

transition to output drivers

50 ns

Vcc

Hardware

RESET_N

MDC

32 clocks

Latch-In of Hardware
Configuration Pins

Dual Function Pins
Become Enabled As Outputs

input

output

T2.1.3

T2.1.2

T2.1.1

X1 clock

58 www.national.com

DP83848H

8.2.2 Reset Timing

Note: It is important to c hoo se p ull -up and / or pu ll- dow n resi sto rs fo r eac h o f the hard ware c onf iguration pins that provid e
fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.

Parameter Description Notes Min Typ Max Units

T2.2.1 Post RESET Stabili zation time

prior to MDC preamble fo r re g­ister accesses

MDIO is pulled high for 32-bit serial man­agement initializat ion

3 µs

T2.2.2 Hardware Configuration Latch-

in Time from the Deassertion
of RESET (either soft or hard)

Hardware Configuration Pins are de­scribed in the Pin Description sec tio n

3 µs

T2.2.3 Hardware Configuration pins

transition to output drivers

50 ns

T2.2.4 RESET pulse width X1 Clock must be stable for at min. of 1us

during RESET pulse low time.

1 µs

Vcc

Hardware

RESET_N

MDC

32 clocks

Latch-In of Hardware
Configuration Pins

Dual Function Pins
Become Enabled As Outputs

input

output

T2.2.3

T2.2.2

T2.2.1

X1 clock

T2.2.4

59 www.national.com

DP83848H

8.2.3 MII Serial Management Timing

8.2.4 100 Mb/s MII Transmit Timing

Parameter Description Notes Min Typ Max Units

T2.3.1 MDC to MDIO (Output) Delay Time 0 30 ns
T2.3.2 MDIO (Input) to MDC Setup Time 10 ns
T2.3.3 MDIO (Input) to MDC Hold Time 10 ns
T2.3.4 MDC Frequency 2.5 25 MHz

Parameter Description Notes Min Typ Max Units

T2.4.1 TX_CLK High/Low Time 100 Mb/s Normal mode 16 20 24 ns
T2.4.2 TXD[3:0], TX_EN Data Setup to TX_CLK 100 Mb/s Normal mode 10 ns

T2.4.3 TXD[3:0], TX_EN Data Hold from TX_CLK 100 Mb/s Normal mode 0 ns

MDC

MDC

MDIO (output)

MDIO (input)

Valid Data

T2.3.1

T2.3.2 T2.3.3

T2.3.4

TX_CLK

TXD[3:0]

TX_EN

Valid Data

T2.4.2

T2.4.3

T2.4.1

T2.4.1

60 www.national.com

DP83848H

8.2.5 100 Mb/s MII Receive Timing

Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered
clocks. Minimum high and low times will not be violated.

8.2.6 100BASE-TX Transmit Packet Latency Timing

Note: For Normal mode, late ncy i s det ermine d by measuri ng the time from the fir st ris ing e dge of TX_CLK o ccurri ng af ter
the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100
Mb/s mode.

Parameter Description Notes Min Typ Max Units

T2.5.1 RX_CLK High/Low Time 100 Mb/s Normal mode 16 20 24 ns
T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 30 ns

Parameter Description Notes Min Typ Max Units

T2.6.1 TX_CLK to PMD Output Pair

Latency

100 Mb/s Normal mode 6 b its

RX_CLK

RXD[3:0]
RX_DV

T2.5.2

T2.5.1

T2.5.1

Valid Data

RX_ER

TX_CLK

TX_EN

TXD

PMD Output Pair

(J/K) IDLE DATA

T2.6.1

61 www.national.com

DP83848H

8.2.7 100BASE-TX Transmit Packet Deassertion Timing

Note: Deassertion is determi ned by me as urin g th e time from the first ris ing ed ge o f TX_ CLK oc cu rring after the deass er­tion of TX_EN to the first bit o f the “T” cod e group as output from the PMD Output Pair . 1 bit ti me = 10 ns in 100 M b/s mode.

Parameter Description Notes Min Typ Max Units

T2.7.1 TX_CLK to PMD Output Pair

Deassertion

100 Mb/s Normal mode 6 bits

TX_CLK

TXD

TX_EN

PMD Output Pair

(T/R) DATA IDLE

T2.7.1

(T/R) DATA IDLE

62 www.national.com

DP83848H

8.2.8 100BASE-TX Transmit Timing (t

R/F

& Jitter)

Note: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times
Note: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude

Parameter Description Notes Min Typ Max Units

T2.8.1 100 Mb/s PMD Output Pair tR

and t

F

345ns

100 Mb/s t

R

and tF Mismatch 500 ps

T2.8.2 100 Mb/s PMD Output Pair

Transmit Jitter

1.4 ns

PMD Output Pair

T2.8.1

T2.8.1

T2.8.1

T2.8.1

+1 rise

+1 fall

-1 fall

-1 rise

eye pattern

T2.8.2

T2.8.2

90%

10%

10%

90%

PMD Output Pair

63 www.national.com

DP83848H

8.2.9 100BASE-TX Receive Packet Latency Timing

Note: Carrier Sense On Dela y is determin ed by meas uring the ti me fro m the first b it of the “J” code group to the asse rtion
of Carrier Sense.

Note: 1 bit time = 10 ns in 100 Mb/s mode
Note: PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.

8.2.10 100BASE-TX Receive Packet Deassertion Timing

Note: Carrier Sense Off De lay is de termin ed by measu ring th e time from the first b it of th e “T” cod e group to the d eass er­tion of Carrier Sense.

Note: 1 bit time = 10 ns in 100 Mb/s mode

Parameter Description Notes Min Typ Max Units

T2.9.1 Carrier Sense ON Delay 100 Mb/s Normal mode 20 bits
T2.9.2 Receive Data Latency 100 Mb/s Normal mode 24 bits

Parameter Description Notes Min Typ Max Units

T2.10.1 Carrier Sense OFF Delay 100 Mb/s Normal mode 24 bits

CRS

RXD[3:0]

PMD Input Pair

RX_DV

RX_ER

IDLE

Data

T2.9.1

T2.9.2

(J/K)

CRS

T2.10.1

PMD Input Pair

DATA

IDLE

(T/R)

64 www.national.com

DP83848H

8.2.11 10 Mb/s MII Transmit Timing

Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII
signals are sampled on the falling edge of TX_CLK.

8.2.12 10 Mb/s MII Receive Timing

Note: RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks.
Minimum high and low times will not be violated.

Parameter Description Notes Min Typ Max Units

T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns
T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode 25 ns
T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode 0 ns

Parameter Description Notes Min Typ Max Units

T2.12.1 RX_CLK High/Low Time 160 200 240 ns
T2.12.2 RX_CLK to RXD[3:0], RX_DV Delay 10 Mb/s MII mode 100 ns
T2.12.3 RX_CLK rising edge delay from RXD[3:0],

RX_DV Valid

10 Mb/s MII mode 100 ns

TX_CLK

TXD[3:0]

TX_EN

Valid Data

T2.11.2

T2.11.3

T2.11.1

T2.11.1

RX_CLK

RXD[3:0]
RX_DV

T2.12.2

T2.12.1

T2.12.1

T2.12.3

Valid Data

65 www.national.com

DP83848H

8.2.13 10BASE-T Transmit Timing (Start of Packet)

Note: 1 bit time = 100 ns in 10Mb/s.

8.2.14 10BASE-T Transmit Timing (End of Packet)

Parameter Description Notes Min Typ Max Units

T2.13.1 Transmit Output Delay from the

Falling Edge of TX_CLK

10 Mb/s MII mode 3.5 bits

Parameter Description Notes Min Typ Max Units

T2.14.1 End of Packet High Time

(with ‘0’ ending bit)

250 300 ns

T2.14.2 End of Packet High Time

(with ‘1’ ending bit)

250 300 ns

TX_CLK

TX_EN

TXD

PMD Output Pair

T2.13.1

TX_CLK

TX_EN

PMD Output Pair

00

11

PMD Output Pair

T2.14.1

T2.14.2

66 www.national.com

DP83848H

8.2.15 10BASE-T Receive Timing (Start of Packet)

Note: 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV
Note: 1 bit time = 100 ns in 10 Mb/s mode.

8.2.16 10BASE-T Receive Timing (End of Packet)

Parameter Description Notes Min Typ Max Units

T2.15.1 C arrier Sen se Turn On De lay (PMD

Input Pair to CRS)

630 1000 ns

T2.15.2 RX_DV Latency 10 bits
T2.15.3 Receive Data Latency Measurement shown from SFD 8 bits

Parameter Description Notes Min Typ Max Units

T2.16.1 Carrier Sense Turn Off Delay 1.0 µs

TPRD±

CRS

RX_CLK

RX_DV

1st SFD bit decoded

RXD[3:0]

T2.15.1

T2.15.2

T2.15.3

101010101011

Preamble SFD Data

0000

1

0

1

PMD Input Pair

RX_CLK

CRS

IDLE

T2.16.1

67 www.national.com

DP83848H

8.2.17 10 Mb/s Heartbeat Timing

8.2.18 10 Mb/s Jabber Timing

Parameter Description Notes Min Typ Max Units

T2.17.1 CD Heartbeat Delay All 10 Mb/s modes 1200 ns
T2.17.2 CD Heartbeat Duration All 10 Mb/s modes 1000 ns

Parameter Description Notes Min Typ Max Units

T2.18.1 Jabber Activation Time 85 ms
T2.18.2 Jabber Deactivation Time 500 ms

TX_CLK

TX_EN

COL

T2.17.1

T2.17.2

TXE

PMD Output Pair

COL

T2.18.2

T2.18.1

68 www.national.com

DP83848H

8.2.19 10BASE-T Normal Link Pulse Timing

Note: These specifications represent transmit timings.

8.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing

Note: These specifications represent transmit timings.

Parameter Description Notes Min Typ Max Units

T2.19.1 Pulse Width 100 ns
T2.19.2 Pulse Period 16 ms

Parameter Description Notes Min Typ Max Units

T2.20.1 Clock, Data Pulse Width 100 ns
T2.20.2 Clock Pulse to Clock Pulse

Period

125 µs

T2.20.3 Clock Pulse to Data Pulse

Period

Data = 1 62 µs

T2.20.4 Burst Width 2ms
T2.20.5 FLP Burst to FLP Burst Period 16 ms

T2.19.2

T2.19.1

Normal Link Pulse(s)

clock
pulse

data
pulse

clock
pulse

FLP Burst FLP Burst

Fast Link Pulse(s)

T2.20.1

T2.20.1

T2.20.2

T2.20.3

T2.20.4

T2.20.5

69 www.national.com

DP83848H

8.2.21 100BASE-TX Signal Detect Timing

Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant.

8.2.22 100 Mb/s Internal Loopback Timing

Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”
of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is
based on device delays after the initial 550µs “dead-time”.

Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

Parameter Description Notes Min Typ Max Units

T2.21.1 SD Internal Turn-on Time 1 ms
T2.21.2 SD Internal Turn-off Time 350 µs

Parameter Description Notes Min Typ Max Units

T2.22.1 TX_EN to RX_DV Loopback 100 Mb/s internal loopback mode 240 ns

T2.21.1

SD+ internal

T2.21.2

PMD Input Pair

TX_CLK

TX_EN

TXD[3:0]

CRS

RX_CLK

RXD[3:0]

RX_DV

T2.22.1

70 www.national.com

DP83848H

8.2.23 10 Mb/s Internal Loopback Timing

Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

Parameter Description Notes Min Typ Max Units

T2.23.1 TX_EN to RX_DV Loopback 10 Mb/s internal loopback mode 2 µs

TX_CLK

TX_EN

TXD[3:0]

CRS

RX_CLK

RXD[3:0]

RX_DV

T2.23.1

71 www.national.com

DP83848H

8.2.24 Isolation Timing

8.2.25 25 MHz_OUT Timing

Note: 25 MHz_OUT characteristics are dependent upon the X1 input characteristics.

Parameter Description Notes Min Typ Max Units

T2.24.1 From software clear of bit 10 in

the BMCR register to the transi­tion from Isolate to Normal Mode

100 µs

T2.24.2 From Deassertion of S/W or H/W

Reset to transition from Isolate to
Normal mode

500 µs

Parameter Description Notes Min Typ Max Units

T2.25.1 25 MHz_OUT High/Low Time MII mode 20 ns
T2.25.2 25 MHz_OUT propagation delay Relative to X1 8 ns

Clear bit 10 of BMCR
(return to normal operation

from Isolate mode)

H/W or S/W Reset

(with PHYAD = 00000)

MODE

ISOLATE

NORMAL

T2.24.2

T2.24.1

X1

T2.25.2

25 MHz_OUT

T2.25.1 T2.25.1

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly used
in accordance with instructions for use provided in the labeling,
can be reasonably expected to result in a significant injury to the
user.

2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to af­fect its safety or effectiveness.

National Semiconductor
Corporation

Tel: [phone]
Fax: [phone]
Email: [e-mail]

National Semico nductor
Europe

Fax: [phone]

Email: [e-mail]

Deutsch Tel: [phone]

English Tel: [phone]

Francais Tel: [phone]

National Semiconductor
Japan Ltd.

Tel: [phone]
Fax: [phone]

www.national.com

National Semiconductor
Asia Pacific
Customer Response Group

Tel: [phone]
Fax: [phone]
Email: [e-mail]

BANNED SUBSTANCE COMPLIANCE

National Semiconductor certifies that the products and packing mate rials meet the provisions of the Customer Products Stewardship
Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no “Banned
Substances” as defined in CSP-9-111S2.

Leadfree products are RoHS compliant.

DP83848H PHYTER

®

Mini - Extreme Temperature Single 10/100 Ethernet Transceiver

Physical Dimensions inches (millimeters) unless otherwise noted