Datasheet DM74S112N, DM74S112CW Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS006459 www.fairchildsemi.com

August 1986
Revised April 2000

DM74S112 Dual Negative-Edge-T riggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary

Outputs

DM74S112
Dual Negative-Edge-T riggered Master-Sl ave J-K Flip-Flop

with Preset, Clear, and Complementary Outputs

General Description

This device contains two indepe ndent negative-edge-trig­gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip -flops on the f alling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of t he
negative going edge of the clock pulse. Data on the J and
K inputs can be changed while the clock is HIGH or LOW
without affecting the outputs as long as setup and hold
times are not violated. A low logic leve l on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.

Ordering Code:

Connection Diagram Function Table

H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↓ = Negative going edge of pulse.
Q0 = The output logic level of Q before the indicated input conditions were

established.

* = This configuration is nonstable ; th at is , it will not persist w hen either the

preset and/or clear in puts return to its inactive (H I GH ) level.

Tog gle = Each output changes to the complement of its previous level on

each falling edge of th e c loc k pulse.

Order Number Package Number Package Description

DM74S112 N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

PR CLR CLK J K Q Q

LHXXXH L
HL XXXL H
LLXXXH*H*
HH ↓ LL Q

0

Q

0

HH ↓ HL H L
HH ↓ LH L H
HH ↓ H H Toggle

HHHXXQ

0

Q

0

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DM74S112

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maxim um Ratin gs” are those valu es beyon d which

the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limit s. The parametric values defin ed in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the co ndition s
for actual device operation.

Recommended Operating Conditions

Note 2: CL = 15 pF, RL = 280Ω, TA = 25°C and VCC = 5V.
Note 3: C

L

= 50 pF, RL = 280Ω, TA = 25°C and VCC = 5V.

Note 4: T

A

= 25°C and VCC = 5V.

Note 5: The symbol (↓) indicates the falling edge at the clock pulse is used for reference.

Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

V

CC

Supply Voltage 4.75 5 5.25 V

V

IH

HIGH Level Input Voltage 2 V

V

IL

LOW Level Input Voltage 0.8 V

I

OH

HIGH Level Output Current −1mA

I

OL

LOW Level Output Current 20 mA

f

CLK

Clock Frequency (Note 2) 0 125 80 MHz

f

CLK

Clock Frequency (Note 3) 0 80 60 MHz

t

W

Pulse Width Clock HIGH 6
(Note 2) Clock LOW 6.5

ns

Clear LO W 8
Preset LOW 8

t

W

Pulse Width Clock HIGH 8
(Note 3) Clock LOW 8

ns

Clear LO W 10
Preset LOW 10

t

SU

Setup Time (Note 4)(Note 5) 7↓ ns

t

H

Input Hold Time (Note 4)(Note 5) 0↓ ns

T

A

Free Air Operating Temperature 0 70 °C

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DM74S112

Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

Note 6: All typi c als are at VCC = 5V, TA = 25°C.
Note 7: Clear is tested with preset H I GH and preset is tested with clear HIGH.

Note 8: Not more than one output sh ould be shorted at a time, an d t he duration should not ex ceed one second.
Note 9: With all outputs OPEN, I

CC

is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock input is grounded.

Switching Characteristics

at VCC = 5V and TA = 25°C

Symbol Parameter Conditions Min

Typ

Max Units

(Note 6)

V

I

Input Clamp Voltage VCC = Min, II = − 18 mA −1.2 V

V

OH

HIGH Level VCC = Min, IOH = Max

2.7 3.4 V

Output Voltage V

IL

= Max, VIH = Min

V

OL

LOW Level VCC = Min, IOL = Max

0.5 V

Output Voltage VIH = Min, VIL = Max

I

I

Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA

I

IH

HIGH Level VCC = Max J, K 50
Input Current VI = 2.7V Clear 100

µA

Preset 100
Clock 100

I

IL

LOW Level VCC = Max J, K −1.6
Input Current V

I

= 0.5V Clear −7

mA

(Note 7) Preset −7

Clock −4

I

OS

Short Circuit Output Current VCC = Max (Note 8) −40 −100 mA

I

CC

Supply Current VCC = Max (Note 9) 30 50 mA

RL = 280Ω

Symbol Parameter From (Input)

CL = 15 pF CL = 50 pF

Units

To (Output) Min Max Min Max

f

MAX

Maximum Clock Frequency 80 60 MHz

t

PLH

Propagation Delay Time

Preset to Q 7 9 ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time

Preset to Q 712ns

HIGH-to-LOW Level Output

t

PLH

Propagation Delay Time

Clear to Q

79ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time

Clear to Q 7 12 ns

HIGH-to-LOW Level Output

t

PLH

Propagation Delay Time

Clock to Q or Q 79ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time

Clock to Q or Q 712ns

HIGH-to-LOW Level Output

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DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary

Outputs

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t devices o r syste ms a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical compon ent in any com ponen t of a life su pport
device or system whose failure t o perform can be rea­sonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.

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