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August 1986
Revised March 2000
DM74LS74A
Dual Positive-Edge-Triggered D Flip-Flops with
Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flo ps with complement ary outputs. The info rmation on the D inp ut is accepted by the f lip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly r elated to the
transition time of the rising edg e of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as the data
setup and hold times are not violated . A low logic level on
the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
Ordering Code:
Order Number Package Number Package Description
DM74LS74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS85ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
Connection Diagram Function Table
Inputs Outputs
PR CLR CLK D Q Q
LHXX H L
HLXX L H
L L X X H (Note 1) H (Note 1)
HH↑ HH L
HH↑ LL H
HHLX Q
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↑ = Positive-going Transition
Q0 = The out put logic lev el of Q be fore the in dica ted input con ditio ns were
established.
Note 1: This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to thei r inactive (HIGH) level.
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0
Q
0
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Absolute Maximum Ratings(Note 2)
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
DM74LS74A
Storage Temperature Range −65°C to +150°C
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the c ondit ions
for actual device operation.
Recommended Operating Conditions
Symbol Parameter Min Nom Max Units
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
f
CLK
t
W
t
W
t
SU
t
SU
t
H
T
A
Note 3: CL = 15 pF, RL = 2 kΩ, TA = 25°C, and VCC = 5V.
Note 4: C
Note 5: The symbol (↑) indicates the rising edge of the clock pulse is used for reference.
Note 6: T
Supply Voltage 4.75 5 5.25 V
HIGH Level Input Voltage 2 V
LOW Level Input Voltage 0.8 V
HIGH Level Output Current −0.4 mA
LOW Level Output Current 8 mA
Clock Frequency (Note 3) 0 25 MHz
Clock Frequency (Note 4) 0 20 MHz
Pulse Width Clock HIGH 18
(Note 3) Preset LOW 15 ns
Clear LOW 15
Pulse Width Clock HIGH 25
(Note 4) Preset LOW 20 ns
Clear LOW 20
Setup Time (Note 3)(Note 5) 20↑ ns
Setup Time (Note 4)(Note 5) 25↑ ns
Hold Time (Note 5)(Note 6) 0↑ ns
Free Air Operating Temperature 0 70 °C
= 50 pF, RL = 2 kΩ, TA = 25°C, and VCC = 5V.
L
= 25°C and VCC = 5V.
A
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Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min
V
I
V
OH
V
OL
Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
HIGH Level VCC = Min, IOH = Max
Output Voltage VIL = Max, VIH = Min
2.7 3.4 V
LOW Level VCC = Min, IOL = Max
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
I
I
Input Current @ Max VCC = Max Data 0.1
Input Voltage VI = 7V Clock 0.1
Preset 0.2
Clear 0.2
I
IH
HIGH Level VCC = Max Data 20
Input Current VI = 2.7V Clock 20
Clear 40
Preset 40
I
IL
LOW Level VCC = Max Data −0.4
Input Current VI = 0.4V Clock −0.4
Preset −0.8
Clear −0.8
I
OS
I
CC
Note 7: All typicals are at VCC = 5V, TA = 25°C.
Note 8: Not more than one out put sh ould be shorted at a time, and the duration sh ould not exceed one second. For dev ic es , with fe edback from the outputs,
where shorting the outputs to g r ound ma y ca use the outputs to change logic state an equivale nt te st may be performed where V
and maximum limits reduced by one half from t heir stated values. This is v ery us eful when using automatic test equipment .
Note 9: With all outputs OPEN, I
Short Circuit Output Current VCC = Max (Note 8) −20 −100 mA
Supply Current VCC = Max (Note 9) 4 8 mA
is measured with CLO C K grounded after sett ing the Q and Q outputs HIGH in turn.
CC
Typ
(Note 7)
0.35 0.5
= 2.125V with the minimum
O
Max Units
DM74LS74A
mA
µA
mA
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol Parameter
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency 25 20 MHz
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
From (Input)
To (Output)
CL = 15 pF CL = 50 pF Units
RL = 2 kΩ
Min Max Min Max
Clock to Q or Q 25 35 ns
Clock to Q or Q 30 35 ns
Preset to Q 25 35 ns
Preset to Q 30 35 ns
Clear to Q 25 35 ns
Clear to Q 30 35 ns
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Physical Dimensions inches (millimeters) unless otherwise noted
DM74LS74A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
DM74LS74A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
Package Number N14A
2. A critical component in any componen t of a life su pport
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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