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© 2000 Fairchild Semiconductor Corporation DS009827 www.fairchildsemi.com
October 1988
Revised March 2000
DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
DM74LS299
8-Input Universal Shift/Storage Register with
Common Parallel I/O Pins
General Description
The DM74LS299 is an 8-b it univ ersal shift/stor age r egist er
with 3-STATE outputs. Four modes of opera tion are possi ble: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Separate outputs
are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset
the register.
Features
■ Common I/O for reduced pin count
■ Four operation modes: shift left, shift right, load and
store
■ Separate shift right serial input and shift left se rial input
for easy cascading
■ 3-STATE outputs for bus oriented applications
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol
VCC = Pin 20
GND = Pin 10
Pin Descriptions
Connection Diagram
Order Number Package Number Package Description
DM74LS299WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS299N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin
Names
Description
CP Clock Pulse Input (Active Rising Edge)
D
S0
Serial Data Input for Right Shift
D
S7
Serial Data Input for Left Shift
S0, S1 Mode Select Inputs
MR
Asynchronous Master Reset Input (Active LOW)
OE
1, OE2 3-STATE Output Enable Inputs (Active LOW)
I/O0–I/O7 Parallel Data Inputs or 3-STATE Parallel Outputs
Q0–Q7 Serial Outputs
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DM74LS299
Functional Description
The DM74LS299 contains eight edge- tri g ge red D - type f lip flops and the interstage l ogic necessary to perform synchronous shift left, shift righ t, parallel loa d and hold operations. The type of operation is determi ned by the S0 and
S1, as shown in the Mode Select Table. All flip-flop outputs
are brought out through 3-STATE buffers to separat e I/O
pins that also serve as data inputs in the parallel load
mode. Q0 and Q7 are also brou ght out on other pins for
expansion in serial shifting of longer words.
A LOW signal on MR
overrides the Sele ct and CP inputs
and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change
when the clock is in either st ate prov ided only that th e recommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE
1 or OE2 disables the 3-STATE
buffers and puts the I/O pins in the high impedance stat e.
In this condition the sh ift, hold, load and reset operatio ns
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S0 and S1 in preparation for a parallel load operation.
Mode Select Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock (CP) Transition
Logic Diagram
Inputs
Response
MR
S1 S0 CP
LXXXAsynchronous Reset; Q0–Q7 = LOW
HHH
Parallel Load; I/On→Q
n
HLHShift Right; DS0→Q0, Q0→Q1, etc.
HHL
Shift Left; DS7→Q7, Q7→Q6, etc.
H L L X Hold
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DM74LS299
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.
Recommended Operating Conditions
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.75 5 5.25 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current Q0, Q7 −0.4 mA
I/O0–I/O7 −2.6 mA
I
OL
LOW Level Output Current Q0, Q7 8 mA
I/O0–I/O7 24 mA
T
A
Free Air Operating Temperature 0 70 °C
t
S
(H) Setup Time HIGH or LOW 24
ns
t
S
(L) S0 or S1 to CP 24
t
H
(H) Hold Time HIGH or LOW 0
ns
t
H
(L) S0 or S1 to CP 0
t
S
(H) Setup Time HIGH or LOW 10
ns
t
S
(L) I/On, DS0, DS7 to CP 10
t
H
(H) Hold Time HIGH or LOW 0
ns
t
H
(L) I/On, DS0, DS7 to CP 0
t
W
(H) CP Pulse Width HIGH or LOW 15
ns
t
W
(L) 15
t
W
(L) MR Pulse Width LOW 15 ns
t
REC
Recovery Time
10 ns
MR
to CP
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DM74LS299
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
VCC = +5.0V, TA = +25°C
Symbol Parameter Conditions Min
Typ
Max Units
(Note 2)
V
I
Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
V
OH
HIGH Level VCC = Min, IOH = Max Q0, Q7 2.7 3.4
V
Output Voltage VIL = Max I/O0–I/O7 2.4
V
OL
LOW Level VCC = Min, IOL = Max
0.35 0.5
Output Voltage VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
I
I
Input Current @ Max VCC = Max Inputs 0.1 mA
Input Voltage VI = 7V Sn 0.2 mA
I
IH
HIGH Level VCC = Max, VI = 2.7V Sn 40 µA
Input Current Inputs 20 µA
I
IL
LOW Level VCC = Max, VI = 0.4V Sn −0.8 mA
Input Current Inputs −0.4 mA
I
OS
Short Circuit VCC = Max Q0, Q
7
−20 −100
mA
Output Current (Note 3) I/O0–I/O7−30 −130
I
CC
Supply Current VCC = Max, OE = 4.5V 60 mA
I
OZH
3-STATE Output Off VCC = Max
40 µA
Current HIGH VO = 2.7V
I
OZL
3-STATE Output Off VCC = Max
−400 µA
Current Low VO = 0.4V
Symbol Parameter
RL = 2 kΩ
UnitsCL = 15 pF
Min Max
f
MAX
Maximum Input Frequency 35 MHz
t
PLH
Propagation Delay 26
ns
t
PHL
CP to Q0 or Q7 28
t
PLH
Propagation Delay 25
ns
t
PHL
CP to I/O
n
35
t
PHL
Propagation Delay
28 ns
MR to Q0 or Q7
t
PHL
Propagation Delay
35 ns
MR to I/O
n
t
PZH
Output Enable Time 18
ns
t
PZL
25
t
PHZ
Output Disable Time 15
ns
t
PLZ
20
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DM74LS299
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/ O Pins
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems a re device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component in any compon ent of a l ife supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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