Datasheet DM74LS221SJX, DM74LS221SJ, DM74LS221N, DM74LS221MX, DM74LS221M Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS006409 www.fairchildsemi.com

August 1986
Revised April 2000

DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs

DM74LS221 Dual Non-Retriggerable One-Shot
with Clear and Complementary Outputs

General Description

The DM74LS221 is a dual monostable multivibrator with
Schmitt-trigger input. E ach devi ce has three inp uts permi t­ting the choice of either leading-edge or trailing-e dge trig­gering. Pin (A) is an active-LOW trigger transition input and
pin (B) is an active-HI GH transition Schmitt-trigger input
that allows jitter free triggering for inputs with transition
rates as slow as 1 volt/second. This provides the input with
excellent noise immunity. Additionally an internal latching
circuit at the input stage also provid es a high immunity to
V

CC

noise. The clear (CLR) input can terminate the output

pulse at a predetermined tim e independent of the timing
components. This (CLR) input also serves as a trigger
input when it is pulsed with a low level pulse transition
(



). To obtain the best and trouble free operatio n from
this device please read operati ng ru les as well as th e Fair­child Semiconductor one-shot application notes carefully
and observe recommendations.

Features

■ A dual, highly stable one-shot

■ Compensated for V

CC

and temperature variations

■ Pin-out identical to DM74LS123 (Note 1)

■ Output pulse width range from 30 ns to 70 seconds

■ Hysteresis provided at (B) input for added noise

immunity

■ Direct reset terminates output pulse

■ Triggerable from CLEAR input

■ DTL, TTL compatible

■ Input clamp diodes

Note 1: The pin-out is identical to DM74LS123 but, functionally it is not;
refer to Operating R ules #10 in this datasheet .

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Function Table

H = HIGH Logic Level
L = LOW Logic Level
X = Can Be Either LOW or HIGH

↑ = Positive Going Transition
↓ = Negative Going Trans it ion



= A Positive Pulse



= A Negative Pulse

Note 2: This mode of triggering requires first the B input be set from a
LOW-to-HIGH leve l while the CLEAR input is m aintained at logic LOW
level. Then with the B in put at logic HIGH level , the CLEAR input whos e
positive transition fro m LOW-to-HIGH will trigger an output pulse.

Order Number Package Number Package Description

DM74LS221M M16A 16-Lead Small Outline Integrat ed Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS221SJ M16D 16-Lead Small Out line Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS221N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

CLEAR A B Q Q

LXXLH
XHXLH
XXLLH
HL↑



H ↓ H



↑ (Note 2) L H



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DM74LS221 Dual Non-Retriggerable One-Shot

Functional Description

The basic output pulse width is determined by selection of
an external resistor (R

X

) and capacitor (CX). Once trig-

gered, the basic puls e w idth is independent of f urt her i np ut
transitions and is a functio n of the timing compon ents, or it

may be reduced or termin ated by use of the active low
CLEAR input. Stable output pulse width ranging from 30 ns
to 70 seconds is readily obtainable.

Operating Rules

1. An external resistor (RX) and an external capacitor
(C

X

) are required for prop er op er ati on . Th e val u e of C

X

may vary from 0 to approxima tely 1000 µF. For small
time constants h igh-grade mica, glass, polyp ropylene,
polycarbonate, or polystyrene material capacitor may
be used. For large time c onst ant s use ta nta lum or spe ­cial aluminum capacitor s. If timing capacitor has leak­ages approaching 10 0 nA or if stray capacit ance from
either terminal to gr ound is gr eater than 5 0 pF the tim ­ing equations may not repre sent the pulse width the
device generates.

2. When an electrol ytic capa ci to r is us ed for C

X

a switch-

ing diode is often requir ed for standard TTL one-shots
to prevent high inverse leakage current . Thi s switchin g
diode is not need ed for the DM7 4LS221 one- shot and
should not be used.

Furthermore, if a polarized timing capacitor is used on
the DM74LS221, the positive side of the capacitor

should be connected to the “C

EXT

” pin (Figure 1).

3. For C

X

>> 1000 pF, the output pulse width (tW) is
defined as follows:
t

W

= KRX C

X

where [RX is in kΩ]

[C

X

is in pF]

[t

W

is in ns]

K ≈ Ln2 = 0.70

4. The multiplicative factor K is plotted as a function of C

X

for design considerations: (See Figure 4).

5. For C

X

< 1000 pF see F igure 3 for tW vs. CX family

curves with R

X

as a parameter.

6. To obtain variable pulse widths by remote trim ming,
the following circuit is recommended: (See Figure 2).

7. Output pulse width versus V

CC

and temperatures: Fig-

ure 5 depicts the relationship between pulse width vari­ation versu s V

CC

. Figure 6 depicts pulse width variation

versus temperatures.

8. Duty cycle is defined as t

W

/T × 100 in percentage, if it

goes above 50% the output pulse width will become
shorter. If the duty cycle varies between LOW and
HIGH values, this causes out put pulse w idth to var y, or
jitter (a function of the R

EXT

only). To reduce jitter, R

EXT

should be as large as possible, for example, with
R

EXT

= 100k jitter is not appreciable until the duty cycle

approaches 90%.

9. Under any operating condition C

X

and RX must be kept

as close to the one-shot device pins as possible to min­imize stray capacitance, to reduce noise pick-up, and
to reduce I-R and Ldi/d t voltage devel oped along th eir
connecting paths. If the lead leng th from C

X

to pins (6)

and (7) or pins (14) an d (15) is greate r than 3 cm, for
example, the output pulse width might be quite different
from values predicte d from the appropriat e equations.
A non-inductive and low capacitive path is necessary to
ensure complete discharge of C

X

in each cycle of its

operation so that the output pulse width will b e accu­rate.

10. Although the DM74LS221's pin-out is id entical to the
DM74LS123 it should be remembered that they are not
functionally identica l. The DM74LS123 is a retrigger­able device such that the output is dependent upon the
input transitions when its output “Q” is at the “High”
state. Furthermore, it is recommended for the
DM74LS123 to externally ground the C

EXT

pin for

improved system performance. However, this pin on
the DM74LS221 is not an int ernal connection to the
device gro un d. He nc e , if s u bst i tu tion of an DM 74LS221
onto an DM74LS123 d esi g n la yout w he re the C

EXT

pin

is wired to the ground, the device will not function.

11. V

CC

and ground wiring shoul d conform to good high-

frequency standards and practices so that switching
transients on the V

CC

and ground return leads do not

cause interaction between one-shots. A 0.01 µF to 0.10
µF bypass capacitor (disk ce ramic or monolithic type)
from V

CC

to ground is necessar y on each de vice. Fur-

thermore, the bypass capacitor sho uld be located as
close to the V

CC

-pin as spac e permits.

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DM74LS221 Dual Non-Retriggerable One-Shot

Operating Rules (Continued)

FIGURE 1.

Note: “R

remote

” should be as close to th e one-shot as possible.

FIGURE 2.

FIGURE 3.

FIGURE 4.

FIGURE 5. FIGURE 6.

Note: For further detailed dev ic e c haracteristics and output performance, pleas e refer to the Fairchild Sem ic onductor one-shot ap plication note AN-372.

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DM74LS221 Dual Non-Retriggerable One-Shot

Absolute Maximum Ratings(Note 3)

Note 3: The “Absolute Maximum Ratings” are those values beyon d which

the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limit s. The parametric values defin ed in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recomme nded O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Recommended Operating Conditions

Note 4: TA = 25°C and VCC = 5V.

Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

V

CC

Supply Voltage 4.75 5 5.25 V

V

T+

Positive-Going Input Threshold Voltage

12V

at the A Input (V

CC

= Min)

V

T−

Negative-Going Input Threshold Voltage

0.8 1 V

at the A Input (V

CC

= Min)

V

T+

Positive-Going Input Threshold Voltage

12V

at the B Input (V

CC

= Min)

V

T−

Negative-Going Input Threshold Voltage

0.8 0.9 V

at the B Input (V

CC

= Min)

I

OH

HIGH Level Output Current −0.4 mA

I

OL

LOW Level Output Current 8 mA

t

W

Pulse Width Data 40

ns

(Note 4) Clear 40

t

REL

Clear Release Time (Note 4) 15 ns
Rate of Rise or Fall of

1

Schmitt Input (B) (Note 4)
Rate of Rise or Fall of

1

Logic Input (A) (Note 4)

R

EXT

External Timing Resistor (Note 4) 1.4 100 kΩ

C

EXT

External Timing Capacitance (Note 4) 0 1000 µF

DC Duty Cycle R

T

= 2 kΩ 50

%

(Note 4) R

T

= R

EXT

(Max) 60

T

A

Free Air Operating T emperature 0 70 °C

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DM74LS221 Dual Non-Retriggerable One-Shot

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 5: All typi c als are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output sh ould be shorted at a time, an d t he duration should not ex ceed one second.

Switching Characteristics

at V

CC

= 5V and T

A

= 25°C

Symbol Parameter Conditions Min

Typ

Max Units

(Note 5)

V

I

Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V

V

OH

HIGH Level VCC = Min, IOH = Max

2.7 3.4 V

Output Voltage V

IL

= Max, VIH = Min

V

OL

LOW Level VCC = Min, IOL = Max

0.35 0.5

Output Voltage VIL = Max, VIH = Min V

V

CC

= Min, IOL = 4 mA 0.4

I

I

Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

I

IH

HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

I

IL

LOW Level VCC = Max A1, A2 −0.4
Input Current V

I

= 0.4V B −0.8 mA

Clear −0.8

I

OS

Short Circuit VCC = Max

−20 −100 mA

Output Current (Note 6)

I

CC

Supply Current VCC = Max Quiescent 4.7 11

mA

Triggered 19 27

Symbol Parameter

From (Input)

Conditions Min Max Units

To (Output)

t

PLH

Propagation Delay Time A1, A2 C

EXT

= 80 pF

70 ns

LOW-to-HIGH Level Output to Q R

EXT

= 2 kΩ

t

PLH

Propagation Delay Time B CL = 15 pF

55 ns

LOW-to-HIGH Level Output to Q R

L

= 2 kΩ

t

PHL

Propagation Delay Time A1, A2

80 ns

HIGH-to-LOW Level Output to Q

t

PHL

Propagation Delay Time B

65 ns

HIGH-to-LOW Level Output to Q

t

PLH

Propagation Delay Time Clear to

65 ns

LOW-to-HIGH Level Output Q

t

PHL

Propagation Delay Time Clear

55 ns

HIGH-to-LOW Level Output to Q

t

W(out)

Output Pulse A1, A2 C

EXT

= 0

Width Using Zero to Q, Q

R

EXT

= 2 kΩ

20 70 ns

Timing Capacitance RL = 2 kΩ

CL = 15 pF

t

W(out)

Output Pulse A1, A2 C

EXT

= 100 pF

Width Using External to Q, Q R

EXT

= 10 kΩ

600 750 ns

Timing Resistor RL = 2 kΩ

CL = 15 pF

C

EXT

= 1 µF

R

EXT

= 10 kΩ

67.5ms

RL = 2 kΩ

CL = 15 pF

C

EXT

= 80 pF

R

EXT

= 2 kΩ

70 150 ns

RL = 2 kΩ

CL = 15 pF

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DM74LS221 Dual Non-Retriggerable One-Shot

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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DM74LS221 Dual Non-Retriggerable One-Shot

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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