Datasheet DM74LS194AN, DM74LS194AMX, DM74LS194AM Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS006407 www.fairchildsemi.com

August 1986
Revised March 2000

DM74LS194A 4-Bit Bidirectional Universal Shift Register

DM74LS194A
4-Bit Bidirectional Universal Shift Register

General Description

This bidirectional shift register is designed to incorp orate
virtually all of the features a system designer may want in a
shift register; they feature p arallel inputs, parallel outputs,
right-shift and left-shi ft serial inputs, operating-mode-co n­trol inputs, and a dire ct overriding clear lin e. The register
has four distinct modes of operation, namely:

Parallel (broadside) load
Shift right (in the direction Q

A

toward QD)

Shift left (in the direction Q

D

toward QA)

Inhibit clock (do nothing)

Synchronous parallel loading is accomplished by applying
the four bits of da ta and taking both mode control inputs,
S0 and S1, HIGH. T he data is load ed into the associated
flip-flops and appear at the outputs after the positive transi­tion of the clock in put. During loading, seri al data flow is
inhibited.

Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is HIGH a nd S1 is LOW.
Serial data for this mode is entered at the shift-right data
input. When S0 is LOW and S1 is HIGH, data shifts left
synchronously and new data is entered at the shift-left
serial input.

Clocking of the flip-flop is inhibited when both mode control
inputs are LOW.

Features

■ Parallel inputs and outputs

■ Four operating modes:

Synchronous parallel load
Right shift
Left shift
Do nothing

■ Positive edge-triggered clocking

■ Direct overriding clear

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

DM74LS194AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS194AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74LS194A

Function Table

H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH lev el
a, b, c, d = The level of steady state input at inputs A, B, C or D, re s pec t iv ely.
Q

A0

, QB0, QC0, QD0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established.

Q

An

, QBn, QCn, QDn = The level of QA, QB, QC, respectively, before the most -recent ↑ transition of the clock.

Logic Diagram

Inputs Outputs

Clear

Mode

Clock

Serial Parallel

Q

AQBQCQD

S1 S0 Left Right A B C D

L X X X X X XXXX L L L L
H X X L X X XXXXQ

A0QB0QC0QD0

HHH↑ XXabcdabcd
HLH↑ X H XXXX H Q

AnQBnQCn

HLH↑ X L XXXX L QAnQBnQ

Cn

HHL ↑ H X XXXXQBnQCnQ

Dn

H

HHL ↑ L X XXXXQ

BnQCnQDn

L

H L L X X X XXXXQ

A0QB0QC0QD0

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DM74LS194A

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich

the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.

Recommended Operating Conditions

Note 2: CL = 15 pF, TA = 25°C and VCC = 5V.
Note 3: C

L

= 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 4: T

A

= 25°C and VCC = 5V.

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 7: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR, and the serial inputs, I

CC

is tested with momentary ground,

then 4.5V applied to CLOCK.

Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

V

CC

Supply Voltage 4.75 5 5.25 V

V

IH

HIGH Level Input Voltage 2 V

V

IL

LOW Level Input Voltage 0.8 V

I

OH

HIGH Level Output Current −0.4 mA

I

OL

LOW Level Output Current 8 mA

f

CLK

Clock Frequency (Note 2) 0 25

MHz

Clock Frequency (Note 3) 0 20

t

W

Pulse Width Clock 20

ns

(Note 4) Clear 20

t

SU

Setup Time Mode 30

ns

(Note 4) Data 20

t

H

Hold Time (Note 4) 0 ns

t

REL

Clear Release Time (Note 4) 25 ns

T

A

Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min

Typ

Max Units

(Note 5)

V

I

Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V

V

OH

HIGH Level VCC = Min, IOH = Max

2.7 3.4 V

Output Voltage VIL = Max, VIH = Min

V

OL

LOW Level VCC = Min, IOL = Max

0.35 0.5

Output Voltage VIL = Max, VIH = Min V

IOL = 4 mA, VCC = Min 0.4

I

I

Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

I

IH

HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

I

IL

LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

I

OS

Short Circuit Output Current VCC = Max (Note 6) −20 −100 mA

I

CC

Supply Current VCC = Max (Note 7) 15 23 mA

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DM74LS194A

Switching Characteristics

at VCC = 5V and TA = 25°C

Note 8: All typicals are at VCC = 5V, TA = 25°C.
Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 10: With all outputs ope n, inputs A through D grounded, a nd 4.5V ap plied to S0 , S1, CLEA R, and the serial inpu ts, I

CC

is tested with momentary

ground, then 4.5V applied to CLOCK.

Timing Diagram

Typical Clear, Load, Right-Shift, Left-Shift, Inhibit, and Clear Sequences

Symbol Parameter

From (Input)

CL = 50 pF, RL = 2 kΩ

Units

To (Output) Min Max

f

MAX

Maximum Clock Frequency 20 MHz

t

PLH

Propagation Delay Time Clock to Any Q

26 ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time Clock to Any Q

35 ns

HIGH-to-LOW Level Output

t

PHL

Propagation Delay Time Clear to Any Q

38 ns

HIGH-to-LOW Output

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DM74LS194A

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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DM74LS194A 4-Bit Bidirectional Universal Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical compon ent i n any compon ent of a life su pport
device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.

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