Datasheet DM74LS166WM, DM74LS166N, DM74LS166MX, DM74LS166M, DM74LS166WMX Datasheet (Fairchild Semiconductor)

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August 1986 Revised March 2000

DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register

General Description

These parallel-in or serial-in, serial-out shift registers feature gated clock inputs and an ov erriding clear input. All inputs are buffered to l ower the d rive requirem ents to one normalized load, and input clamping diodes minimize switching transients to simplify system design. The load mode is established by the shift/load input. When HIGH, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When LOW, the parallel (broadside) data inputs are enabled and synchronou s load ing occurs on the next clock pulse. During parallel loa ding, serial data flow i s inhibited.

Clocking is accomplished on the LOW-to-HIGH level edge of the clock pulse through a two-input NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inpu ts HIGH inhibits clocking; holding either LOW e na bles t he other clock input. This allows the system clock to be free running, and the register can be stopped on c ommand with the other clock in put. The clock-inhibit input shou ld be changed to the high level only while the clock input is HIGH. A buffered, direct cl ear input overrides all other inputs, including the clock, and sets all flip-flops to zero.

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

DM74LS166M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JED EC MS-012, 0.150 Narrow DM74LS166WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS166N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74LS166

Function Table

H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH lev el

a…h = The level of steady-state input at inputs A through H, respectively Q

, QB0, QH0 = The level of QA, QB, QH, respectively, before the indicated steady-state input co nditions were establis hed

, QGn, = The level of QA, QG, respectively, before the most recent ↑ transition of the clock

Logic Diagram

Timing Diagram

Typical Clear, Shift, Load, Inhibit and Shift Sequences

Inputs Internal Output

Clear

Shift/ Clock

Clock Serial

Parallel Outputs Q

Load Inhibit

A…H Q

LXXXXXLLL HXLLXXQ

HLL↑ X a…habh

HHL ↑ HXHQ

HHL ↑ LXLQAnQ

HXH↑ XXQA0Q

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DM74LS166

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich

the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s for actual device operation.

Recommended Operating Conditions

Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 3: C

= 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 4: T

= 25°C and VCC = 5V.

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 7: With all outpu ts OP EN, 4.5 V applied to the se rial inp ut, all ot her input s exce pt the C LOCK g rounded , I

is measured after a mome ntary gro und,

then 4.5V is applied to the CLOCK.

Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

Supply Voltage 4.75 5 5.25 V

HIGH Level Input Voltage 2 V

LOW Level Input Voltage 0.8 V

HIGH Level Output Current −0.4 mA

LOW Level Output Current 8 mA

CLK

Clock Frequency (Note 2) 0 25 MHz Clock Frequency (Note 3) 0 20 MHz

Pulse Width (Note 4) Clock 20

Clear 20

Setup Time (Note 4) Mode 30

Data 20

Hold Time (Note 4) 0 ns

Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min

Typ

Max Units

(Note 5)

Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V

HIGH Level VCC = Min, IOH = Max

2.7 3.4 V

Output Voltage VIL = Max, VIH = Min

LOW Level VCC = Min, IOL = Max

0.35 0.5

Output Voltage VIL = Max, VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

Short Circuit Output Current VCC = Max (Note 6) −20 −100 mA

Supply Current VCC = Max (Note 7) 22 38 mA

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DM74LS166

Switching Characteristics

at VCC = 5V and TA = 25°C

Parameter Measurement Information

Voltage Waveforms

Test Table for Synchronous Inputs

Note A: The clock pulse has the fo llowing characteristics: t

W(clock)

≥ 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics:

W(clear)

≥ 20 ns and t

HOLD

= 0 ns. When testing f

MAX

, vary the clock PRR.

Note B: A clear pulse is applied prior to each test. Note C: Propagation delay times (t

PLH

and t

PHL

) are measured at t

n+1

. Proper shifting of data is ve rif ied at t

n+8

with a functional test.

Note D: t

= bit time before clocking transition

n+1

= bit time after one clocking transition

n+8

= bit time after eight clocking transitions

Note E: V

REF

= 1.3V.

From (Input)

RL = 2 kΩ

Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units

Min Max Min Max

MAX

Maximum Clock Frequency 25 20 MHz

PLH

Propagation Delay Time

Clock to Output 8 35 38 ns

LOW-to-HIGH Level Output

PHL

Propagation Delay Time

Clock to Output 8 35 41 ns

HIGH-to-LOW Level Output

PHL

Propagation Delay Time

Clear to Output 6 30 36 ns

HIGH-to-LOW Level Output

Data Input Shift/Load Output Tested

for Test (See Note C)

H0VQ

at T

N+1

Serial Input 4.5V QH at T

N+8

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DM74LS166

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M16B

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DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

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