Datasheet DM74LS165WMX, DM74LS165WM, DM74LS165N, DM74LS165MX, DM74LS165M Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS006399 www.fairchildsemi.com

August 1986
Revised March 2000

DM74LS165 8-Bit Parallel In/Serial Output Shift Registers

DM74LS165
8-Bit Parallel In/Serial Output Shift Registers

General Description

This device is an 8-bit se rial sh ift regi ster wh ich shif ts data
in the direction of Q

A

toward QH when clocked. Parallel-in

access is made available by eight individual direct data
inputs, which are enabled by a low level at the shift/load
input. These register s also feature gat ed clock inputs and
complementary outputs from the eighth bit.

Clocking is accomplished through a 2-input NOR gate, per­mitting one input to be used as a clock-inhibit function.
Holding either of the clock inputs HIGH inhibits clocking,
and holding either clock input LOW with the load input
HIGH enables the other clock input. Th e clock-inhibit input
should be changed to the high level onl y while the clock
input is HIGH. Parallel loading is inhibited as lo ng as the
load input is HIGH. D ata at the parallel in puts are loaded
directly into the register on a HIGH-to-LOW transition of the
shift/load input, regardless of th e logic levels on the clock,
clock inhibit, or serial inputs.

Features

■ Complementary outputs

■ Direct overriding (data) inputs

■ Gated clock inputs

■ Parallel-to-serial data conversion

■ Typical frequency 35 MHz

■ Typical power dissipation 105 mW

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Function Table

H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don't Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
a...h = The level of steady-state input at inputs A through H, respectively.
Q

A0

, QB0, QH0 = The level of QA, QB, or QH, respectively, before the

indicated steady-s ta t e input conditions were es t ablished.

Q

An

, QGn = The level of QA or QG, respectively, before the most recent

↑ transition of the clock.

Order Number Package Number Package Description

DM74LS165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS165WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Internal
Shift/ Clock Clock Serial Parallel Outputs Output
Load Inhibit A...H

Q

AQBQH

L X X X a...h a b h

HL LX XQ

A0QB0QH0

HL ↑ HXHQAnQ

Gn

HL ↑ LXLQAnQ

Gn

HHXX XQA0QB0Q

H0

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DM74LS165

Logic Diagram

Timing Diagram

Typical Shift, Load, and Inhibit Sequences

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DM74LS165

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich

the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.

Recommended Operating Conditions

Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V
Note 3: C

L

= 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V

Note 4: T

A

= 25°C and VCC = 5V.

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 5: All typicals are at VCC = 5V, TA = 25° C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7: With all outputs OPEN, clock inhibit and shift/load at 4.5V, and a clock pulse applied to the CLOCK input, I

CC

is measured first with the parallel inputs

at 4.5V, then again grounded.

Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

V

CC

Supply Voltage 4.75 5 5.25 V

V

IH

HIGH Level Input Voltage 2 V

V

IL

LOW Level Input Voltage 0.8 V

I

OH

HIGH Level Output Current −0.4 mA

I

OL

LOW Level Output Current 8 mA

f

CLK

Clock Frequency (Note 2) 0 25 MHz

f

CLK

Clock Frequency (Note 3) 0 20 MHz

t

W

Pulse Width Clock 25

ns

(Note 3) Load 15

t

SU

Setup Time Parallel 10
(Note 4) Serial 20

ns

Enable 30
Shift 45

t

H

Hold Time (Note 4) 0 ns

T

A

Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min

Typ

Max Units

(Note 5)

V

I

Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V

V

OH

HIGH Level VCC = Min, IOH = Max

2.7 3.4 V

Output Voltage VIL = Max, VIH = Min

V

OL

LOW Level VCC = Min, IOL = Max 0.4
Output Voltage VIL = Max, VIH = Min 0.35 0.5 V

IOL = 4 mA, VCC = Min 0.25 0.4

I

I

Input Current @ Max VCC = Max, VI = 7V Shift/Load 0.3

mA

Input Voltage Others 0.1

I

IH

HIGH Level VCC = Max Shift/Load 60

µA

Input Current VI = 2.7V Others 20

I

IL

LOW Level VCC = Max Shift/Load −1.2

mA

Input Current VI = 0.4V Others −0.4

I

OS

Short Circuit Output Current VCC = Max (Note 6) −20 −100 mA

I

CC

Supply Current VCC = Max (Note 7) 21 36 mA

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DM74LS165

Switching Characteristics

at VCC = 5V and TA = 25°C

Symbol Parameter

From (Input)

CL = 15 pF RL = 2 kΩ, CL = 50 pF

Units

To (Output) Min Max Min Max

f

MAX

Maximum Clock Frequency 25 20 MHz

t

PLH

Propagation Delay Time

Load to Any Q 35 37 ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time

Load to Any Q 35 42 ns

HIGH-to-LOW Level Output

t

PLH

Propagation Delay Time

Clock to Any Q 40 42 ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time

Clock to Any Q 40 47 ns

HIGH-to-LOW Level Output

t

PLH

Propagation Delay Time

H to Q

H

25 27 ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time

H to Q

H

30 37 ns

HIGH-to-LOW Level Output

t

PLH

Propagation Delay Time

H to Q

H

30 32 ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time

H to Q

H

25 32 ns

HIGH-to-LOW Level Output

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DM74LS165

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M16B

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DM74LS165 8-Bit Parallel In/Serial Output Shift Regist ers

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

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device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the life su pp ort
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