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© 2000 Fairchild Semiconductor Corporation DS006292 www.fairchildsemi.com
April 1984
Revised March 2000
DM74AS169A Synchronous 4-Bit Binary Up/Down Counter
DM74AS169A
Synchronous 4-Bit Binary Up/Down Counter
General Description
These synchronous presettabl e counters feature an internal carry look ahe ad for c ascading i n high speed co unting
applications. The DM74AS169 is a 4-bit binary up/down
counter. The carry output is decoded to prevent spikes during normal mode of counting operation. Synchronous operation is provided so th at outputs change coincident with
each other when so in structed by count ena ble inputs a nd
internal gating. This mode of op eration elim inates the output counting spikes which are normally associated with
asynchronous (ripple clock) counters. A buffered clock
input triggers the four flip-flops on the rising (positive going)
edge of clock input waveform.
These counters are fully programmable; that is, the outputs
may each be preset either HIGH or LOW. The load input
circuitry allows loading with carry-enable output of cascaded counters. As loading is synchr onous, setting up a
LOW level at the load input disables the counter and
causes the outputs to a gree with the data inputs after the
next clock pulse.
The carry look-ahead cir cuitry permits casca ding counters
for n-bit synchronous applications without additional gating.
Both count enable inputs (P
and T) must be LOW to count.
The direction of the co unt is determ ined b y the leve l of t he
up/down input. When the input is HIGH, the counter counts
UP; when LOW, it counts DOWN . Inpu t T is fed fo rwa rd to
enable the carry outputs. The carry output thus enabled will
produce a LOW level output pulse w ith a d uration appro ximately equal to the HIGH portio n of the QA output when
counting UP, and approximately equal to t he LOW port ion
of the QA output when counting DOWN. This LOW level
overflow carry pulse can be used to enable s uccessively
cascaded stages. Transitions at the enable P
or T inputs
are allowed regardless of the level of the clock input.
The control function s for these counters are fully synchr o-
nous. Changes at control inpu ts (enab le P
, enable T, load,
up/down) which modify the opera ting mode have no effect
until clocking occurs. The func tion of the counte r (whether
enabled, disabled, loading or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.
Features
■ Switching Specifications at 50 pF
■ Switching Specifications gua ranteed over full tempera-
ture and V
CC
range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
■ Improved AC performance over Schottky and low power
Schottky counterparts
■ Synchronously programmable
■ Internal look ahead for fast counting
■ Carry out put for n-bit cascading
■ Synchronous counting
■ Load control line
■ ESD inputs
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Order Number Package Number Package Description
DM74AS169AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS169AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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DM74AS169A
Connection Diagram
Logic Diagram
DM74AS169A
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DM74AS169A
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C
Note 2: The output con dit ions have been chosen to produce a current that closely approximates one half of the true s hort circuit output current, IOS.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Typical θ
JA
N Package 71.5°C/W
M Package 101.0°C/W
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.5 5 5.5 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current −2mA
I
OL
LOW Level Output Current 20 mA
f
CLK
Clock Frequency 0 75 MHz
t
SU
t
setup
, Set-up Time Data; A, B, C, D 8 ns
En P
, En T 8ns
LOAD
8ns
U/D
11 ns
t
H
t
hold
, Hold Time Data; A, B, C, D 0 ns
En P
, En T 0ns
LOAD
0ns
U/D
0ns
t
WCLK
Width of Clock Pulse 6.7 ns
t
A
Free Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min Typ Max Units
V
IK
Input Clamp Voltage VCC = 4.5V, II = −18 mA −1.2 V
V
OH
HIGH Level IOH = −2 mA,
VCC − 2V
Output Voltage VCC = 4.5V to 5.5V
V
OL
LOW Level VCC = 4.5V,
0.35 0.5 V
Output Voltage IOL = 20 mA
I
I
Input Current @ Max VCC = 5.5V,
LOAD, ENT, U/D
0.2
mA
Input Voltage VIH = 7V Others 0.1
I
IH
HIGH Level Input Current VCC = 5.5V,
LOAD, ENT, U/D
40
µA
VIH = 2.7V Others 20
I
IL
LOW Level Input Current VCC = 5.5V,
CLK, DATA, ENP
−0.5
mA
VIL = 0.4V
LOAD, ENT, U/D
−1
IO (Note 2) Output Drive Current VCC = 5.5V, VO = 2.25V −30 −112 mA
I
CC
Supply Current VCC = 5.5V 46 63 mA
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DM74AS169A
Switching Characteristics
over recommended operating free air temperature range
Note 3: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level
of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If t he count is
maximum, the ripp le carry output will be out of phase.
Symbol Parameter Conditions From To Min Max Units
f
MAX
Maximum Clock Frequency VCC = 4.5V to 5.5V 75 MHz
t
PLH
Propagation Delay Time RL = 500Ω
Clock RIPPLE Carry 3 16.5 ns
LOW-to-HIGH Level Output CL = 50 pF
t
PHL
Propagation Delay Time
Clock RIPPLE Carry 2 13 ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Clock Any Q 1 7 ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock Any Q 2 13 ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
En T RIPPLE Carry 1.5 9 ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
En T RIPPLE Carry 1.5 9 ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
U/D
RIPPLE Carry 2 12 ns
LOW-to-HIGH Level Output (Note 3)
t
PHL
Propagation Delay Time
U/D
RIPPLE Carry 2 13 ns
HIGH-to-LOW Level Output (Note 3)
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DM74AS169A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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DM74AS169A Synchronous 4-Bit Binary Up/Down Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
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SEMICONDUCTOR CORPORATION. As used herein:
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which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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