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© 2000 Fairchild Semiconductor Corporation DS009162 www.fairchildsemi.com
October 1986
Revised February 2000
DM74ALS563A Octal D-Type Transparent Latch with 3-STATE Output
DM74ALS563A
Octal D-Type Transparent Latch with 3-STATE Output
General Description
These 8-bit register s feature totem-pole 3- STATE outputs
designed specifically fo r driving highly-capacitive or relatively low-impedance loa ds. Th e hi gh -im ped ance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bu s-or ga nized sy stem w ith ou t n eed fo r interface or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight inverting latches of the DM74ALS563A are transparent D-type latches. While the e nable ( G) is HIGH th e Q
outputs will follow the da ta (D) inputs. W hen the enable is
taken LOW the output will be latched at the complement of
the level of the data that was set up.
A buffered output control input ca n be used to place the
eight outputs in either a normal l ogic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-impedance state the outputs ne ither load nor dr ive the bus lines
significantly.
The output control does not affect the i nternal oper ation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full tempera-
ture and V
CC
range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ 3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Order Number Package Number Package Description
DM74ALS563AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS563AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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DM74ALS563A
Function Table
L = LOW State
H = HIGH State
X = Don’t Care
Z = High Impedance State
Q
0
= Previous Condit ion of Q
Logic Diagram
Output Enable D Output
Control G Q
LHHL
LHLH
LLXQ
0
HXXZ
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DM74ALS563A
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.
Recommended Operating Conditions
Note 2: The (↓) arrow in dic ates the negative edge of the enable is used for ref erence.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Supply Voltage 7V
Input Voltage 7V
Voltage Applied to Disabled Output 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Typical θ
JA
N Package 56.0°C/W
M Package 75.0°C/W
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.5 5 5.5 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current −2.6 mA
I
OL
LOW Level Output Current 24 mA
t
W
Width of Enable Pulse, HIGH or LOW 15 ns
t
SU
Data Setup Time (Note 2) 10↓ ns
t
H
Data Hold Time (Note 2) 10↓ ns
T
A
Free Air Operating T emperature 0 70 °C
Symbol Parameter Conditions Min Typ Max Units
V
IK
Input Clamp Voltage VCC = 4.5V, II = −18 mA −1.2 V
V
OH
HIGH Level VCC = 4.5V
IOH = Max 2.4 3.2 V
Output Voltage VIL = VIL Max
VCC = 4.5V to 5.5V IOH = −400 µAVCC − 2V
V
OL
LOW Level VCC = 4.5V IOL = 12 mA 0.25 0.4 V
Output Voltage VIH = 2V IOL = 24 mA 0.35 0.5 V
I
I
Input Current @ Maximum
VCC = 5.5V, VIH = 7V 0.1 mA
Input Voltage
I
IH
HIGH Level Input Current VCC = 5.5V, VIH = 2.7V 20 µA
I
IL
LOW Level Input Current VCC = 5.5V, VIL = 0.4V −0.1 mA
I
O
Output Drive Current VCC = 5.5V, VO = 2.25V −30 −112 mA
I
OZH
OFF-State Output Current VCC = 5.5V, VIH = 2V
20 µA
HIGH Level Voltage Applied VO = 2.7V
I
OZL
OFF-State Output Current VCC = 5.5V, VIH = 2V
−20 µA
LOW Level Voltage Applied VO = 0.4V
I
CC
Supply Current VCC = 5.5V Outputs HIGH 10 17 mA
Outputs OPEN Outputs LOW 16 2 6 mA
Outputs Disabled 17 29 mA
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DM74ALS563A
Switching Characteristics
over recommended operating free air temperature range
Symbol Parameter Conditions From To Min Max Units
t
PLH
Propagation Delay Time VCC = 4.5V to 5.5V
Data Any Q 318ns
LOW-to-HIGH Level Output RL = 500Ω
t
PHL
Propagation Delay Time CL = 50 pF
Data Any Q 314ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Enable Any Q 822ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Enable Any Q 821ns
HIGH-to-LOW Level Output
t
PZH
Output Enable Time Output
Any Q 418ns
to HIGH Level Output Control
t
PZL
Output Enable Time Output
Any Q 418ns
to LOW Level Output Control
t
PHZ
Output Disable Time Output
Any Q 210ns
from HIGH Level Output Control
t
PLZ
Output Disable Time Output
Any Q 315ns
from LOW Level Output Control
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DM74ALS563A
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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DM74ALS563A Octal D-Type Transparent Latch with 3-STATE Output
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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