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DM74ALS109A
DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear
April 1984
Revised February 2000
Dual J-K
Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS109A is a dual edge-triggered flip-flop. Each
flip-flop has individual J, K
and also complementary Q and Q
Information at input J o r K
the positive going edge of the clock pulse. Cl ock trigg ering
occurs at a voltage level of the clock pulse and is not
directly related to t he transition time of the p ositive going
pulse. When the clock in put is at eith er the HIGH or LOW
level, the J, K
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
The J-K
J and K
input signal has no effect.
design allows operation as a D flip-flop by tying the
inputs together.
, clock, clear and preset inputs,
outputs.
is transferred to th e Q outp ut on
Ordering Code:
Order Number Package Number Package Description
DM74ALS109AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS109AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Connection Diagram Function Table
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full tempera-
ture and V
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Functionally and pin for pin compatible with Schottky
and LS TTL counterpart
■ Improved AC performance over LS 109 at a pproxim ately
half the power
PR
LHXXX H L
HLXXX L H
L L X X X H (Note 1) H (Note 1)
HH↑ LL L H
HH↑ H L TOGGLE
HH↑ LH Q
HH↑ HH H L
HHLXX Q
L = LOW State
H = HIGH State
X = Don't Care
↑ = Positive Edge Transition,
= Previous Condit ion of Q
Q
0
Note 1: This condition is nonstable; it will not persist when presen t and
clear inputs return to th eir inactive (HIGH) lev el. The output leve ls in this
condition are not guaranteed to meet the V
range
CC
Inputs Outputs
CLR CK J K QQ
Q
Q
specification.
OH
0
0
0
0
© 2000 Fairchild Semiconductor Corporation DS006196 www.fairchildsemi.com
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Logic Diagram
DM74ALS109A
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Absolute Maximum Ratings(Note 2)
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Typical θ
JA
N Package 82.5°C/W
M Package 111.5°C/W
Note 2: The “Absolute M aximu m R atin gs” are t hose valu es b eyo nd w hich
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condit ions
for actual device operation.
Recommended Operating Conditions
Symbol Parameter Min Nom Max Units
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
t
W(CLK)
t
W
t
SU
t
H
T
A
Note 3: The (↑) arrow indicates t he positive edge of the Clock is used for reference.
Supply Voltage 4.5 5 5.5 V
HIGH Level Input Voltage 2 V
LOW Level In put Voltage 0.8 V
HIGH Level Output Current −0.4 mA
LOW Level Ou tput Current 8 mA
Clock Frequency 0 34 MHz
Pulse Width Clock HIGH 14.5 ns
Clock LOW 14.5 ns
Pulse Width (Note 3) Preset and Clear 15 ns
Data Setup Time J or K 15↑ ns
(Note 3)
or CLR inactive 10↑
PRE
Data Hold Time 0↑ ns
Free Air Operating Temperature 0 70 °C
DM74ALS109A
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Electrical Characteristics
over recommended operating free-air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Symbol Parameter Conditions Min Typ Max Units
DM74ALS109A
V
IK
V
OH
V
OL
Input Clamp Voltage VCC = 4.5V, II = −18 mA −1.5 V
HIGH Level IOH = −400 µA
Output Voltage VCC = 4.5V to 5.5V
LOW Level VCC = 4.5V
Output Voltage VIH = 2V
IOL = 4 mA 0.25 0.4 V
VCC − 2V
IOL = 8 mA 0.35 0.5 V
I
I
Input Current at Max VCC = 5.5V, Clock, J, K 0.1
Input Voltage VIH = 7V Preset, Clear 0.2
I
IH
High Level VCC = 5.5V, Clock, J, K 20
Input Current VIH = 2.7V Preset, Clear 40
I
IL
Low Level VCC = 5.5V, Clock, J, K −0.2
Input Current VIL = 0.4V Preset, Clear −0.4
IO (Note 4) Output Drive Current VCC = 5.5V, VO = 2.25V −30 −112 mA
I
CC
Note 4: The output c onditions have been ch os en to produce a current t hat closely approximates one half of the true short circuit output current, IOS.
Note 5: I
Supply Current VCC = 5.5V (Note 5) 2.4 4 mA
is measured with J, K, CLK and PRESET grounded, th en with J, K, CLK and CLEAR grounded.
CC
Switching Characteristics
over recommended operating free air temperature range
Symbol Parameter Conditions From To Min Max Units
f
t
t
t
t
MAX
PLH
PHL
PLH
PHL
Maximum Clock Frequency VCC = 4.5V to 5.5V 34 MHz
Propagation Delay Time RL = 500Ω
LOW-to-HIGH Level Output CL = 50 pF
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Preset or Clear Q or Q 313ns
Preset or Clear Q or Q 515ns
Clock Q or Q 516ns
Clock Q or Q 518ns
mA
µA
mA
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Physical Dimensions inches (millimeters) unless otherwise noted
DM74ALS109A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
2. A critical component in any compon ent of a l ife supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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