Datasheet DM74174 Datasheet (Fairchild)

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DM74174 Hex/Quad D-Type Flip-Flop with Clear

September 1986 Revised February 2000

General Description

These positive-edg e trigge re d flip-fl ops ut iliz e TTL ci rcuitry to implement D-type flip-flop logic. All have a direct clear input.

Information at the D inputs meeting the setup and hold time requirements is transfer red to the Q outputs on the positive-going edge of the clock pul se. Clock triggerin g occurs at a particular voltage level and is not directly related to the transition time of the pos itive-goin g pulse. When the clock input is at either the HIGH or LOW level, the D inpu t sig nal has no effect at the output.

Features

■ Contains six flip-flops with single-rail outputs

■ Buffered clock and direct clear inputs

■ Individual data input to each flip-flop

■ Applications include:

Buffer/storage registers Shift registers Pattern generators

■ Typical clock frequency 40 MHz

■ Typical power dissipation per flip-fl op 38 mW

Ordering Code:

Order Number Package Number Package Description

DM74174 N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram Function Table

(Each Flip-Flop)

Clear Clock D Q

LXXL H ↑ HH H ↑ LL HLXQ

H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care ↑ = Transition from LOW-to-HIGH level

= The level of Q before the indic at ed steady-state inp ut c onditions were

established.

Inputs Outputs

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Logic Diagram

DM74174

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Absolute Maximum Ratings(Note 1)

Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C

Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommend ed O peratin g Cond itions” t able w ill defin e the condit ions for actual device operation.

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units

V V V I I f t

CC IH

IL OH OL CLK W

Supply Voltage 4.75 5 5.25 V HIGH Level Input Voltage 2 V LOW Level Input Voltage 0.8 V HIGH Level Output Current −0.8 mA LOW Level Output Current 16 mA Clock Frequency (Note 2) 0 30 MHz Pulse Width Clock LOW 25 (Note 2) Clock HIGH 10 ns

Clear 20

REL

Note 2: TA = 25°C and VCC = 5V.

Data Setup Time (Note 2) 20 ns Data Hold Time (Note 2) 0 ns Clear Release Time (Note 2) 30 ns Free Air Operating Temperature 0 70 °C

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min

Note 3: All typicals are at VCC = 5V, TA = 25°C. Note 4: Not more than one output should be shorted at a time.

Note 5: With all output s o pen and all DATA and CLEAR inputs at 4.5V, I

Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min, VIL = Max Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA Short Circuit Output Current VCC = Max (Note 4) −18 −57 mA Supply Current VCC = Max (Note 5) 45 65 mA

is measured after a momentary ground, then 4.5V applied to the CLOCK input.

2.4 V

Typ

(Note 3)

Max Units

0.4 V

DM74174

Switching Characteristics

at VCC = 5V and TA = 25°C

Symbol Parameter

f t

MAX PLH

PHL

Maximum Clock Frequency 30 MHz Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output

From (Input) RL = 400Ω, CL = 15 pF

To (Output) Min Max

Clock to Any Q 25 ns

Clear to Any Q 40 ns

Units

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Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

DM74174 Hex/Quad D-Type Flip-Flop with Clear

Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the user.

2. A critical component in any compon ent of a lif e supp ort device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort device or system, or to affect its safety or effectiveness.

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