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PRELIMINARY DATA
November, 20 2002
DB-900-100W
100W / 26V / 869-894 MHz PA using 2x PD57060S
The
LdmoST
FAMILY
ORDER CODE
DB-900-100W
ABSOLUTE MAXIMUM RATINGS (T
CASE
= 25oC)
Symbol Parameter Value Unit
V
DD
Supply voltage 32 V
I
D
Drain Current 12
A
P
DISS
Power dissipation at Tcase = +85°C 145 W
T
CASE
Operating Case Temperature -20 to +85
o
C
P
amb
Max. Ambient Temperature +55
o
C
RF POWER AMPLIFIER DEMOBOARD USING
TWO N-CHANNEL ENHANCEMENT-MODE
LATERAL MOSFETs
• EXCEL L ENT THERMA L STABI LITY
• COMMON SOURCE CONFIGURATION
• P
OUT
= 100 W min. with 13 dB gain over
869-894 MHz
• 10:1 LOAD VSWR CAPABILITY
• BeO FREE AMPLIFIER
TYPICAL CDMA PERFORMANCE:
IS-95 CDMA / 9ch FWD
Pout = 20W
Gain = 13 dB
Nd = 22%
ACPR (750 KHz) : -45 dBc
ACPR (1.98 MHz) : -60 dBc
DESCRIPTION
The DB-900-100W is a com mon source N-Channel enhancement-mode lateral Field-Effect RF
power amplifier designed for IS-54/-136 & IS-95
base station applications.
The DB-900-100W is designed in cooperation
with Europeenne de Telecomunications S.A.
(www.etsa.rf), for high gain and broadband
performance operating in comm on source mode
at 26 V, capable of withstanding load mismatch
up to 10:1 all ph ases and with harmo nics lower
than 30 dBc.
MECH. SPECIFICATION L=80 mm W=50 mm H=10 mm
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DB-900-100W
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Symbol Test Conditions Min. Typ. Max. Unit
FREQ. Frequency Range 869 894 MHz
Gain P
OUT
= 100 W
12.5 13 dB
P
1dB
Over frequency range: 869 - 894 MHz 100 W
Flatness
Over frequency range and @ P
OUT
= 100 W
+/- 0.5 dB
Flatness
P
OUT
from 0.1W to 100 W
1dB
ND at P
1dB
P
1dB
40 45 %
IRTL
Input return Loss P
OUT
from 0.1W to 100 W
-20 -15 dB
Harmonic
P
OUT
= 100 W
-40 -30 dBc
VSWR
Load Mismatch all phases @ P
OUT
= 100 W
10:1
Spurious
10:1 VSWR all phases and P
OUT
from 0.1 to 100W
-76 dBc
IMD
3
P
OUT
= 100 WPEP
-25 dBc
ELECTRICAL SPECIFICATION (T
amb
= +25oC, Vdd = 26V, Idq = 2 x 200 mA)
TYPICAL CDMA PERFORMANCE IS 95 / 9ch FWD (Vdd = 26V, Idq = 350mA)
F requency
Pout
CH PWR
Pout
CH PWR
ACPR
-750 KHz
ACPR
+750 K Hz
ACPR
-1.98 MHz
ACPR
+1.98 M HzItotal
Nd
(M Hz) (W) (dBm) (dBc) (dBc) (dBc) (dBc) (A) (%)
865 10 40.0 53.4 50.8 67.0 67.0
880 10 40.0 54.2 51.7 68.6 68.3
895 10 40.0 53.2 51.7 69.0 69.0
865 20 43.0 45.0 45.0 64.0 64.0
880 20 43.0 45.1 45.4 64.7 64.7
895 20 43.0 45.2 45.7 66.8 66.5
2.5
3.5
15.4
22.0
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DB-900-100W
TYPICAL PERFORMANCE
Power Gain vs Output Power Power Gain vs Frequency
Efficiency vs Frequency
1 10 100 1000
Pout (W)
10
11
12
13
14
15
16
17
18
Gp (dB)
Vdd = 26 V
Idq = 2 x 200m A
865 MHz
880 MHz
895 MHz
860 865 870 875 880 885 890 895 900
f (MHz)
10
11
12
13
14
15
16
17
18
Gp (dB)
Vdd = 26 V
Idq = 2 x 200mA
Pout = 110W
Pout = 100W
Pout = 15W
860 865 870 875 880 885 890 895 900
f (MHz)
30
35
40
45
50
55
60
Nd (%)
Vdd = 26 V
Idq = 2 x 200m A
Pout = 110W
Pout = 100W
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TEST FIXTU R E CO M PONENT LAY O UT
TEST CIRCUIT PHOTOMASTER
Ref. ETSA c07/2000 - Ed1
CV1
CV2
Ref. ETSA c07/2000 - Ed1
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DB-900-100W
TEST CIRCUIT COMPONENT PART LIST
COMPONENT DESCRIPTION
T1, T2 PD57060S TRANSISTOR
C1, C2, C23, C24 47pF - 500V CERAMIC CHIP CAPACITOR
C3, C4, C12, C14 6.8pF - 500V CERAMIC CHIP CAPACITOR
C5, C6, C17, C18 100pF - 500V CERAMIC CHIP CAPACITOR
C7, C8, C9, C10, C11, C13 10pF - 500V CERAMIC CHIP CAPACITOR
C15, C16 100nF - 63V CERAMIC CHIP CAPACITOR
C19, C20 1µF / 35V ELECTROLYTIC CAPACITOR
C26, C27 3.3pF - 500V CERAMIC CHIP CAPACITOR
C21, C22 4.7pF - 500V CERAMIC CHIP CAPACITOR
C25 0.5pF - 500V CERAMIC CHIP CAPACITOR
CV1, CV2 ADJUSTABLE CAPACITOR 0.6 - 4.5pF / 500V
P1, P2 10K Ohms MULTITURN POTENTIOMETER
R1,R7 100 Ohms 1/4W 1206 SMD CHIP RESISTOR
R2 50 Ohms 30W - 4GHz LOAD
R3, R4 4.7K Ohms 1/4W 1206 SMD CHIP RESISTOR
R5, R6 10K Ohms 1/4W 1206 SMD CHIP RESISTOR
D1, D2 ZENER DIODE 5V - 500 mW SOD80
SM1, SM2 90° SMD HYBRID COUPLER ANAREN Xinger 1304-3
BOARD METCLAD MX3-30-C1/10C THK 0.762 mm Cu 35µ
SUBSTRATE TEFLON-GLASS Er = 2.55
BACK SIDE COPPER FLANGE 2 mm THICKNESS
CERAMIC CHIP CAPACITORS ATC100B or EQUIVALENT
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