Page 1
®
Current
Sources
LSB
Switches
Segmented
Switches
+1.24V Ref.
Latches
10-Bit Data Input
D9...D0
DAC900
FSA
BW
+V
D
+V
A
AGND CLK DGND
REF
IN
INT/EXT
I
OUT
I
OUT
BYP
PD
For most current data sheet and other product
information, visit www.burr-brown.com
DAC900
DAC900
DAC900
DIGITAL-TO-ANALOG CONVERTER
FEATURES
● SINGLE +5V OR +3V OPERATION
●
HIGH SFDR: 5MHz Output at 100MSPS: 68dBc
● LOW GLITCH: 3pV-s
● LOW POWER: 170mW at +5V
● INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
DESCRIPTION
The DAC900 is a high-speed, digital-to-analog converter (DAC)
offering a 10-bit resolution option within the SpeedPlus family
of high-performance converters. Featuring pin compatibility
among family members, the DAC908, DAC902, and DAC904
provide a component selection option to an 8-, 12-, and 14-bit
resolution, respectively. All models within this family of D/A
converters support update rates in excess of 165MSPS with
excellent dynamic performance, and are especially suited to
fulfill the demands of a variety of applications.
The advanced segmentation architecture of the DAC900 is
optimized to provide a high Spurious-Free Dynamic Range
(SFDR) for single-tone, as well as for multi-tone signals—
essential when used for the transmit signal path of communication systems.
The DAC900 has a high impedance (200kΩ) current output with
a nominal range of 20mA and an output compliance of up to
1.25V. The differential outputs allow for both a differential, or
single-ended analog signal interface. The close matching of the
current outputs ensures superior dynamic performance in the
differential configuration, which can be implemented with a
transformer.
Utilizing a small geometry CMOS process, the monolithic
DAC900 can be operated on a wide, single-supply range of
+2.7V to +5.5V. Its low power consumption allows for use in
portable and battery operated systems. Further optimization can
be realized by lowering the output current with the adjustable
full-scale option.
©
1999 Burr-Brown Corporation PDS-1446B Printed in U.S.A. May, 2000
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
10-Bit, 165MSPS
TM
APPLICATIONS
● COMMUNICATION TRANSMIT CHANNELS
WLL, Cellular Base Station
Digital Microwave Links
Cable Modems
● WAVEFORM GENERATION
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
● MEDICAL/ULTRASOUND
● HIGH-SPEED INSTRUMENTATION AND
CONTROL
● VIDEO, DIGITAL TV
For noncontinuous operation of the DAC900, a power-down
mode results in only 45mW of standby power.
The DAC900 comes with an integrated 1.24V bandgap reference and edge-triggered input latches, offering a complete
converter solution. Both +3V and +5V CMOS logic families
can be interfaced to the DAC900.
The reference structure of the DAC900 allows for additional
flexibility by utilizing the on-chip reference, or applying an
external reference. The full-scale output current can be adjusted
over a span of 2mA to 20mA, with one external resistor, while
maintaining the specified dynamic performance.
The DAC900 is available in SO-28 and TSSOP-28 packages.
1
®
DAC900
Page 2
SPECIFICATIONS
At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC900U/E
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution 10 Bits
Output Update Rate (f
Output Update Rate 2.7V to 3.3V 125 165 MSPS
Full Specified Temperature Range, Operating Ambient, T
STATIC ACCURACY
Differential Nonlinearity (DNL) f
Integral Nonlinearity (INL) –1.0 ±0.5 +1.0 LSB
DYNAMIC PERFORMANCE TA = +25°C
Spurious Free Dynamic Range (SFDR) To Nyquist
= 1.0MHz, f
f
OUT
= 2.1MHz, f
f
OUT
= 5.04MHz, f
f
OUT
= 5.04MHz, f
f
OUT
= 20.2MHz, f
f
OUT
= 25.3MHz, f
f
OUT
= 41.5MHz, f
f
OUT
= 27.4MHz, f
f
OUT
= 54.8MHz, f
f
OUT
Spurious Free Dynamic Range within a Window
= 5.04MHz, f
f
OUT
= 5.04MHz, f
f
OUT
Total Harmonic Distortion (THD)
= 2.1MHz, f
f
OUT
= 2.1MHz, f
f
OUT
Two Tone
f
= 13.5MHz, f
OUT1
Output Settling Time
Output Rise Time
Output Fall Time
(2)
(2)
Glitch Impulse 3 pV-s
DC-ACCURACY
Full-Scale Output Range
Output Compliance Range –1.0 +1.25 V
Gain Error With Internal Reference –10 ±1 +10 %FSR
Gain Error With External Reference –10 ±2 +10 %FSR
Gain Drift With Internal Reference ±120 ppmFSR/°C
Offset Error With Internal Reference –0.025 +0.025 %FSR
Offset Drift With Internal Reference ±0.1 ppmFSR/°C
Power Supply Rejection, +V
Power Supply Rejection, +V
Output Noise I
Output Resistance 200 kΩ
Output Capacitance I
REFERENCE
Reference Voltage +1.24 V
Reference Tolerance ±10 %
Reference Voltage Drift ±50 ppmFSR/°C
Reference Output Current 10 µA
Reference Input Resistance 1MΩ
Reference Input Compliance Range 0.1 1.25 V
Reference Small Signal Bandwidth
DIGITAL INPUTS
Logic Coding Straight Binary
Latch Command Rising Edge of Clock
Logic High Voltage, V
Logic Low Voltage, V
Logic High Voltage, V
Logic Low Voltage, V
Logic High Current
Logic Low Current, I
Input Capacitance 5pF
) 4.5V to 5.5V 165 200 MSPS
CLOCK
(1)
CLOCK
= 25MSPS 70 76 dBc
CLOCK
= 50MSPS 75 dBc
CLOCK
= 50MSPS 68 dBc
CLOCK
= 100MSPS 68 dBc
CLOCK
= 100MSPS 62 dBc
CLOCK
= 125MSPS 62 dBc
CLOCK
= 125MSPS 53 dBc
CLOCK
= 165MSPS 59 dBc
CLOCK
= 165MSPS 53 dBc
CLOCK
= 50MSPS 2MHz Span 78 dBc
CLOCK
= 100MSPS 4MHz Span 78 dBc
CLOCK
= 50MSPS –74 dBc
CLOCK
= 125MSPS –73 dBc
CLOCK
= 14.5MHz, f
OUT2
(2)
= 100MSPS
CLOCK
TA = +25°C
= 25MSPS, f
A
= 1.0MHz –0.5 ±0.3 +0.5 LSB
OUT
to 0.1% 30 ns
–40 +85 °C
60 dBc
10% to 90% 2 ns
10% to 90% 2 ns
(3)
(FSR) All Bits High, I
A
D
(4)
IH
IL
IH
IL
,
(5)
I
IH
IL
OUT
OUT
= 20mA, R
, I
OUT
OUT
= 50Ω 50 pA/√Hz
LOAD
to Ground 12 pF
+VD = +5V 3.5 5 V
+VD = +5V 0 1.2 V
+VD = +3V 2 3 V
+VD = +3V 0 0.8 V
+VD = +5V ±20 µA
+VD = +5V ±20 µA
2.0 20.0 mA
–0.2 +0.2 %FSR/V
–0.025 +0.025 %FSR/V
1.3 MHz
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC900
2
Page 3
SPECIFICATIONS (Cont.)
At TA = +25°C, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC900U/E
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Supply Voltages
+V
A
+V
D
Supply Current
I
VA
, Power-Down Mode 1.1 2 mA
I
VA
I
VD
Power Dissipation +5V, I
Power Dissipation, Power-Down Mode 45 mW
Thermal Resistance,
SO-28 75 °C/W
TSSOP-28 50 °C/W
NOTES: (1) At output I
Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an
internal pull-down resistor. (6) Measured at f
(6)
= 20mA 170 230 mW
OUT
+3V, I
θ
JA
, while driving a virtual ground. (2) Measured single-ended into 50Ω Load. (3) Nominal full-scale output current is 32x I
OUT
= 50MSPS and f
CLOCK
OUT
= 2mA 50 mW
OUT
= 1.0MHz.
+2.7 +5 +5.5 V
+2.7 +5 +5.5 V
24 30 mA
815mA
; see Application
REF
ABSOLUTE MAXIMUM RATINGS
+VA to AGND ........................................................................ –0.3V to +6V
+VD
to DGND........................................................................ –0.3V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
+VA to +VD .............................................................................. –6V to +6V
CLK, PD to DGND ...................................................... –0.3V to VD + 0.3V
D0-D9 to DGND .......................................................... –0.3V to VD + 0.3V
, I
to AGND............................................................–1V to VA + 0.3V
I
OUT
OUT
BW, BYP to AGND.......................................................–0.3V to VA + 0.3V
REFIN, FSA to AGND.................................................. –0.3V to VA + 0.3V
INT/EXT to AGND........................................................ –0.3V to VA + 0.3V
Junction Temperature .................................................................... +150°C
Case Temperature ......................................................................... +100°C
Storage Temperature..................................................................... +125°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
ELECTROSTATIC
DISCHARGE SENSITIVITY
PACKAGE/ORDERING INFORMATION
PACKAGE SPECIFIED
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
DAC900U SO-28 217 –40°C to +85°C DAC900U DAC900U Rails
"""""DAC900U/1K Tape and Reel
DAC900E TSSOP-28 360 –40°C to +85°C DAC900E DAC900E Rails
"""""DAC900E/2K5 Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “DAC900E/2K5” will get a single 2500-piece Tape and Reel.
(1)
MEDIA
DEMO BOARD ORDERING INFORMATION
PRODUCT ORDERING NUMBER COMMENT
DAC900U DEM-DAC90xU Populated evaluation board without D/A converter. Order sample of desired DAC90x model separately.
DAC900E DEM-DAC900E Populated evaluation board including the DAC900E.
DEMO BOARD
3
DAC900
®
Page 4
Top View SO/TSSOP
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
NC
NC
NC
NC
1
2
3
4
5
6
7
DAC900
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK
+V
D
DGND
NC
+V
A
BYP
I
OUT
I
OUT
AGND
BW
FSA
REF
IN
INT/EXT
PD
PIN DESCRIPTIONSPIN CONFIGURATION
PIN DESIGNATOR DESCRIPTION
1 Bit 1 Data Bit 1 (D9), MSB
2 Bit 2 Data Bit 2 (D8)
3 Bit 3 Data Bit 3 (D7)
4 Bit 4 Data Bit 4 (D6)
5 Bit 5 Data Bit 5 (D5)
6 Bit 6 Data Bit 6 (D4)
7 Bit 7 Data Bit 7 (D3)
8 Bit 8 Data Bit 8 (D2)
9 Bit 9 Data Bit 9 (D1)
10 Bit 10 Data Bit 10 (D0), LSB
11 NC No Connection
12 NC No Connection
13 NC No Connection
14 NC No Connection
15 PD Power Down, Control Input; Active
16 INT/EXT Reference Select Pin; Internal ( = 0) or
17 REF
IN
18 FSA Full-Scale Output Adjust
19 BW Bandwidth/Noise Reduction Pin:
20 AGND Analog Ground
21 I
22 I
23 BYP Bypass Node: Use 0.1µF to AGND
24 +V
25 NC No Connection
OUT
OUT
A
26 DGND Digital Ground
27 +V
28 CLK Clock Input
D
High.
Contains internal pull-down circuit;
may be left unconnected if not used.
External ( = 1) Reference Operation.
Reference Input/Ouput. See Applications
section for further details.
Bypass with 0.1µF to +V
Performance.
for Optimum
A
Complementary DAC Current Output
DAC Current Output
Analog Supply Voltage, 2.7V to 5.5V
Digital Supply Voltage, 2.7V to 5.5V
TYPICAL CONNECTION CIRCUIT
+5V +5V
0.1µF
+V
A
DAC900
FSA
REF
IN
R
SET
0.1µF
INT/EXT
+1.24V Ref.
AGND CLK DGND
BW
Current
Sources
+V
D
Switches
Segmented
Switches
Latches
10-Bit Data Input
D9.......D0
LSB
MSB
I
OUT
I
OUT
BYP
PD
0.1µF
50Ω
20pF
50Ω
1:1
20pF
®
DAC900
4
Page 5
TIMING DIAGRAM
CLK
D9 - D0
I
OUT
t
1
t
t
S
H
t
PD
t
2
t
SET
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
t
2
t
S
t
H
t
PD
t
SET
Clock Pulse High Time 6.25 ns
Clock Pulse Low Time 6.25 ns
Data Setup Time 2 ns
Data Hold Time 2 ns
Propagation Delay Time (t1+t2)+1 ns
Output Settling Time to 0.1% 25 ns
®
5
DAC900
Page 6
TYPICAL PERFORMANCE CURVES, VD = VA = +5V
At TA = +25°C, Differential I
1.00
0.75
0.50
0.25
0
–0.25
Error (LSBs)
–0.50
–0.75
–1.00
0
100
200
90
85
= 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
OUT
TYPICAL DNL
300
400
SFDR vs f
500
DAC Code
AT 25MSPS
OUT
600
700
800
900
1000
1024
1.00
0.75
0.50
0.25
0
–0.25
Error (LSBs)
–0.50
–0.75
–1.00
85
80
0
100
200
TYPICAL INL
300
400
SFDR vs f
500
DAC Code
AT 50MSPS
OUT
600
700
800
900
1000
1024
80
75
SFDR (dBc)
70
65
60
85
80
75
70
65
60
SFDR (dBc)
55
50
45
2.0 4.0 6.0 8.0 10.0 12.00
0dBFS
10.0 20.0 30.0 40.0 50.00
–6dBFS
Frequency (MHz)
SFDR vs f
Frequency (MHz)
AT 100MSPS
OUT
–6dBFS
0dBFS
75
70
SFDR (dBc)
65
60
55
85
80
75
70
65
60
SFDR (dBc)
55
50
45
–6dBFS
0dBFS
5.0 10.0 15.0 20.0 25.00
Frequency (MHz)
SFDR vs f
10.0 20.0 30.0 50.040.0 60.00
AT 125MSPS
OUT
–6dBFS
0dBFS
Frequency (MHz)
®
DAC900
6
Page 7
TYPICAL PERFORMANCE CURVES, VD = VA = +5V (Cont.)
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
Temperature (°C)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
–20 0 25 7050 85–40
2.1MHz
10.1MHz
40.4MHz
X
X
X
X
X
X
X
SFDR vs I
OUTFS
and f
OUT
AT 100MSPS, 0dBFS
I
OUTFS
(mA)
SFDR (dBc)
80
75
70
65
60
55
50
45
40
510202
X
X
X
X
2.1MHz
10.1MHz
5.04MHz
40.4MHz
*
*
*
*
SFDR vs f
OUT
AT 200MSPS
Frequency (MHz)
SFDR (dBc)
80
75
70
65
60
55
50
45
40
20.010.0 30.0 40.0 50.0 70.060.0 90.080.00
–6dBFS
0dBFS
At TA = +25°C, Differential I
80
75
70
65
60
55
SFDR (dBc)
50
45
40
20.010.0 30.0 40.0 50.0 70.060.0 80.00
DIFFERENTIAL vs SINGLE-ENDED SFDR vs f
85
80
X
75
70
65
60
SFDR (dBc)
X
I
OUT
X
55
50
45
10.0 20.0 30.0 40.0 50.00
= 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
OUT
SFDR vs f
AT 165MSPS
OUT
–6dBFS
0dBFS
Frequency (MHz)
AT 100MSPS
OUT
(–6dBFS)
Diff (–6dBFS)
X
X
X
I
OUT
(0dBFS)
X
Diff (0dBFS)
Frequency (MHz)
THD vs f
–70
CLOCK
–75
–80
–85
THD (dBc)
–90
–95
–100
25 50 100 125 1500
f
CLOCK
AT f
OUT
(MSPS)
= 2.1MHz
2HD
3HD
®
7
DAC900
Page 8
TYPICAL PERFORMANCE CURVES, VD = VA = +5V (Cont.)
At TA = +25°C, Differential I
DUAL-TONE OUTPUT SPECTRUM
0
–10
–20
–30
–40
–50
–60
–70
Magnitude (dBm)
–80
–90
–100
0
5 101520253035404550
= 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
OUT
0
–10
f
= 100MSPS
CLOCK
= 13.5MHz
f
OUT1
= 14.5MHz
f
OUT2
SFDR = 60dBc
Amplitude = 0dBFS
–20
–30
–40
–50
–60
–70
Magnitude (dBm)
–80
–90
–100
0
510152025
Frequency (MHz)
FOUR-TONE OUTPUT SPECTRUM
f
= 50MSPS
CLOCK
= 6.25MHz
f
OUT1
= 6.75MHz
f
OUT2
f
= 7.25MHz
OUT3
= 7.75MHz
f
OUT4
SFDR = 66dBc
Amplitude = 0dBFS
Frequency (MHz)
®
DAC900
8
Page 9
TYPICAL PERFORMANCE CURVES, VD = VA = +3V
DIFFERENTIAL vs SINGLE-ENDED SFDR vs f
OUT
AT 100MSPS (3V)
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
10.0 20.0 30.0 40.0 50.00
Diff (0dBFS)
I
OUT
(–6dBFS)
I
OUT
(0dBFS)
Diff (–6dBFS)
X
X
X
X
X
X
X
SFDR vs f
OUT
AT 125MSPS (3V)
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
10.0 20.0 30.0 50.040.0 60.00
0dBFS
–6dBFS
SFDR vs f
OUT
AT 50MSPS (3V)
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
5.0 10.0 15.0 20.0 25.00
–6dBFS
0dBFS
At TA = +25°C, Differential I
85
80
75
70
SFDR (dBc)
65
0dBFS
60
55
2.0 4.0 6.0 8.0 10.0 12.00
85
80
75
70
65
60
SFDR (dBc)
55
50
45
10.0 20.0 30.0 40.0 50.00
= 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
OUT
SFDR vs f
AT 25MSPS (3V)
OUT
–6dBFS
Frequency (MHz)
SFDR vs f
AT 100MSPS (3V)
OUT
–6dBFS
0dBFS
Frequency (MHz)
80
SFDR vs f
75
70
65
60
55
SFDR (dBc)
50
45
40
20.010.0 30.0 40.0 50.0 70.060.0 80.00
Frequency (MHz)
AT 165MSPS (3V)
OUT
–6dBFS
0dBFS
®
9
DAC900
Page 10
TYPICAL PERFORMANCE CURVES, VD = VA = +3V (Cont.)
At TA = +25°C, Differential I
SFDR vs I
80
75
70
X
65
60
55
SFDR (dBc)
*
50
45
40
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS (3V)
80
75
70
65
60
55
SFDR (dBc)
50
45
X
X
40
–20 0 25 7050 85–40
= 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
OUT
and f
OUTFS
X
AT 100MSPS (3V)
OUT
10.1MHz
2.1MHz
5.04MHz
X
X
–70
–75
–80
THD vs f
–85
THD (dBc)
*
40.4MHz
*
*
–90
–95
–100
510202
I
(mA)
OUTFS
25 50 100 125 1500
0
2.1MHz
–10
–20
10.1MHz
–30
–40
–50
–60
40.4MHz
X
X
X
X
X
–70
Magnitude (dBm)
–80
–90
–100
0
5 101520253035404550
Temperature (°C)
AT f
CLOCK
= 2.1MHz (3V)
OUT
2HD
3HD
f
(MSPS)
CLOCK
DUAL-TONE OUTPUT SPECTRUM
f
= 100MSPS
CLOCK
= 13.5MHz
f
OUT1
= 14.5MHz
f
OUT2
SFDR = 61.5dBc
Amplitude = 0dBFS
Frequency (MHz)
®
DAC900
0
–10
–20
–30
–40
–50
–60
–70
Magnitude (dBm)
–80
–90
–100
0
FOUR-TONE OUTPUT SPECTRUM
f
= 50MSPS
CLOCK
= 6.25MHz
f
OUT1
= 6.75MHz
f
OUT2
f
= 7.25MHz
OUT3
= 7.75MHz
f
OUT4
SFDR = 62.5dBc
Amplitude = 0dBFS
510152025
Frequency (MHz)
10
Page 11
APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC900 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic D/A converter is an
array of segmented current sources, which are designed to
deliver a full-scale output current of up to 20mA (see
Figure 1). An internal decoder addresses the differential
current switches each time the DAC is updated and a
corresponding output current is formed by steering all
currents to either output summing node, I
The complementary outputs deliver a differential output
signal, which improves the dynamic performance through
reduction of even-order harmonics, common-mode signals
(noise), and double the peak-to-peak output signal swing by
a factor of two, compared to single-ended operation.
The segmented architecture results in a significant reduction of the glitch energy, and improves the dynamic performance (SFDR) and DNL. The current outputs maintain a
very high output impedance of greater than 200kΩ.
The full-scale output current is determined by the ratio of
the internal reference voltage (1.24V) and an external
resistor, R
. The resulting I
SET
is internally multiplied by
REF
a factor of 32 to produce an effective DAC output current
that can range from 2mA to 20mA, depending on the value
of R
SET
.
The DAC900 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section comprises the current source array with its associated switches and the
reference circuitry.
OUT
or I
OUT
DAC TRANSFER FUNCTION
The total output current, I
, of the DAC900 is the
OUTFS
summation of the two complementary output currents:
I
OUTFS
= I
OUT
+ I
OUT
The individual output currents depend on the DAC code and
can be expressed as:
I
= I
I
OUT
OUT
= I
OUTFS
.
• (Code/1024) (2)
OUTFS
• (1023 - Code/1024) (3)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, I
ence current I
, which is determined by the reference
REF
voltage and the external setting resistor, R
I
= 32 • I
OUTFS
is a function of the refer-
OUTFS
SET
= 32 • V
REF
REF/RSET
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
V
= I
= I
OUT
OUT
• R
• R
LOAD
LOAD
OUT
V
OUT
(1)
.
(4)
(5)
(6)
+3V to +5V
Digital
Bandwidth
Control
BW
Clock
Input
+V
PMOS
Current
Source
400pF
Array
Latches and Switch
NOTE: Supply bypassing not shown.
Full-Scale
Adjust
Resistor
R
SET
2kΩ
Ref
Input
0.1µF
DAC900
FSA
REF
IN
INT/EXT
+1.24V Ref
AGND
+3V to +5V
Analog
+V
A
Ref
Buffer
Analog
Ground
0.1µF
Ref
Control
Amp
CLK
FIGURE 1. Functional Block Diagram of the DAC900.
D
Switches
Segmented
MSB
Switches
Decoder Logic
10-Bit Data Input
D9...D0
11
LSB
I
OUT
I
OUT
BYP
PD
DGND
Digital
Ground
50Ω
0.1µF
Power Down
(internal pull-down)
20pF
DAC900
50Ω
20pF
1:1
V
OUT
®
Page 12
The value of the load resistance is limited by the output
compliance specification of the DAC900. To maintain specified linearity performance, the voltage for I
OUT
and I
OUT
should not exceed the maximum allowable compliance range.
The two single-ended output voltages can be combined to
find the total differential output swing:
Code
•
V V V
= =
OUTDIFF OUT
( – )2 1023
OUT
1024
I R
• •–
OUTFS LOAD
(7)
ANALOG OUTPUTS
The DAC900 provides two complementary current outputs,
I
OUT
and I
. The simplified circuit of the analog output
OUT
stage representing the differential topology is shown in
Figure 2. The output impedance of 200kΩ || 12pF for I
and I
results from the parallel combination of the differ-
OUT
OUT
ential switches, along with the current sources and associated parasitic capacitances.
+V
A
DAC900
OUT
R
I
OUT
R
L
L
I
FIGURE 2. Equivalent Analog Output.
I
OUT
and I
. Furthermore, using the differential output
OUT
configuration in combination with a transformer will be
instrumental for achieving excellent distortion performance.
Common-mode errors, such as even-order harmonics or
noise, can be substantially reduced. This is particularly the
case with high output frequencies and/or output amplitudes
below full-scale.
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a reduced performance level.
INPUT CODE (D9 - D0) I
11 1111 1111 20mA 0mA
10 0000 0000 10mA 10mA
00 0000 0000 0mA 20mA
OUT
I
OUT
Table I. Input Coding vs Analog Output Current.
OUTPUT CONFIGURATIONS
The current output of the DAC900 allows for a variety of
configurations, some of which are illustrated below. As
mentioned previously, utilizing the converter’s differential
outputs will yield the best dynamic performance. Such a
differential output circuit may consist of an RF transformer
(see Figure 3) or a differential amplifier configuration (see
Figure 4). The transformer configuration is ideal for most
applications with ac coupling, while op amps will be suitable
for a dc-coupled configuration.
The single-ended configuration (see Figure 6) may be considered for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs to
ground will convert the output current into a ground-referenced voltage signal. To improve on the dc linearity an I to
V converter can be used instead. This will result in a
negative signal excursion and, therefore, requires a dual
supply amplifier.
The signal voltage swing that may develop at the two
outputs, I
OUT
and I
, is limited by a negative and positive
OUT
compliance. The negative limit of –1V is given by the
breakdown voltage of the CMOS process, and exceeding it
will compromise the reliability of the DAC900, or even
cause permanent damage. With the full-scale output set to
20mA, the positive compliance equals 1.25V, operating with
+VD = 5V. Note that the compliance range decreases to
about 1V for a selected output current of I
OUTFS
= 2mA.
Care should be taken that the configuration of DAC900 does
not exceed the compliance range to avoid degradation of the
distortion performance and integral linearity.
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5V. This is the case for a 50Ω doubly terminated load and
a 20mA full-scale output current. A variety of loads can be
adapted to the output of the DAC900 by selecting a suitable
transformer while maintaining optimum voltage levels at
®
DAC900
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of
converting the differential output signal into a single-ended
signal while achieving excellent dynamic performance (see
Figure 3). The appropriate transformer should be carefully
selected based on the output frequency spectrum and impedance requirements. The differential transformer configuration has the benefit of significantly reducing common-mode
signals, thus improving the dynamic performance over a
wide range of frequencies. Furthermore, by selecting a
suitable impedance ratio (winding ratio), the transformer can
be used to provide optimum impedance matching while
controlling the compliance voltage for the converter outputs.
The model shown, ADT1-1WT (by Mini-Circuits), has a 1:1
ratio and may be used to interface the DAC900 to a 50Ω
load. This results in a 25Ω load for each of the outputs, I
and I
. The output signals are ac coupled and inherently
OUT
isolated because of the transformer's magnetic coupling .
12
OUT
Page 13
As shown in Figure 3, the transformer’s center tap is connected to ground. This forces the voltage swing on I
I
to be centered at 0V. In this case the two resistors, RS,
OUT
may be replaced with one, R
, or omitted altogether. This
DIFF
OUT
and
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be observed. Alternatively, if the center tap is not connected, the
signal swing will be centered at RS • I
/2. However, in
OUTFS
this case, the two resistors, RS, must be used to enable the
necessary dc-current flow for both outputs.
ADT1-1WT
(Mini-Circuits)
1:1
R
L
DAC900
I
I
OUT
OUT
Optional
R
DIFF
R
S
50Ω
R
50Ω
S
The OPA680 is configured for a gain of two. Therefore,
operating the DAC900 with a 20mA full-scale output will
produce a voltage output of ±1V. This requires the amplifier
to operate off of a dual power supply (±5V). The tolerance
of the resistors typically sets the limit for the achievable
common-mode rejection. An improvement can be obtained
by fine tuning resistor R4.
This configuration typically delivers a lower level of ac
performance than the previously discussed transformer solution because the amplifier introduces another source of
distortion. Suitable amplifiers should be selected based on
their slew-rate, harmonic distortion, and output swing capabilities. High-speed amplifiers like the OPA680 or OPA687
may be considered. The ac performance of this circuit may
be improved by adding a small capacitor, C
outputs I
OUT
and I
,
as shown in Figure 4
OUT
, between the
DIFF
. This will introduce a real pole to create a low-pass filter in order to slewlimit the DACs fast output signal steps, which otherwise
could drive the amplifier into slew-limitations or into an
overload condition; both would cause excessive distortion.
The difference amplifier can easily be modified to add a
level shift for applications requiring the single-ended output
voltage to be unipolar, i.e., swing between 0V and +2V.
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a dc-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feedback op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC900 generates a differential output
signal of 0.5Vp-p at the load resistors, RL. The resistor
values shown were selected to result in a symmetric 25Ω
loading for each of the current outputs since the input
impedance of the difference amplifier is in parallel to resistors RL, and should be considered.
R
2
402Ω
R
1
200Ω
200Ω
R
L
28.7Ω
OPA680
R
3
+5V
–5V
R
4
402Ω
V
OUT
DAC900
I
OUT
I
OUT
C
DIFF
R
L
26.1Ω
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
The circuit example of Figure 5 shows the signal output
currents connected into the summing junction of the
OPA2680, which is set up as a transimpedance stage, or
‘I to V converter’. With this circuit, the DAC’s output will
be kept at a virtual ground, minimizing the effects of output
impedance variations, and resulting in the best dc linearity
(INL). However, as mentioned previously, the amplifier
may be driven into slew-rate limitations, and produce unwanted distortion. This may occur, especially, at high DAC
update rates.
+5V
50Ω
DAC900
I
OUT
I
OUT
1/2
OPA2680
R
F1
C
C
D1
C
D2
F1
R
F2
C
F2
1/2
OPA2680
–V
–V
OUT
OUT
= I
• R
OUT
F
= I
• R
OUT
F
FIGURE 4. Difference Amplifier Provides Differential to
Single-Ended Conversion and DC-Coupling.
50Ω
–5V
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680
Forms Differential Transimpedance Amplifier.
13
DAC900
®
Page 14
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
CF is added across RF to compensate for this noise gain
peaking. To achieve a flat transimpedance frequency response, the pole in each feedback network should be set to:
1
2 4π πR C
F F F D
GBP
=
R C
(8)
with GBP = Gain Bandwidth Product of OPA
which will give a corner frequency f
f
dB
−=3
2π
GBP
R C
of approximately:
-3dB
F D
(9)
The full-scale output voltage is defined by the product of
I
• RF, and has a negative unipolar excursion. To
OUTFS
improve on the ac performance of this circuit, adjustment of
RF and/or I
should be considered. Further extensions of
OUTFS
this application example may include adding a differential
filter at the OPA2680’s output followed by a transformer, in
order to convert to a single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be accomplished. The circuit in Figure 6 shows a 50Ω resistor
connected to I
, providing the termination of the further
OUT
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0 to 0.5V into the 25Ω load.
INTERNAL REFERENCE OPERATION
The DAC900 has an on-chip reference circuit which comprises a 1.24V bandgap reference and a control amplifier.
Grounding of pin 16, INT/EXT, enables the internal reference operation. The full-scale output current, I
DAC900 is determined by the reference voltage, V
the value of resistor R
I
= 32 • I
OUTFS
As shown in Figure 7, the external resistor R
SET
. I
OUTFS
= 32 • V
REF
can be calculated by:
/ R
REF
SET
, of the
OUTFS
REF
SET
connects to
, and
(10)
the FSA pin (Full-Scale Adjust). The reference control
amplifier operates as a V to I converter producing a reference current, I
and R
I
OUTFS
(see Equation 10). The full-scale output current,
SET
, results from multiplying I
V
=
I
REF
R
R
SET
2kΩ
, which is determined by the ratio of V
REF
by a fixed factor of 32.
REF
C
COMPEXT
BW
C
400pF
COMP
REF
SET
0.1µF
DAC900
FSA
REF
IN
INT/EXT
+1.24V Ref.
Ref
Control
Amp
0.1µF
+5V
+V
Current
Sources
REF
A
FIGURE 7. Internal Reference Configuration.
I
= 20mA
DAC900
I
I
OUT
OUT
OUTFS
50Ω
25Ω
V
= 0V to +0.5V
OUT
50Ω
FIGURE 6. Driving a Doubly Terminated 50Ω Cable Directly.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, I
, and the load resistor, may be mutu-
OUTFS
ally adjusted to provide the desired output signal swing and
performance.
®
DAC900
Using the internal reference, a 2kΩ resistor value results in
a 20mA full-scale output. Resistors with a tolerance of 1%
or better should be considered. Selecting higher values, the
converter output can be adjusted from 20mA down to 2mA.
Operating the DAC900 at lower than 20mA output currents
may be desirable for reasons of reducing the total power
consumption, improving the distortion performance, or observing the output compliance voltage limitations for a given
load condition.
It is recommended to bypass the REFIN pin with a ceramic chip
capacitor of 0.1µF or more. The control amplifier is internally
compensated, and its small signal bandwidth is approximately
1.3MHz. To improve the ac performance, an additional capacitor (C
COMPEXT
) should be applied between the BW pin and the
analog supply, +VA, as shown in Figure 7. Using a 0.1µF
capacitor, the small-signal bandwidth and output impedance of
the control amplifier is further diminished, reducing the noise
that is fed into the current source array. This also helps
shunting feedthrough signals more effectively, and improving
the noise performance of the DAC900.
14
Page 15
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by applying a logic
High (+VA) to pin INT/EXT. An external reference voltage
can then be driven into the REFIN pin, which in this case
functions as an input, as shown in Figure 8. The use of an
external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
While a 0.1µF capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1MΩ) and can easily be driven by various
sources. Note that the voltage range of the external reference
should stay within the compliance range of the reference
input (0.1V to 1.25V).
DIGITAL INPUTS
The digital inputs, D0 (LSB) through D9 (MSB) of the
DAC900 accept standard positive binary coding. The digital
input word is latched into a master-slave latch with the rising
edge of the clock. The DAC output becomes updated with
the following rising clock edge (refer to the specification
table and timing diagram for details). The best performance
will be achieved with a 50% clock duty cycle, however, the
duty cycle may vary as long as the timing specifications are
met. Additionally, the setup and hold times may be chosen
within their specified limits.
All digital inputs are CMOS compatible. The logic thresholds depend on the applied digital supply voltage such that
they are set to approximately half the supply voltage;
Vth = +VD/2 (±20% tolerance). The DAC900 is designed to
operate over a supply range of 2.7V to 5.5V.
POWER-DOWN MODE
The DAC900 features a power-down function which can be
used to reduce the supply current to less than 9mA over the
specified supply range of 2.7V to 5.5V. Applying a logic
High to the PD pin will initiate the power-down mode, while
a logic Low enables normal operation. When left unconnected, an internal active pull-down circuit will enable the
normal operation of the converter.
GROUNDING, DECOUPLING AND
LAYOUT INFORMATION
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer pc-boards are recommended
for best performance since they offer distinct advantages
such as minimization of ground impedance, separation of
signal layers by ground layers, etc.
The DAC900 uses separate pins for its analog and digital
supply and ground connections. The placement of the decoupling capacitor should be such that the analog supply (+VA)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most
cases 0.1uF ceramic chip capacitors at each supply pin are
adequate to provide a low impedance decoupling path. Keep
in mind that their effectiveness largely depends on the
proximity to the individual supply and ground pins. Therefore they should be located as close as physically possible to
those device leads. Whenever possible, the capacitors should
be located immediately under each pair of supply/ground
pins on the reverse side of the pc board. This layout approach will minimize the parasitic inductance of component
leads and pcb runs.
I
=
REF
External
Reference
R
SET
FIGURE 8. External Reference Configuration.
V
R
+5V
REF
SET
DAC900
FSA
REF
IN
INT/EXT
+1.24V Ref.
15
Ref
Control
Amp
C
BW
C
400pF
COMPEXT
0.1µF
COMP
+5V
+V
Current
Sources
A
®
DAC900
Page 16
Further supply decoupling with surface mount tantalum
capacitors (1uF to 4.7uF) may be added as needed in
proximity of the converter.
Low noise is required for all supply and ground connections
to the DAC900. It is recommended to use a multilayer pcboard utilizing separate power and ground planes. Mixed
signal designs require particular attention to the routing of
the different supply currents and signal traces. Generally,
analog supply and ground planes should only extend into
analog signal areas, such as the DAC output signal and the
reference signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the D/A converter.
This can be realized with a short track of approximately
1/8inch (3mm).
The power to the DAC900 should be provided through the
use of wide pcb runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decoupling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low noise analog supply voltage, which can then
be connected to the +VA supply pin of the DAC900.
While designing the layout, it is important to keep the analog
signal traces separated from any digital line, in order to
prevent noise coupling onto the analog signal path.
®
DAC900
16
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