Datasheet DAC8412 Datasheet (ANALOG DEVICES)

Quad, 12-Bit DAC

A

V

VDDV

FEATURES

+5 V to ±15 V operation
Unipolar or bipolar operation
True voltage output
Double-buffered inputs
Reset to minimum (DAC8413) or center scale (DAC8412)
Fast bus access time
Readback

APPLICATIONS

Automatic test equipment
Digitally controlled calibration
Servo controls
Process control equipment

GENERAL DESCRIPTION

The DAC8412/DAC8413 are quad, 12-bit voltage output
DACs with readback capability. Built using a complementary
BiCMOS process, these monolithic DACs offer the user very
high package density.

Output voltage swing is set by the two reference inputs V
and V

. By setting the V

REFL

input to 0 V and V

REFL

REFH

positive voltage, the DAC provides a unipolar positive output
range. A similar configuration with V

at 0 V and V

REFH

negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both V

to nonzero voltages. This method of setting output voltage

V

REFL

range has advantages over other bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.

Digital controls allow the user to load or read back data from any
DAC, load any DAC, and transfer data to all DACs at one time.

An active low

RESET

loads all DAC output registers to midscale

for the DAC8412 and zero scale for the DAC8413.

The DAC8412/DAC8413 are available in 28-lead plastic DIP,
28-lead ceramic DIP, 28-lead PLCC, and 28-lead LCC packages.

to a

REFL

REFH

REFH

at a

and

Voltage Output with Readback

DAC8412/DAC8413

FUNCTIONAL BLOCK DIAGRAM

LOGIC

12

DAT

RESET

I/O

DGND

R/W

LDAC

A0

A1

CS

I/O

PORT

CONTROL

LOGIC

INPUT
REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

OUTPUT

REG A

OUTPUT

REG B

OUTPUT

REG C

OUTPUT

REG D

Figure 1.

They can be operated from a wide variety of supply and reference
voltages with supplies ranging from single +5 V to ±15 V, and
references from +2.5 V to ±10 V. Power dissipation is less than
330 mW with ±15 V supplies and only 60 mW with a +5 V supply.

For MIL-STD-883 applications, contact your local Analog
Devices, Inc. sales office for the DAC8412/DAC8413/883 data
sheet, which specifies operation over the −55°C to +125°C
temperature range. All 883 parts are also available on Standard
Military Drawings 5962-91 76401MXA through 76404M3A.

0.500

0.375

0.250

0.125

–0.125

LINEAR ITY E RROR (LSB)

–0.250

–0.375

–0.500

+25°C

0

VDD = +15V
V

= –15V

SS

V

= +10V

REFH

V

= –10V

REFL

T

= –55°C, +25° C, +125°C

A

1024 1536 2046 2548 25 60 3072 40960

512

DIGITAL INPUT CODE (Decimal)

Figure 2. INL vs. Code Over Temperature

+125°C

–55°C

DAC A

DAC B

DAC C

DAC D

V

REFL

REFH

V

OUTA

V

OUTB

V

OUTC

V

OUTD

V

SS

00274-002

00274-001

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2000–2009 Analog Devices, Inc. All rights reserved.

DAC8412/DAC8413

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 14

REVISION HISTORY

9/09—Rev. E to Rev. F

Updated Figure Numbering .............................................. Universal

Removed Figure 7 ............................................................................. 6

Changes to Ordering Guide .......................................................... 20

6/07—Rev. D to Rev. E

Updated Format .................................................................. Universal

Added CERDIP Package .................................................... Universal

Changes to Specifications Section .................................................. 3

Changes to Absolute Maximum Ratings Section ......................... 7

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 20

3/00—Rev. C to Rev. D

Introduction ................................................................................ 14

DACs ............................................................................................ 14

Glitch ............................................................................................ 14

Reference Inputs ......................................................................... 14

Digital I/O ................................................................................... 14

Coding ......................................................................................... 14

Supplies ........................................................................................ 15

Amplifiers .................................................................................... 15

Reference Configurations .......................................................... 16

Single +5 V Supply Operation .................................................. 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 20

Rev. F | Page 2 of 20

DAC8412/DAC8413

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = +15.0 V, VSS = −15.0 V, V

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

ACCURACY

Integral Nonlinearity Error INL E grade ±0.25 ±0.5 LSB
F grade ±1 LSB
Differential Nonlinearity Error DNL Monotonic over temperature −1 LSB
Min-Scale Error V
Full-Scale Error V
Min-Scale Temperature Coefficient TCV
Full-Scale Temperature Coefficient TCV
Linearity Matching Adjacent DAC Matching ±1 LSB

REFERENCE

Positive Reference Input Voltage Range2 V
Negative Reference Input Voltage Range
Reference High Input Current I
Reference Low Input Current I
Large Signal Bandwidth BW −3 dB, V

AMPLIFIER CHARACTERISTICS

Output Current I
Settling Time tS To 0.01%, 10 V step, RL = 1 kΩ 10 μs
Slew Rate SR 10% to 90% 2.2 V/μs
Analog Crosstalk 72 dB

LOGIC CHARACTERISTICS

Logic Input High Voltage V
Logic Input Low Voltage V
Logic Output High Voltage VOH IOH = 0.4 mA 2.4 V
Logic Output Low Voltage VOL IOL = −1.6 mA 0.4 V
Logic Input Current IIN 1 μA
Input Capacitance C
Digital Feedthrough

3

LOGIC TIMING CHARACTERISTICS

Chip Select Write Pulse Width t
Write Setup t
Write Hold tWH t
Address Setup t
Address Hold tAH 0 ns
Load Setup tLS 70 ns
Load Hold tLH 30 ns
Write Data Setup t
Write Data Hold t
Load Data Pulse Width t
Reset Pulse Width t
Chip Select Read Pulse Width t
Read Data Hold t
Read Data Setup t
Data to High-Z t
Chip Select to Data t

= +5.0 V, V

LOGIC

3, 4

= +10.0 V, V

REFH

R

ZSE

R

FSE

RL = 2 kΩ 15 ppm/°C

ZSE

RL = 2 kΩ 20 ppm/°C

FSE

2

−10 V

−2.75 +1.5 +2.75 mA

REFH

0 2 2.75 mA

REFL

RL = 2 kΩ, CL = 100 pF –5 +5 mA

OUT

TA = 25°C 2.4 V

INH

T

INL

8 pF

IN

V

= −10.0 V,−40°C ≤ TA ≤ +85°C, unless otherwise noted.1

REFL

= 2 kΩ ±2 LSB

L

= 2 kΩ ±2 LSB

L

+ 2.5 VDD − 2.5 V

REFL

− 2.5 V

REFH

= 0 V to 10 V p-p 160 kHz

REFH

= 25°C 0.8 V

A

= 2.5 V, V

REFH

= 0 V 5 nV-sec

REFL

80 ns

WCS

t

WS

0 ns

AS

t

WDS

t

WDH

170 ns

LDW

140 ns

RESET

130 ns

RCS

t

RDH

t

RDS

C

DZ

CL = 100 pF 160 ns

CSD

= 80 ns 0 ns

WCS

= 80 ns 0 ns

WCS

= 80 ns 20 ns

WCS

= 80 ns 0 ns

WCS

= 130 ns 0 ns

RCS

= 130 ns 0 ns

RCS

= 10 pF 200 ns

L

Rev. F | Page 3 of 20

DAC8412/DAC8413

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY CHARACTERISTICS

Power Supply Sensitivity PSS 14.25 V ≤ VDD ≤ 15.75 V 150 ppm/V
Positive Supply Current I
Negative Supply Current I
Power Dissipation P

1

All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies.

2

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

3

All parameters are guaranteed by design.

4

All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

V

DD

−10 −6.5 mA

SS

330 mW

DISS

= 2.5 V 8.5 12 mA

REFH

VDD = V
unless otherwise noted.

= +5.0 V ± 5%, VSS = 0.0 V, V

LOGIC

1

= +2.5 V, V

REFH

= 0.0 V, VSS = –5.0 V ± 5%, V

REFL

= −2.5 V, −40°C ≤ TA ≤ +85°C,

REFL

Table 2.

Parameter Symbol Conditions Min Typ Max Units

ACCURACY

Integral Nonlinearity Error INL E grade ±0.5 ±1 LSB
F grade ±2 LSB
V
V

= 0.0 V, E grade2 ±2 LSB

SS

= 0.0 V, F grade

SS

2

±4 LSB

Differential Nonlinearity Error DNL Monotonic over temperature –1 LSB
Min-Scale Error V
Full-Scale Error V
Min-Scale Error V
Full-Scale Error V
Min-Scale Temperature Coefficient TCV
Full-Scale Temperature Coefficient TCV

VSS = −5.0 V ±4 LSB

ZSE

VSS = −5.0 V ±4 LSB

FSE

VSS = 0.0 V ±8 LSB

ZSE

V

FSE

100 ppm/°C

ZSE

100 ppm/°C

FSE

= 0.0 V ±8 LSB

SS

Linearity Matching Adjacent DAC matching ±1 LSB

REFERENCE

Positive Reference Input Voltage Range3 V
Negative Reference Input Voltage Range VSS = 0.0 V 0 V
V
Reference High Input Current I

Code 0x000 –1.0 +1.0 mA

REFH

Large Signal Bandwidth BW −3 dB, V

= −5.0 V –2.5 V

SS

= 0 V to 2.5 V p-p 450 kHz

REFH

+ 2.5 VDD − 2.5 V

REFL

− 2.5 V

REFH

− 2.5 V

REFH

AMPLIFIER CHARACTERISTICS

Output Current I

RL = 2 kΩ, CL = 100 pF –1.25 +1.25 mA

OUT

Settling Time tS To 0.01%, 2.5 V step, RL = 1 kΩ 7 μs
Slew Rate SR 10% to 90% 2.2 V/μs

LOGIC CHARACTERISTICS

Logic Input High Voltage V
Logic Input Low Voltage V

TA = 25°C 2.4 V

INH

TA = 25°C 0.8 V

INL

Logic Output High Voltage VOH IOH = 0.4 mA 2.4 V
Logic Output Low Voltage VOL IOL = −1.6 mA 0.45 V
Logic Input Current I
Input Capacitance C

4, 5

LOGIC TIMING CHARACTERISTICS

Chip Select Write Pulse Width t
Write Setup tWS t
Write Hold tWH t

1 μA

IN

8 pF

IN

150 ns

WCS

= 150 ns 0 ns

WCS

= 150 ns 0 ns

WCS

Address Setup tAS 0 ns
Address Hold t

0 ns

AH

Load Setup tLS 70 ns
Load Hold tLH 50 ns

Rev. F | Page 4 of 20

DAC8412/DAC8413

A

Parameter Symbol Conditions Min Typ Max Units

Write Data Setup t
Write Data Hold t
Load Data Pulse Width t
Reset Pulse Width t
Chip Select Read Pulse Width t
Read Data Hold t
Read Data Setup t
Data to High-Z t
Chip Select to Data t

SUPPLY CHARACTERISTICS

Power Supply Sensitivity PSS 100 ppm/V
Positive Supply Current I
Negative Supply Current I
Power Dissipation P

V

1

All supplies can be varied ±5%, and operation is guaranteed. Device is tested with V

2

For single-supply operation only (V

3

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

4

All parameters are guaranteed by design.

5

All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

= 0.0 V, VSS = 0.0 V). Due to internal offset errors, INL and DNL are measured beginning at 0x005.

REFL

t

t

AS

RDS

DATA VALID

t

RDH

t

AH

t

CS

R/W

0/A1

DATA

OUT

t

RCS

HIGH-Z HIGH-Z

t

CSD

Figure 3. Data Output (Read Timing)

t

WDS

t

WDH

180 ns

LDW

150 ns

RESET

170 ns

RCS

t

RDH

t

RDS

C

DZ

CL = 100 pF 320 ns

CSD

7 12 mA

DD

VSS = −5.0 V −10 mA

SS

VSS = 0 V 60 mW

DISS

DZ

= 150 ns 20 ns

WCS

= 150 ns 0 ns

WCS

= 170 ns 20 ns

RCS

= 170 ns 0 ns

RCS

= 10 pF 200 ns

L

= −5.0 V 110 mW

SS

= 4.75 V.

DD

t

CS

t

WS

R/W

t

AS

A0/A1

t

LS

LDAC

t

WDS

DATA IN

t

00274-003

RESET

RESET

WCS

t

WH

t

AH

t

LH

t

WDH

Figure 4. Data Write (Input and Output Registers) Timing

t

LDW

00274-004

Rev. F | Page 5 of 20

DAC8412/DAC8413

A

A

DDRESS

LDAC

DATA IN

CS

R/W

80ns

t

WS

t

AS

ADDRESS

ONE

DATA1

VALID

ADDRESS

TWO

t

LS

t

WDS

DATA2

VALID

Figure 5. Single-Buffer Mode

ADDRESS

THREE

DATA3

VALID

ADDRESS

FOUR

DATA4

VALID

80ns

CS

t

WH

R/W

DDRESS

t

LH

LDAC

t

WDH

00274-005

DATA IN

t

WS

t

AS

ADDRESS

ONE

t

WDS

DATA1
VALID

ADDRESS

TWO

DATA2

VALID

ADDRESS

THREE

DATA3

VALID

ADDRESS

FOUR

tLSt

DATA4

VALID

t

LH

LDW

t

t

WH

WDH

00274-006

Figure 6. Double-Buffer Mode

Rev. F | Page 6 of 20

DAC8412/DAC8413

ABSOLUTE MAXIMUM RATINGS

TA = +25°C, unless otherwise noted.

Table 3.

Parameter Rating

VSS to VDD −0.3 V, +33.0 V
VSS to V
V

LOGI C

VSS to V
V

REFH

V

REFH

Current into Any VSS pin ±15 mA
Digital Input Voltage to DGND −0.3 V, V
Digital Output Voltage to DGND −0.3 V, +7.0 V
Operating Temperature Range

EP, FP, FPC −40°C to +85°C

AT, BT, BTC −55°C to +125°C
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Power Dissipation Package 1000 mW
Lead Temperature JEDEC Industry Standard

Soldering J-STD-020

−0.3 V, +33.0 V

LOGI C

to DGND −0.3 V, +7.0 V

−0.3 V, +VSS − 2.0 V

REFL

to VDD +2.0 V, +33.0 V
to V

+2.0 V, VSS − VDD

REFL

+ 0.3 V

LOGI C

THERMAL RESISTANCE

θJA is specified for the worst-case mounting conditions, that is, a
device in socket.

Table 4. Thermal Resistance

Package Type θJA θJC Unit

28-Lead Plastic DIP (PDIP) 48 22 °C/W
28-Terminal Ceramic Leadless Chip Carrier (LLC) 70 28 °C/W
28-Lead Plastic Leaded Chip Carrier (PLLC) 63 25
28-Lead Ceramic Dual In-Line Package (CERDIP) 51 9 °C/W

°C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. F | Page 7 of 20

DAC8412/DAC8413

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

REFH

2

V

OUTB

V

3

OUTA

V

4

SS

5

DGND

RESET

LDAC

DB0 (LSB)

DB1

DB2

DB3

DB4

DB5

DB6

DAC8412/

6

DAC8413

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

Figure 7. PDIP/CERDIP Figure 8. PLCC Figure 9. LCC

Table 5. Pin Function Descriptions

Pin Number Mnemonic Description

1 V
2 V
3 V
4 V

REFH

OUTB

OUTA

SS

5 DGND
6
7

RESET

LDAC
8 DB0
9 DB1
10 DB2
11 DB3
12 DB4
13 DB5
14 DB6
15 DB7
16 DB8
17 DB9
18 DB10
19 DB11
20

R/W
21 A1 Address Bit 1.
22 A0
23
24 V
25 V
26 V
27 V
28 V

CS

LOGI C

DD

OUTD

OUTC

REFL

V

28

REFL

27

V

OUTC

V

26

OUTD

V

25

DD

24

V

LOGIC

CS

23

A0

22

21

A1

20

R/W

DB11 (MSB)

19

DB10

18

17

DB9

DB8

16

DB7

15

5

DGND

RESET

6

7

LDAC

8

DB1

9

10

DB2

DB3 DB11 (MSB)

11 19

00274-008

DB0 (LSB)

OUTAVOUTBVREFHVREFLVOUTCVOUTD

VSSV

1282726234

PIN 1

INDENTFIER

DAC8412/

DAC8413

TOP VIEW

(Not to Scale)

12 13 14 15 16 17 18

DB4

DB5

DB6

DB7

DB8

DB9

DB10

25

V

DD

24

V

LOGIC

23

CS

22

A0

21

A1

20

R/W

RESET

DB0 (LSB)

00274-009

High-Side DAC Reference Input.

DAC B Output.
DAC A Output.

Lower Rail Power Supply.

Digital Ground.
Reset Input and Output Registers to all 0s, Enabled at Active Low.
Load Data to DAC, Enabled at Active Low.

Data Bit 0, LSB.
Data Bit 1.
Data Bit 2.
Data Bit 3.
Data Bit 4.
Data Bit 5.
Data Bit 6.
Data Bit 7.
Data Bit 8.
Data Bit 9.
Data Bit 10.
Data Bit 11, MSB.
Active Low to Write Data to DAC. Active high to readback previous data at data bit pins with V

Address Bit 0.
Chip Select, Enabled at Active Low.

Voltage Supply for Readback Function. Can be open circuit if not used.

Upper Rail Power Supply.

DAC D Output.

DAC C Output.

Low-Side DAC Reference Input.

DGND

LDAC

DB1

DB2

DB3

SS

V

V

V

1

2

3

4

5

6

DAC8412/

7

DAC8413

8

9

10

11

(Not to Scale)

13

12

DB5

DB4

TOP VIEW

15

14

DB6

V

V

V

26

27

28

18

17

16

DB9

DB8

DB7

connected to 5 V.

LOGI C

V

DB10

25

V

DD

24

V

LOGIC

23

CS

22

A0

21

A1

20

R/W

19

DB11 (MSB)

OUTD

OUTC

REFL

REFH

OUTB

OUTA

00274-010

Rev. F | Page 8 of 20

DAC8412/DAC8413

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = +15V

= –15V

V

)
B
S
L

(

1

R
O
R
R
E
Y
T

I

0

R
A
E
N

I
L

M
U
M

–1

I
X
A
M

)
B
S
L

(

1

R
O
R
R
E
Y
T

I

0

R
A
E
N

I
L

M
U
M

–1

I
X
A
M

SS

V

REFL

= 25°C

T

A

6

= –10V

V

(V)

REFH

Figure 10. DNL vs. V

2

11109871

REFH

VDD = 5V
V

= 0V

SS

V

= 0V

REFL

T

= 25°C

A

00274-011

)
B

2

S
L

(
R

O

1

R
R
E

Y
T

I

0

R
A
E
N

I
L

–1

M
U
M

I
X
A

–2

M

)
B
S
L

(

0.3

R

O
R
R
E

Y
T

I

0.2

R
A
E
N

I
L

M
U
M

0.1

I
X
A

M

VDD = 5V
V

= 0V

SS

V

= 0V

REFL

T

= 25°C

A

V

(V)

REFH

Figure 13. DNL vs. V

REFH

321

VDD = +15V
V

SS

V

REFL

T

A

= –15V

= 0V

= 25°C

00274-012

REFH

321

VDD = +15V
V

= –15V

SS

V

REFH

V

REFL

V

(V)

REFH

Figure 11. INL vs. V

0.4

0.2

0

–0.2

FULL-SCAL E ERROR (LSB)

–0.4

–0.6

0

200

T = HOURS OF OPERATION AT 125°C

400 600 800

Figure 12. Full-Scale Error vs. Time Accelerated by Burn-in

= +10V

= –10V

X+3σ

X–3σ

00274-014

V

Figure 14. INL vs.V

0.3

0.1

–0.1

–0.3

X

1000

00274-015

ZERO-SCALE ERROR (LSB)

–0.5

–0.7

0

200

T = HOURS OF OPERATI ON AT 125°C

400 600 800

108612

REFH

(V)

REFH

VDD = +15V

= –15V

V

SS

V

REFH

V

REFL

= +10V

= –10V

X+3σ

X–3σ

00274-013

X

1000

00274-016

Figure 15. Zero-Scale Error vs. Time Accelerated by Burn-In

Rev. F | Page 9 of 20

DAC8412/DAC8413

0.2

VDD = +15V

= –15V

V

SS

= +10V

V

REFH

= –10V

V

0

REFL

1.00

0.75

0.50

0.25

VDD = 5V
V

= 0V

SS

V

REFH

T

= 25°C

A

= 2.5V

–0.2

DAC A

DAC D

–0.4

FULL-SCAL E ERROR (LSB)

–0.6

–75

0

TEMPERATURE (° C)

DAC B

DAC C

75 150

00274-017

Figure 16. Full-Scale Error vs. Temperature

0.2

0

DAC A

–0.2

DAC D

–0.4

ZERO-SCALE ERROR (LSB)

–0.6

–75

0

TEMPERATURE ( °C)

DAC B

VDD = +15V

= –15V

V

SS

= +10V

V

REFH

= –10V

V

REFL

DAC C

75 150

00274-018

Figure 17. Zero-Scale Error vs. Temperature

0

–0.25

LINEARITY ERROR (LSB)

–0.50

–0.75

–1.00

0 512 1024 1536 2048 2560 3072 3584 4096

Figure 19. Channel-to-Channel Matching (V

13

10

(mA)

DD

I

7

4

73

DIGITAL INPUT CODE (Decimal)

15913

V

REFH

Figure 20. I

vs. V

DD

REFH

SUPPLY

VDD = +15V
VSS = –15V
V

(V)

(All DACs High)

REFL

= +5 V/GND)

= –10V

00274-020

00274-021

0.37500

0.26125

0.18750

0.08375

0

–0.09375

LINEARITY ERROR (LSB)

–0.18750

–0.23125

–0.37500

0512

1024 1536 2048 2560 3072 3584 4096

DIGITAL INPUT CODE (Decimal)

Figure 18. Channel-to-Channel Matching (V

V

REFH

V

REFL

T

A

SUPPLY

= 10V

= 0V

= 25°C

= ±15 V)

00274-019

Rev. F | Page 10 of 20

0.500

0.375

0.250

0.125

–0.125

LINEARITY ERROR (LSB)

–0.250

–0.375

–0.500

0

VDD = +15V
V

= –15V

SS

V

= +10V

REFH

V

= –10V

REFL

T

= –55°C, +25° C, +125°C

A

512

1024 1536 2048 2560 3072 3584 40960

DIGITAL INPUT CODE (Decimal)

Figure 21. INL vs. Code

00274-022

DAC8412/DAC8413

V

V

V

V

T

V

10

10

1V/DIV

EA

TRIG'D

0V

–580ns

15.5m

INPUT

–5V

2mV/DIV

5V/DIV

TRIG'D

–4.5mV

–1.96µs

1V/DI

VDD = +15V
V

= –15V

SS

V

= +10V

REFH

V

= –10V

REFL

T

= 25°C

A

1µs/DIV

9.42µs

00274-026

Figure 22. Positive Slew Rate

0

VDD = +15V
V

= –15V

SS

V

= +10V

REFH

V

= –10V

REFL

T

= 25°C

A

EA

RIG'D

0V

–580ns

2.0

1.5

VDD = +15V
V

= –15V

SS

V

= +10V

REFH

V

= –10V

REFL

T

= 25°C

A

1µs/DIV 9.42µs

Figure 25. Negative Slew Rate

VDD = +15V
V

= –15V

SS

V

= +10V

REFH

V

= –10V

REFL

T

= 25°C

A

00274-027

1.0

(mA)

VREFH

0.5

I

0

2µs/DIV

Figure 23. Settling Time (Negative)

18.04µs

00274-025

–0.5

1023 1535 2047 2559 3071 3583 40950

511

DIGITAL INPUT CODE (Decimal)

Figure 26. I

VREFH

00274-023

vs. Code

32.5m

5V

INPUT

5mV/DIV

5V/DIV

TRIG'D

–17.5mV

–1.96µs

1.0
VDD = +15V
V

= –15V

SS

V
V
T

REFH

REFL

A

= +10V
= –10V

= 25°C

0

0.8

0.6

1 LSB ERRO R BAND

0.4

INL (LSB)

0.2

0

–0.2

0.01 0.1 1 10 100

LOAD RESISTANCE (kΩ)

Figure 27. INL vs. Load Resistance

00274-028

2µs/DIV

Figure 24. Settling Time (Positive)

VDD = +15V
V

= –15V

SS

V

= +10V

REFH

V

= –10V

REFL

T

= 25°C

A

18.04µs

00274-024

Rev. F | Page 11 of 20

DAC8412/DAC8413

12

VDD = +15V
V

= –15V

SS

V
V
T

REFH

REFL

A

= +10V
= –10V

= 25°C

10

8

6

4

FULL-SCALE VOLTAGE (V)

2

0

0.01 0.1 1 10 100

LOAD RESISTANCE (kΩ)

Figure 28. Output Swing vs. Load Resistance

00274-029

100

80

60

+PSRR:
V

40

V

–PSRR:
V

20

V
V

POWER SUPPLY REJECTION RATIO (dB)

ALL DATA 0

0

10 100k10k1k100

= +15V ±1Vp

DD

= –15V

SS

= +15V

DD

= –15V ±1V

SS

= +10V

REFH

FREQUENCY (Hz)

Figure 31. PSRR vs. Frequency

+PSRR

–PSRR

1M

00274-032

0

–10

GAIN (dB)

–30

VDD = +15V
VSS = –15V
V

= 0 ±100mV

REFH

–50

V

= –10V

REFL

DATA BITS = +5V
200mV p-p

–70

0

FREQUENCY (Hz)

Figure 29. Small Signal Response

10

I

DD

6

VDD= +15V
V

= –15V

SS

2

–2

I

POWER SUPPL Y CURRENT (mA)

–10

–6

–75

SS

TEMPERATURE ( °C)

Figure 30. Power Supply Current vs. Temperature

10

1

VDD = +15V
V

= –15V

SS

V

= +10V

REFH

V

= –10V

REFL

T

= 25°C

A

0.10

NOISE DENSI TY (µV)

0.01

1M

10M10 100k10k1k100

00274-030

0.001
1 10 100 1k 10k

NOISE FREQ UENCY (Hz)

00274-033

Figure 32. Noise Density vs. Noise Frequency

40

VDD = +15V
V

= –15V

SS

30

V

= +10V

REFH

V

= –10V

REFL

20

T

= 25°C

A

DATA = 0x000

10

(mA)

0

OUT

I

–10

–20

–I

–30

750

150

00274-031

–40

–25 –20

SC

Figure 33. I

(V)

V

OUT

vs. V

OUT

OUT

+I

SC

25

20151050–5–1 0–15

00274-034

Rev. F | Page 12 of 20

DAC8412/DAC8413

10µs

CH1 MEAN

66.19µV

1

VDD = +15V
VSS = –15V
V

= +10V

REFH

V

= –10V

REFL

TA = 25°C

20µV/DIV M 200µs A CH1 12.9mV

Figure 34. Broadband Noise

25

20

15

10

(mA)

OUT

I

–5

–10

–15

–20

–25

VDD = +15V
V

SS

V

REFH

V

REFL

T

= 25°C

A

DATA = 0x800

5

0

= 0V

= +10V
= 0V

–I

–4

SC

–2 0 2 4

V

(V)

OUT

+I

SC

1V

GLITCH AT DAC OUTPUT

2

1

1V

00274-035

DEGLITCHER OUTPUT

Figure 36. Glitch and Deglitched Results

6–6

00274-036

4µs

CH2 1.86V

00274-037

vs. V

Figure 35. I

OUT

OUT

Rev. F | Page 13 of 20

DAC8412/DAC8413

−

THEORY OF OPERATION

INTRODUCTION

The DAC8412/DAC8413 are quad, voltage output, 12-bit parallel
input DACs featuring a 12-bit data bus with readback capability.
The only differences between the DAC8412/DAC8413 are the
reset functions. The DAC8412 resets to midscale (Code 0x800),
and the DAC8413 resets to minimum scale (Code 0x000).

The ability to operate from a single 5 V supply is a unique
feature of these DACs.

Operation of the DAC8412/DAC8413 can be viewed by
dividing the system into three separate functional groups: the
digital I/O and logic, the digital-to-analog converters, and the
output amplifiers.

DACS

Each DAC is a voltage switched, high impedance (R = 50 kΩ),
R-2R ladder configuration. Each 2R resistor is driven by a pair
of switches that connect the resistor to either V

REFH

or V

REFL

.

GLITCH

Worst-case glitch occurs at the transition between Half-Scale
Digital Code 1000 0000 0000 to half-scale minus 1 LSB, 0111
1111 1111. It can be measured at about 2 V μs (see Figure 36).
For demanding applications such as waveform generation or
precision instrumentation control, a deglitcher circuit can be
implemented with a standard sample-and-hold circuit (see
Figure 37). When
period to be longer than the glitch tradition, the output voltage
can be smoothed with minimum disturbance. A quad
sample-and-hold amplifier, SMP04, has been used to illustrate
the deglitching result (see ). Figure 36

DACOUT

CS

S/H

DACOUT

CS

is enabled by synchronizing the hold

DACOUT

S/H

HSH

1

Figure 37. Data Output (Read Timing)

DACOUT

1

S

00274-038

REFERENCE INPUTS

All four DACs share common reference high (V
low (V

) inputs. The voltages applied to these reference inputs set

REFL

the output high and low voltage limits of all four of the DACs.
Each reference input has voltage restrictions with respect to the
other reference and to the power supplies. The V
any voltage between V
any value between +V

and V

SS

REFH

− 2.5 V and V

DD

− 2.5 V, and V

REFL

because of these restrictions, the DAC8412 references cannot be
inverted (that is, V

cannot be greater than V

REFL

It is important to note that the DAC8412 V
and sources current. In addition, the input current of both V
and V

are code-dependent. Many references have limited

REFL

current-sinking capability and must be buffered with an
amplifier to drive V

REFH

. The V

has no such special

REFL

requirements.

It is recommended that the reference inputs be bypassed with

0.2 μF capacitors when operating with ±10 V references. This
limits the reference bandwidth.

) and reference

REFH

can be set at

REFL

can be set to

REFH

+ 2.5 V. Note that

).

REFH

input both sinks

REFH

REFH

DIGITAL I/O

See Tab le 6 for the digital control logic truth table. Digital I/O
consists of a 12-bit bidirectional data bus, two registers select
inputs, A0 and A1, a R/
and a load DAC (

W

input, a

LDAC

) input. Control of the DACs and bus

direction is determined by these inputs as shown in Digital

RESET

input, a chip select (CS),

Tabl e 6.
data bits are labeled with the MSB defined as Data Bit 11 and the
LSB as Data Bit 0. All digital pins are TTL/CMOS compatible.

See Figure 38 for a simplified I/O logic diagram. The register
select inputs A0 and A1 select individual DAC registers A
(Binary Code 00) through D (Binary Code 11). Decoding of the
registers is enabled by the

CS

input. When CS is high, no
decoding takes place, and neither the writing nor the reading of
the input registers is enabled. The loading of the second bank of
registers is controlled by the asynchronous

LDAC

taking

low while CS is enabled, all output registers can

be updated simultaneously. Note that the t

LDAC

input. By

required pulse

LDW

width for updating all DACs is a minimum of 170 ns.

W

The R/

input, when enabled by CS, controls the writing to

and reading from the input register.

CODING

Both DAC8412/DAC8413 use binary coding. The output
voltage can be calculated by

)( NVV

×

VV

+=

REFL

OUT

N is the digital code in decimal.

where

REFLREFH

4096

Rev. F | Page 14 of 20

DAC8412/DAC8413

is the digital output supply voltage for the readback

RESET

The
time during DAC operation. The
of

RESET

function can be used either at power-up or at any

RESET

function is independent

CS

. This pin is active low and sets the DAC output registers
to either center code for the DAC8412, or zero code for the
DAC8413. The reset-to-center code is most useful when the
DAC is configured for bipolar references and an output of 0 V
after reset is desired.

SUPPLIES

Supplies required are VSS, VDD, and V
be set between −15 V and 0 V. V

DD

operating range is between 5 V and 15 V.

Table 6. DAC8412/DAC8413 Logic Table

A1 A0

R/

CS RS LDAC

W

L L L L H L Write Write Transparent A
L H L L H L Write Write Transparent B
H L L L H L Write Write Transparent C
H H L L H L Write Write Transparent D
L L L L H H Write Hold Write input A
L H L L H H Write Hold Write input B
H L L L H H Write Hold Write input C
H H L L H H Write Hold Write input D
L L H L H H Read Hold Read input A
L H H L H H Read Hold Read input B
H L H L H H Read Hold Read input C
H H H L H H Read Hold Read input D
X X X H H L Hold Update all output registers All
X X X H H H Hold Hold Hold All
X X X X L X All registers reset to midscale/zero-scale
X X X H

1

DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = logic low; H = logic high; X = don’t care. Input and output registers are transparent when asserted.

. The VSS supply can

LOGIC

is the positive supply; its

Input Register Output Register Mode

X All registers latched to midscale/zero-scale

V

LOGIC

function. It is normally connected to +5 V. This pin is a logic
reference input only. It does not supply current to the device.
the readback function is not being used, V
circuit. While V

does not supply current to the DAC8412, it

LOGIC

can be left open-

LOGIC

If

does supply currents to the digital outputs when readback is used.

AMPLIFIERS

Unlike many voltage output DACs, the DAC8412 features buffered
voltage outputs. Each output is capable of both sourcing and
sinking 5 mA at ±10 V, eliminating the need for external
amplifiers when driving 500 pF or smaller capacitive load in
most applications. These amplifiers are short-circuit protected.

DAC

1

1

All
All

Rev. F | Page 15 of 20

DAC8412/DAC8413

T

V

V

REFHVDDVSS

CS

A0

A1

R/W

DB11..DB0

V

LOGIC

READBACK

DATAOUT_DB11

READOUTBAR

READBACKDATAIN_DB11

RDDACA

WRDACA

RDDACB

WRDACB

REGIS TER

RDDACC

WRDACC

RDDACD

WRDACD

INPUT

WRDB0

WRDB1

WRDB2

WRDB3

WRDB4

WRDB5

OUTPUT

WRDB6

REGISTER

WRDB7

WRDB8

WRDB9

WRDB10

WRDB11

READBACKDATAIN_DB10

READOUT

DAC A

DAC B

DAC C

DAC D

V

OUTA

V

OUTB

V

OUTC

V

OUTD

V

REFL

LDAC
RESE

DGND

Figure 38. Simplified I/O Logic Diagram

Careful attention to grounding is important for accurate
operation of the DAC8412. This is not because the DAC8412 is
more sensitive than other 12-bit DACs, but because with four
outputs and two references, there is greater potential for ground
loops. Because the DAC8412 has no analog ground, the ground
must be specified with respect to the reference.

REFERENCE CONFIGURATIONS

Output voltage ranges can be configured as either unipolar or
bipolar, and within these choices, a wide variety of options
exists. The unipolar configuration can be either positive or
negative voltage output, and the bipolar configuration can be
either symmetrical or nonsymmetrical.

INPUT

+15

REF10

+

OUTPUT

TRIM

OP400

0.2µF

10kΩ

+10V OPERATI ON

Figure 39. Unipolar +10 V Operation

V

V

REFH

REFL

+15V

V

DD

DAC8412

OR

DAC8413

V

SS

–15V

0.1µF
//10µF

00274-039

+15V

GAIN

100kΩ

BALANCE

100kΩ

39kΩ

AD688 FOR ±10V

AD588 FOR ±5V

6.2Ω

0.2µF

6.2Ω

0.2µF

1µF

+15V

V

DD

V

REFH

DAC8412

OR

DAC8413

V

REFL

V

SS

–15V

±5 OR ±10V OPERATION

0.1µF
//10µF

00274-041

Figure 40. Symmetrical Bipolar Operation

Figure 40 (symmetrical bipolar operation) shows the DAC8412
configured for ±10 V operation. See the AD688 data sheet for a
full explanation of reference operation. Adjustments may not be
required for many applications since the AD688 is a very high
accuracy reference. However, if additional adjustments are
required, adjust the DAC8412 full scale first. Begin by loading
the digital full-scale code (0xFFF), and then adjust the gain
adjust potentiometer to attain a DAC output voltage of 9.9976 V.

00274-040

Then, adjust the balance adjust to set the center-scale output
voltage to 0.000 V.

Rev. F | Page 16 of 20

DAC8412/DAC8413

Ω

V

The 0.2 μF bypass capacitors shown at the reference inputs in
Figure 40 should be used whenever ±10 V references are used.
Applications with single references or references to ±5 V may
not require the 0.2 μF bypassing. The 6.2 Ω resistor in series
with the output of the reference amplifier keeps the amplifier
from oscillating with the capacitive load. This 6.2 Ω resistor has
been found to be large enough to stabilize this circuit. Larger
resistor values are acceptable, provided that the drop across the
resistor does not exceed V

. Assuming a minimum VBE of 0.6 V

BE

and a maximum current of 2.75 mA, then the resistor should be
under 200 Ω for the loading of a single DAC8412.

Using two separate references is not recommended. Having two
references can cause different drifts with time and temperature;
whereas with a single reference, most drifts track.

Unipolar positive full-scale operation can usually be set with a
reference with the correct output voltage. This is preferable to
using a reference and dividing down to the required value. For a
10 V full-scale output, the circuit can be configured as shown in
Figure 41. In this configuration, the full-scale value is set first by
adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.

10k

V

REFH

V

REFL

V

DD

DAC8412

OR

DAC8413

V

SS

0.1µF
//10µF

00274-042

GND

TRIM

REF08

–15V

OUTPUT

0.2µF

0.01µF

10µF

ZERO TO –10V OPERATI ON

Figure 41. Unipolar –10 V Operation

Figure 41 shows the DAC8412 configured for –10 V to 0 V
operation. A REF08 with a –10 V output is connected directly

for the reference voltage.

to V

REFL

SINGLE +5 V SUPPLY OPERATION

For operation with a 5 V supply, the reference voltage should be
set between 1.0 V and 2.5 V for optimum linearity. Figure 42
shows a REF43 used to supply a 2.5 V reference voltage. The
headroom of the reference and DAC are both sufficient to support
a 5 V supply with ±5% tolerance. V
connected to the same supply. Separate bypassing to each pin
should also be used.

5

10µF 0. 01µF

INPUT

OUTPUT

REF43

TRIM

10kΩ

GND

ZERO TO 2.5V OPERAT ION

SINGLE 5V SUPPLY

Figure 42. +5 V Single-Supply Operation

V

0.2µF

V

REFH

REFL

and V

DD

DAC8412

DAC8413

V

OR

V

DD

SS

LOGIC

should be

0.1µF
//10µF

00274-043

Rev. F | Page 17 of 20

DAC8412/DAC8413

OUTLINE DIMENSIONS

0.300 (7.62)

26

28

1

REF

0.020 (0.51)
MIN

412

5

0.028 (0.71)

0.022 (0.56)

0.15 (3.81)
REF

0.095 (2.41)

0.075 (1.90)

022106-A

0.458 (11.63)

0.442 (11.23)

0.100 (2.54)

0.064 (1.63)

0.458

(11.63)

SQ

MAX

SQ

0.088 (2.24)

0.054 (1.37)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.05 (1.27)

0.075 (1.91)
REF

0.055 (1.40)

0.045 (1.14)

0.075
(1.91)

REF

19 25

11

18

BOTTON

VIEW

Figure 43. 28-Terminal Ceramic Leadless Chip Carrier [LCC]

(E-28-1)

Dimensions shown in inches and (millimeters)

1.565 (39.75)

1.380 (35.05)

0.250 (6.35)

0.200 (5.08)

0.115 (2.92)

0.022 (0.56)

0.014 (0.36)

MAX

28

15

0.580 (14.73)

0.485 (12.31)

114

0.100 (2.54)
BSC

0.015 (0.38)
GAUGE

0.015
(0.38)
MIN

SEATING
PLANE

0.005 (0.13)
MIN

PLANE

0.070 (1.78)

0.050 (1.27)

COMPLIANT TO JEDEC STANDARDS MS-011

CONTROLL ING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSI ONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.

Figure 44. 28-Lead Plastic Dual In-Line Package [PDIP]

Wide Body

(N-28-2)

Dimensions shown in inches and (millimeters)

0.625 (15.88)

0.600 (15.24)

0.700 (17.78)
MAX

0.195 (4.95)

0.125 (3.17)

0.015 (0.38)

0.008 (0.20)

071006-A

Rev. F | Page 18 of 20

DAC8412/DAC8413

0.048 (1.22)

0.042 (1.07)

0.048 (1.22)

0.042 (1.07)

4

5

11

12

0.456 (11.582)

0.450 (11.430)

0.495 (12.57)

0.485 (12.32)

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

CONTROLL ING DIMENSIONS ARE IN I NCHES; MILL IMETER DIM ENSIONS
(IN PARENTHESES ) ARE ROUNDED-OF F INCH EQUIVALENTS FO R
REFERENCE ONLY AND ARE NOT APPROP RIATE FO R USE IN DESIG N.

0.056 (1.42)

0.042 (1.07)

26

25

0.050
(1.27)
BSC

19

18

SQ

SQ

COMPLIANT TO JEDEC STANDARDS MO -047-AB

0.120 (3.04)

0.090 (2.29)

0.180 (4.57)

0.165 (4.19)

0.020 (0.51)
MIN

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.045 (1.14)

0.025 (0.64)

0.430 (10.92)

0.390 (9.91)

R

BOTTOM

VIEW

(PINS UP)

042508-A

Figure 45. 28-Lead Plastic Leaded Chip Carrier [PLCC]

(P-28)

Dimensions shown in inches and (millimeters)

0.100

(2.54)

BSC

0.100 (2.54)
MAX

0.070 (1.78)

0.030 (0.76)

15

0.610 (15.49)

0.500 (12.70)

0.015 (0.38)
MIN

0.150 (3.81)
MIN

SEATING
PLANE

15°

0°

0.620 (15.75)

0.590 (14.99)

0.018 (0.46)

0.008 (0.20)

PIN 1

0.225(5.72)
MAX

0.200 (5.08)

0.125 (3.18)

0.026 (0.66)

0.014 (0.36)

0.005 (0.13)
MIN

28

114

1.490 (37.85) MAX

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 46. 28-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-28-2)

Dimensions shown in inches and (millimeters)

Rev. F | Page 19 of 20

030106-A

DAC8412/DAC8413

ORDERING GUIDE

Model Temperature Range INL Package Description Package Option

DAC8412AT/883C −55°C to +125°C ±0.75 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2
DAC8412BT/883C −55°C to +125°C ±1.5 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2
DAC8412BTC/883C −55°C to +125°C ±1.5 28-Terminal Ceramic Leadless Chip Carrier [LCC] E-28-1
DAC8412EP
DAC8412EPZ
DAC8412FP
DAC8412FPC
DAC8412FPC-REEL
DAC8412FPCZ
DAC8412FPCZ-REEL
DAC8412FPZ
DAC8413AT/883C −55°C to +125°C ±0.75 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2
DAC8413BT/883C −55°C to +125°C ±1.5 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2
DAC8413BTC/883C −55°C to +125°C ±1.5 28-Terminal Ceramic Leadless Chip Carrier [LCC] E-28-1
DAC8413EP
DAC8413EPZ
DAC8413FP
DAC8413FPC
DAC8413FPC-REEL
DAC8413FPCZ
DAC8413FPC-REEL
DAC8413FPZ

1

If burn-in is required, these models are available in CERDIP. Contact sales.

2

Z = RoHS Compliant Part.

1

1, 2

1

−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2

1

−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28

1

1, 2

−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28

1, 2

−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2

1

−40°C to +85°C ±0.5 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2

1, 2

−40°C to +85°C ±0.5 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2

1

−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2

1

−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28

1

1, 2

−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28

1

1, 2

−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2

−40°C to +85°C ±0.5 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2

−40°C to +85°C ±0.5 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2

−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28

1, 2

−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28

−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28

−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2

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