Datasheet DAC7725UB-1K, DAC7725UB, DAC7725U-1K, DAC7725U, DAC7725NB-750 Datasheet (Burr Brown Corporation)

12-Bit Quad Voltage Output

DIGITAL-TO-ANALOG CONVERTER

®

DAC7724
DAC7725

DESCRIPTION

The DAC7724 and DAC7725 are 12-bit quad voltage
output digital-to-analog converters with guaranteed
12-bit monotonic performance over the specified tem­perature range. They accept 12-bit parallel input data,
have double-buffered DAC input logic (allowing simul­taneous update of all DACs), and provide a readback
mode of the internal input registers. An asynchronous
reset clears all registers to a mid-scale code of 800

H

(DAC7724) or to a zero-scale of 000H (DAC7725). The
DAC7724 and DAC7725 can operate from a single
+15V supply, or from +15V and –15V supplies.

Low power and small size per DAC make the DAC7724
and DAC7725 ideal for automatic test equipment,
DAC-per-pin programmers, data acquisition systems,
and closed-loop servo-control. The DAC7724 and
DAC7725 are available in a PLCC-28 or a SO-28
package, and offer guaranteed specifications over the
–40°C to +85°C temperature range.

FEATURES

● LOW POWER: 250mW max

● SINGLE SUPPLY OUTPUT RANGE: +10V

● DUAL SUPPLY OUTPUT RANGE: ±10V

● SETTLING TIME: 10µs to 0.012%

● 12-BIT LINEARITY AND MONOTONICITY:

–40°C to +85°C

● RESET TO MID-SCALE (DAC7724) OR

ZERO-SCALE (DAC7725)

● DATA READBACK

● DOUBLE-BUFFERED DATA INPUTS

APPLICATIONS

● PROCESS CONTROL

● CLOSED-LOOP SERVO-CONTROL

● MOTOR CONTROL

● DATA ACQUISITION SYSTEMS

© 1999 Burr-Brown Corporation PDS-1517B Printed in U.S.A. April, 2000

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone]

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

DAC A

DAC

Register A

Input

Register A

I/O

Buffer

Control

Logic

DAC B

DAC

Register B

Input

Register B

DAC C

DAC

Register C

Input

Register C

DAC D

DAC

Register D

Input

Register D

V

REFH

V

CC

V

DD

V

SS

V

OUTD

V

OUTC

V

OUTB

V

OUTA

V

REFL

RESET LDAC

GND

A0
A1

R/W

CS

DB0-DB11

12

For most current data sheet and other product

information, visit www.burr-brown.com

DAC7724

DAC7725

2

®

DAC7724, 7725

SPECIFICATION (DUAL SUPPLY)

At TA = –40°C to +85°C, VCC = +15V, VDD = +5V, VSS = –15V, V

REFH

= +10V, V

REFL

= –10V, unless otherwise noted.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

DAC7724N, U DAC7724NB, UB

DAC7725N, U DAC7725NB, UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY

Linearity Error ±2 ±1 LSB

(1)

Linearity Matching

(2)

±2 ±1 LSB
Differential Linearity Error ±1 ±1 LSB
Monotonicity T

MIN

to T

MAX

12 ✻ Bits

Zero-Scale Error Code = 000

H

±2 ✻ LSB
Zero-Scale Drift 1 ✻ ppm/°C
Zero-Scale Matching

(2)

±2 ±1 LSB
Full-Scale Error Code = FFF

H

±2 ✻ LSB
Full-Scale Matching

(2)

±2 ±1 LSB
Power Supply Sensitivity At Full Scale 10 ✻ ppm/V

ANALOG OUTPUT

Voltage Output

(3)

V

REFL

V

REFH

✻✻V
Output Current ±5 ✻✻mA
Load Capacitance No Oscillation 500 ✻ pF
Short-Circuit Current ±20 ✻ mA
Short-Circuit Duration To V

SS

, VCC, or GND Indefinite ✻

REFERENCE INPUT

V

REFH

Input Range

V

REFL

+1.25

+10 ✻✻V

V

REFL

Input Range –10

V

REFH

– 1.25

✻✻V
Ref High Input Current –0.5 3.0 ✻✻mA
Ref Low Input Current –3.5 0 ✻✻mA

DYNAMIC PERFORMANCE

Settling Time To ±0.012%, 20V Output Step 8 10 ✻✻ µs
Channel-to-Channel Crosstalk

Full-Scale Step

0.25 ✻ LSB
Digital Feedthrough 2 ✻ nV-s
Output Noise Voltage f = 10kHz 65 ✻ nV/√Hz

DIGITAL INPUT/OUTPUT

Logic Family TTL-Compatible CMOS ✻
Logic Levels

V

IH

IIH ≤ ±10µA 2.4 VDD +0.3 ✻✻V

V

IL

IIL ≤ ±10µA –0.3 0.8 ✻✻V

V

OH

IOH = –0.8mA 3.6 V

DD

✻✻V

V

OL

IOL = 1.6mA 0.0 0.4 ✻✻V

Data Format Straight Binary ✻

POWER SUPPLY REQUIREMENTS

V

DD

+4.75 +5.25 ✻✻V

V

CC

+14.25 +15.75 ✻✻V

V

SS

–14.25 –15.75 ✻✻V

I

DD

50 ✻✻ µA

I

CC

6 8.5 ✻✻ mA

I

SS

–8 –6 ✻✻ mA

Power Dissipation 180 250 ✻✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

NOTES: (1) LSB means Least Significant Bit, when V

REFH

equals +10V and V

REFL

equals –10V, then one LSB equals 4.88mV. (2) All DAC outputs will match within

the specified error band. (3) Ideal output voltage, does not take into account zero or full-scale error.

3

®

DAC7724, 7725

SPECIFICATION (SINGLE SUPPLY)

At TA = –40°C to +85°C, VCC = +15V, VDD = +5V, VSS = GND, V

REFH

= +10V, V

REFL

= 0V, unless otherwise noted.

DAC7724N, U DAC7724NB, UB

DAC7725N, U DAC7725NB, UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY

Linearity Error

(1)

±2 ±1 LSB

(2)

Linearity Matching

(3)

±2 ±1 LSB
Differential Linearity Error ±1 ±1 LSB
Monotonicity T

MIN

to T

MAX

12 ✻ Bits

Zero-Scale Error Code = 004

H

±4 ✻ LSB
Zero-Scale Drift 2 ✻ ppm/°C
Zero-Scale Matching

(3)

±4 ±2 LSB
Full-Scale Error Code = FFF

H

±4 ✻ LSB
Full-Scale Matching

(3)

±4 ±2 LSB
Power Supply Sensitivity At Full Scale 20 ✻ ppm/V

ANALOG OUTPUT

Voltage Output

(4)

V

REFL

V

REFH

✻✻V
Output Current ±5 ✻ mA
Load Capacitance No Oscillation 500 ✻ pF
Short-Circuit Current ±20 ✻ mA
Short-Circuit Duration To V

CC

or GND Indefinite ✻

REFERENCE INPUT

V

REFH

Input Range

V

REFL

+1.25

+10 ✻✻V

V

REFL

Input Range 0

V

REFH

– 1.25

✻✻V
Ref High Input Current –0.3 1.5 ✻✻mA
Ref Low Input Current –2.0 0 ✻✻mA

DYNAMIC PERFORMANCE

Settling Time

(5)

To ±0.012%, 10V Output Step 8 10 ✻✻ µs
Channel-to-Channel Crosstalk 0.25 ✻ LSB
Digital Feedthrough 2 ✻ nV-s
Output Noise Voltage f = 10kHz 65 ✻ nV/√Hz

DIGITAL INPUT/OUTPUT

Logic Family TTL-Compatible CMOS ✻
Logic Levels

V

IH

IIH ≤ ±10µA 2.4 VDD +0.3 ✻✻V

V

IL

IIL ≤ ±10µA –0.3 0.8 ✻✻V

V

OH

IOH = –0.8mA 3.6 V

DD

✻✻V

V

OL

IOL = 1.6mA 0.0 0.4 ✻✻V

Data Format Straight Binary ✻

POWER SUPPLY REQUIREMENTS

V

DD

+4.75 +5.25 ✻✻V

V

CC

14.25 15.75 ✻✻V

I

DD

50 ✻✻ µA

I

CC

3.0 ✻✻ mA

Power Dissipation 45 ✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

NOTES: (1) If V

SS

= 0V, specification applies at code 004H and above. (2) LSB means Least Significant Bit, when V

REFH

equals +10V and V

REFL

equals 0V, then
one LSB equals 2.44mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error.
(5) Full-scale positive 10V step and negative step from code FFF

H

to 004H.

4

®

DAC7724, 7725

RefH

V

SS

V

CC

V

DD

V

CC

V

SS

V

DD

GND

V

OUT

RefL

1 of 4

Typ of Each

Logic Input Pin

Typ of Each

I/O Pin

ABSOLUTE MAXIMUM RATINGS

(1)

V

CC

to VSS........................................................................... –0.3V to +32V

V

CC

to GND......................................................................... –0.3V to +16V

V

SS

to GND ......................................................................... +0.3V to –16V

V

DD

to GND............................................................................. –0.3V to 6V

V

REF

H to GND ....................................................................... –9V to +11V

V

REF

L to GND (VSS = –15V) ................................................. –11V to +9V

V

REF

L to GND (VSS = 0V) .................................................... –0.3V to +9V

V

REFH

to V

REFL

....................................................................... –1V to +22V

Digital Input Voltage to GND ................................... –0.3V to V

DD

+ 0.3V

Digital Output Voltage to GND ................................. –0.3V to V

DD

+ 0.3V

Maximum Junction Temperature................................................... +150°C

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range ......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION

MAXIMUM MAXIMUM

LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION

ERROR NONLINEARITY ERROR DRAWING TEMPERATURE ORDERING TRANSPORT

PRODUCT (LSB) (LSB) PACKAGE NUMBER RANGE NUMBER

(1)

MEDIA

DAC7724N ±2 ±1 PLCC-28 251 –40°C to +85°C DAC7724N Rails

"" " "" "DAC7724N/750 Tape and Reel

DAC7724NB ±1 ±1 PLCC-28 251 –40°C to +85°C DAC7724NB Rails

"" " "" "DAC7724NB/750 Tape and Reel

DAC7724U ±2 ±1 SO-28 217 –40°C to +85°C DAC7724U Rails

"" " "" "DAC7724U/1K Tape and Reel

DAC7724UB ±1 ±1 SO-28 217 –40°C to +85°C DAC7724UB Rails

"" " "" "DAC7724UB/1K Tape and Reel

DAC7725N ±2 ±1 PLCC-28 251 –40°C to +85°C DAC7725N Rails

"" " "" "DAC7725N/750 Tape and Reel

DAC7725NB ±1 ±1 PLCC-28 251 –40°C to +85°C DAC7725NB Rails

"" " "" "DAC7725NB/750 Tape and Reel

DAC7725U ±2 ±1 SO-28 217 –40°C to +85°C DAC7725U Rails

"" " "" "DAC7725U/1K Tape and Reel

DAC7725UB ±1 ±1 SO-28 217 –40°C to +85°C DAC7725UB Rails

"" " "" "DAC7725UB/1K Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /750 indicates 750 devices per reel). Ordering 750 pieces
of “DAC7724/750” will get a single 750-piece Tape and Reel.

ESD PROTECTION CIRCUITS

5

®

DAC7724, 7725

Top View

PIN CONFIGURATIONS

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

1V

REFH

Reference Input Voltage High. Sets maximum output voltage for all DACs.

2V

OUTB

DAC B Voltage Output.

3V

OUTA

DAC A Voltage Output.

4V

SS

Negative Analog Supply Voltage, 0V or –15V.
5 GND Ground.
6 RESET Asynchronous Reset Input. Sets DAC and input registers to either mid-scale (800

H

, DAC7724) or zero-scale (000H, DAC7725)

when LOW.
7 LDAC Load DAC Input. All DAC Registers are transparent when LOW.
8 DB0 Data Bit 0. Least significant bit of 12-bit word.
9 DB1 Data Bit 1

10 DB2 Data Bit 2
11 DB3 Data Bit 3
12 DB4 Data Bit 4
13 DB5 Data Bit 5
14 DB6 Data Bit 6
15 DB7 Data Bit 7
16 DB8 Data Bit 8
17 DB9 Data Bit 9
18 DB10 Data Bit 10
19 DB11 Data Bit 11. Most significant bit of 12-bit word.
20 R/W Read/Write Control Input (read = HIGH, write = LOW).
21 A1 Register/DAC Select (C or D = HIGH, A or B = LOW).
22 A0 Register/DAC Select (B or D = HIGH, A or C = LOW).
23 CS Chip Select Input.
24 V

DD

Positive Digital Supply, +5V.

25 V

CC

Positive Analog Supply Voltage, +15V nominal.

26 V

OUTD

DAC D Voltage Output.

27 V

OUTC

DAC C Voltage Output.

28 V

REFL

Reference Input Voltage Low. Sets minimum output voltage for all DACs.

1
2
3
4
5
6
7
8

9
10
11
12
13
14

V

REFH

V

OUTB

V

OUTA

V

SS

GND

RESET

LDAC

(LSB) DB0

DB1
DB2
DB3
DB4
DB5
DB6

V

REFL

V

OUTC

V

OUTD

V

CC

V

DD

CS
A0
A1
R/W
DB11 (MSB)
DB10
DB9
DB8
DB7

28
27
26
25
24
23
22
21
20
19
18
17
16
15

DAC7724
DAC7725

GND

RESET

LDAC

(LSB) DB0

DB1
DB2
DB3

5

6

7

8

9

10

11

25

24

23

22

21

20

19

V

CC

V

DD

CS
A0
A1
R/W
DB11 (MSB)

VSSV

OUTAVOUTBVREFHVREFLVOUTCVOUTD

DB4

DB5

DB6

DB7

DB8

DB9

DB10

4 3 2 1 28 27 26

12 13 14 15 16 17 18

DAC7724
DAC7725

SO PLCC

6

®

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: VSS = 0V

At TA = +25°C, VCC = +15V, VDD = +5V, VSS = 0V, V

REFH

= +10V, V

REFL

= 0V, representative unit, unless otherwise specified.

000H200H400H600H800

H

Digital Input Code

A00

H

C00HE00HFFF

H

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel 25°C

(Typical of Each Output Channel)

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

LE (LSB)DLE (LSB)

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

LE (LSB)DLE (LSB)

000H200H400H600H800

H

Digital Input Code

A00

H

C00HE00HFFF

H

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel 85°C

(Typical of Each Output Channel)

000H200H400H600H800

H

Digital Input Code

A00

H

C00HE00HFFF

H

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel –40°C

(Typical of Each Output Channel)

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

LE (LSB)DLE (LSB)

–30 –20 –10 0 10 20 30 40 50 60 70 80 90–40

Temperature (°C)

ZERO-SCALE ERROR vs TEMPERATURE

(Code 004

H

)

Zero-Scale Error (mV)

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

DAC A

DAC B

DAC C

DAC D

–30 –20 –10 0 10 20 30 40 50 60 70 80 90–40

Temperature (°C)

FULL-SCALE ERROR vs TEMPERATURE

(Code FFF

H

)

Full-Scale Error (mV)

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

DAC A

DAC B

DAC C

DAC D

1.2

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4

0

–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6

V

REF

Current (mA)V

REF

Current (mA)

000H200H400H600H800

H

Digital Input Code

A00

H

C00HE00HFFF

H

CURRENT vs CODE

All DACs Sent to Indicated Code

V

REFH

V

REFL

7

®

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)

At TA = +25°C, VCC = +15V, VDD = +5V, VSS = 0V, V

REFH

= +10V, V

REFL

= 0V, representative unit, unless otherwise specified.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5

POWER SUPPLY CURRENT vs TEMPERATURE

Quiescent Current (mA)

Temperature (°C)

–40–30 –20 –10 0 10 20 30 40 50 60 70 80 90 100

I

DD

I

CC

I

DD

I

CC

POSITIVE SUPPLY CURRENT

vs DIGITAL INPUT CODE

3.00

2.50

2.00

1.50

1.00

0.50

0

I

CC

(mA)

No Load

200H400H600H800HA00HC00HE00HFFF

H

000

H

Digital Input Code

OUTPUT VOLTAGE

MID-SCALE GLITCH PERFORMANCE

Time (1µs/div)

800H to 7FF

H

+5V
LDAC
0

Output Voltage (200mV/div)

OUTPUT VOLTAGE

MID-SCALE GLITCH PERFORMANCE

Time (1µs/div)

7FFH to 800

H

+5V
LDAC
0

Output Voltage (200mV/div)

OUTPUT VOLTAGE vs SETTLING TIME

(+10V to 0V)

Time (2µs/div)

Large Signal Settling Time: 5V/div

+5V
LDAC
0

Small Signal
Settling Time: 1LSB/div

Output Voltage

OUTPUT VOLTAGE vs SETTLING TIME

(0V to +10V)

Large Signal Settling Time: 5V/div

Small Signal Settling Time: 1LSB/div

+5V
LDAC
0

Output Voltage

Time (2µs/div)

8

®

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)

At TA = +25°C, VCC = +15V, VDD = +5V, VSS = 0V, V

REFH

= +10V, V

REFL

= 0V, representative unit, unless otherwise specified.

+15V

+5V

POWER SUPPLY REJECTION RATIO vs FREQUENCY

Frequency (Hz)

PSRR (dB)

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100

–110

–120

10

2

10

3

10

4

10

5

10

6

10

1

SINGLE SUPPLY CURRENT LIMIT vs INPUT CODE

20
15
10

5
0

–5
–10
–15
–20

I

OUT

(mA)

200H400H600H800HA00HC00HE00HFFF

H

000

H

Digital Input Code

Short to Ground

Short to V

CC

16
14
12
10

8
6
4
2
0

R

LOAD

(kW)

0.01

0.1

1 10 100

OUTPUT VOLTAGE vs R

LOAD

V

OUT

(V)

Source

Sink

LOGIC SUPPLY CURRENT

vs LOGIC INPUT LEVEL FOR DATA BITS

Logic Input Level for Data Bits (V)

Logic Supply Current (mA)

5

4

3

2

1

0

0 0.5 1.0 1.5 2.0 2.5 3.53.0 4.5 5.04.0

OUTPUT NOISE vs FREQUENCY

Frequency (kHz)

Noise (nV/√Hz)

1000

100

10

0.1 1 10 100 1000 100000

Code 004

H

Code FFF

H

9

®

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: VSS = –15V

At TA = +25°C, VCC = +15V, VDD = +5V, VSS = –15V, V

REFH

= +10V, V

REFL

= –10V, representative unit, unless otherwise specified.

–30 –20 –10 0 10 20 30 40 50 60 70 80 90–40

Temperature (°C)

POSITIVE FULL-SCALE ERROR vs TEMPERATURE

(Code FFF

H

)

Positive Full-Scale Error (mV)

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

DAC A

DAC B

DAC C

DAC D

–30 –20 –10 0 10 20 30 40 50 60 70 80 90–40

Temperature (°C)

BIPOLAR ZERO-SCALE ERROR vs TEMPERATURE

(Code 800

H

)

Bipolar Zero-Scale Error (mV)

DAC A

DAC B

DAC C

DAC D

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

2.5

2.0

1.5

1.0

0.5
0

–0.5

V

REF

Current (mA)

CURRENT vs CODE

All DACs Sent to Indicated Code

V

REFH

V

REFL

000H200H400H600H800

H

Digital Input Code

A00

H

C00HE000HFFF

H

0

–0.5
–1.0
–1.5
–2.0
–2.5
–3.0

V

REF

Current (mA)

000H200H400H600H800

H

Digital Input Code

A00

H

C00HE00HFFF

H

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel –40°C

(Typical of Each Output Channel)

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

LE (LSB)DLE (LSB)

000H200H400H600H800

H

Digital Input Code

A00

H

C00HE00HFFF

H

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel 85°C

(Typical of Each Output Channel)

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

LE (LSB)DLE (LSB)

000H200H400H600H800

H

Digital Input Code

A00

H

C00HE00HFFF

H

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel 25°C

(Typical of Each Output Channel)

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4
–0.5

LE (LSB)DLE (LSB)

10

®

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)

At TA = +25°C, VCC = +15V, VDD = +5V, VSS = –15V, V

REFH

= +10V, V

REFL

= –10V, representative unit, unless otherwise specified.

OUTPUT VOLTAGE vs SETTLING TIME

(+10V to –10V)

Time (2µs/div)

+5V
LDAC
0

Small Signal
Settling Time: 0.5LSB/div

Large Signal
Settling Time: 5V/div

Output Voltage

OUTPUT VOLTAGE vs SETTLING TIME

(–10V to +10V)

Time (2µs/div)

+5V
LDAC
0

Small Signal
Settling Time: 0.5LSB/div

Large Signal
Settling Time: 5V/div

Output Voltage

15

10

5

0

–5

–10

–15

R

LOAD

(kΩ)

0.01

0.1

1 10 100

OUTPUT VOLTAGE vs R

LOAD

V

OUT

(V)

Sink

Source

SUPPLY CURRENT vs CODE

6
5
4
3
2
1

0
–1
–2
–3
–4
–5
–6

Supply Current (mA)

I

DD

I

SS

200H400H600H800HA00HC00HE00HFFF

H

000

H

Digital Input Code

Data = FFFH (all DACs)
No Load

I

CC

7
6
5
4
3
2
1

0
–1
–2
–3
–4
–5
–6
–7

Data = FFFH (all DACs)
No Load

POWER SUPPLY CURRENT vs TEMPERATURE

Quiescent Current (mA)

Temperature (°C)

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

I

CC

I

DD

I

SS

–30 –20 –10 0 10 20 30 40 50 60 70 80 90–40

Temperature (°C)

NEGATIVE FULL-SCALE ERROR vs TEMPERATURE

(Code 000

H

)

Negative Full-Scale Error (mV)

DAC A

DAC B

DAC C

DAC D

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

11

®

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)

At TA = +25°C, VCC = +15V, VDD = +5V, VSS = –15V, V

REFH

= +10V, V

REFL

= –10V, representative unit, unless otherwise specified.

BROADBAND NOISE

Time (1ms/div)

Noise Voltage (500µV/div)

BW = 1MHz

Code = 800

H

OUTPUT VOLTAGE

MID-SCALE GLITCH PERFORMANCE

Time (1µs/div)

+5V
LDAC
0

Output Voltage (200mV/div)

7FFH to 800

H

800H to 7FF

H

–15V

+5V

POWER SUPPLY REJECTION RATIO vs FREQUENCY

Frequency (Hz)

PSRR (dB)

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100

–110

–120

10

2

10

3

10

4

10

5

10

6

10

1

+15V

DUAL SUPPLY CURRENT LIMIT vs INPUT CODE

SHORT TO GROUND

20
15
10

5
0

–5
–10
–15
–20

I

OUT

(mA)

200H400H600H800HA00HC00HE00HFFF

H

000

H

Digital Input Code

Noise at any code

OUTPUT NOISE vs FREQUENCY

Frequency (kHz)

Noise (nV/√Hz)

1000

100

10

0.1 1 10 100 1000 100000

DATA BUS FEEDTHROUGH GLITCH

Time (0.5µs/div)

+5V
DATA BUS
0

Output Voltage (20mV/div)

12

®

DAC7724, 7725

THEORY OF OPERATION

The DAC7724 and DAC7725 are quad voltage output,
12-bit digital-to-analog converters (DACs). The architecture
is a classic R-2R ladder configuration followed by an opera­tional amplifier that serves as a buffer, as shown in Figure 1.
Each DAC has its own R-2R ladder network and output op­amp, but all share the reference voltage inputs. The mini­mum voltage output (“zero-scale”) and maximum voltage

output (“full-scale”) are set by the external voltage refer­ences (V

REFL

and V

REFH

, respectively). The digital input is
a 12-bit parallel word and the DAC input registers offer a
readback capability. The converters can be powered from a
single +15V supply or a dual ±15V supply. Each device
offers a reset function which immediately sets all DAC
registers and DAC output voltages to mid-scale (DAC7724,
code 800H) or to zero-scale (DAC7725, code 000H). See
Figures 2 and 3 for the basic operation of the DAC7724/25.

FIGURE 1. DAC7724/25 Architecture.

FIGURE 2. Basic Single-Supply Operation of the DAC7724/25.

R

2R

2R2R 2R 2R 2R 2R 2R 2R

V

REF

H

V

OUT

RRRRRR

V

REF

L

R

F

1
2
3
4

V

REFH

V

OUTB

Load DAC Registers

Reset DACs

(1)

V

OUTA

V

SS

5 GND
6 RESET
7
8
9

10

11
12
13
14

LDAC
DB0
DB1
DB2
DB3
DB4
DB5
DB6

V

REFL

V

OUTC

DAC7724
DAC7725

V

OUTD

V

CC

28
27
26
25

V

DD

24

CS

23
A0
A1

R/W

DB11

DB10

DB9
DB8
DB7

22

21

20

19
18
17
16
15

Chip Select

Read/Write

Data Bus

Data Bus

Address Bus
or Decoder

+15V

NOTE: (1) Reset LOW sets all DACs to code 800

H

on the DAC7724 and to code 000H on the DAC7725.

0V to +10V

0V to +10V

0V to +10V

0V to +10V

0.1µF 1µF to 10µF

+

+5V

0.1µF

1µF to 10µF

+

+10.00V

0.1µF

13

®

DAC7724, 7725

ANALOG OUTPUTS

When VSS = –15V (dual supply operation), the output
amplifier can swing to within 4V of the supply rails, guar­anteed over the –40°C to +85°C temperature range. With
VSS = 0V (single-supply operation) and R

LOAD

connected to
ground, the output can swing to ground. Note that the
settling time of the output op-amp will be longer with
voltages very near ground. Additionally, care must be taken
when measuring the zero-scale error when VSS = 0V. Since
the output voltage cannot swing below ground, the output
voltage may not change for the first few digital input codes
(000H, 001H, 002H, etc.) if the output amplifier has a nega­tive offset. At the negative offset limit of –4 LSB (-9.76mV),
for the single-supply case, the first specified output starts at
code 004H.

REFERENCE INPUTS

For dual-supply operation, the reference inputs, V

REFL

and

V

REFH

, can be any voltage between V

SS

+ 4V and V

CC

– 4V

provided that V

REFH

is at least 1.25V greater than V

REFL

.

For single-supply operation (VSS = 0V), V

REFL

value can be

above 0V, with the same provision that V

REFH

is at least

1.25V greater than V

REFL

. The minimum output of each

DAC is equal to V

REFL

plus a small offset voltage (essen-

tially, the offset of the output op-amp). The maximum
output is equal to V

REFH

plus a similar offset voltage. Note
that VSS (the negative power supply) must either be con­nected to ground or must be in the range of –14.25V to
–15.75V. The voltage on VSS sets several bias points within
the converter, if VSS is not in one of these two configura­tions, the bias values may be in error and proper operation
of the device is not guaranteed.

The current into the V

REF

H input and out of V

REF

L depends
on the DAC output voltages and can vary from a few
microamps to approximately 0.3mA. The reference input
appears as a varying load to the reference. If the reference
can sink or source the required current, a reference buffer is
not required. See “Reference Current vs Code” in the Typi­cal Performance Curves.

The analog supplies (or the analog supplies and the refer­ence power supplies) have to come up first. If the power
supplies for the references come up first, then the VCC and
VSS supplies will be “powered from the reference via the
ESD protection diodes” (see page 4).

Bypassing the reference voltage or voltages with at least a

0.1uF capacitor placed as close to the DAC7724/25 package
is strongly recommended.

FIGURE 3. Basic Dual-Supply Operation of the DAC7724/25.

1
2
3
4

V

REFH

V

OUTB

Load DAC Registers

Reset DACs

(1)

V

OUTA

V

SS

5 GND
6 RESET
7
8

9
10
11
12
13
14

LDAC
DB0
DB1
DB2
DB3
DB4
DB5
DB6

V

REFL

V

OUTC

DAC7724
DAC7725

V

OUTD

V

CC

28
27
26
25

V

DD

24

CS

23
A0
A1

R/W

DB11

DB10

DB9
DB8
DB7

22

21

20

19
18
17
16
15

Chip Select

–10V to +10V

–10V to +10V

Read/Write

Data Bus

Address Bus
or Decoder

NOTE: (1) Reset LOW sets all DACs to code 800H on the DAC7724 and to code 000H on the DAC7725.

–10.000V

0.1µF

–10V to +10V

–10V to +10V

–15V

+10.000V

0.1µF

0.1µF1µF to 10µF

+

Data Bus

+15V

0.1µF

1µF to 10µF

+

+5V

0.1µF

1µF to 10µF

+

14

®

DAC7724, 7725

V

OUT

= V

REFL

+

V

REFH–VREFL

()

•N

4096

STATE OF

SELECTED SELECTED STATE OF

INPUT INPUT ALL DAC

A1 A0 R/W CS RESET LDAC REGISTER REGISTER REGISTERS

L

(1)

LLLH

(2)

L A Transparent Transparent
L H L L H L B Transparent Transparent
H L L L H L C Transparent Transparent
H H L L H L D Transparent Transparent
LLLLHH A Transparent Latched
L H L L H H B Transparent Latched
H L L L H H C Transparent Latched
H H L L H H D Transparent Latched
L L H L H H A Readback Latched
L H H L H H B Readback Latched
H L H L H H C Readback Latched
H H H L H H D Readback Latched

X

(3)

X X H H L NONE (All Latched) Transparent
X X X H H H NONE (All Latched) Latched
XXXXL X ALL Reset

(4)

Reset

(4)

NOTES: (1) L = Logic LOW. (2) H= Logic HIGH. (3) X = Don’t Care. (4) DAC7724 resets to 800H, DAC7725 resets to 000H. When RESET rises, all registers
that are in their latched state retain the reset value.

TABLE I. DAC7724 and DAC7725 Control Logic Truth Table.

DIGITAL INTERFACE

Table I shows the basic control logic for the DAC7724/25.
Note that each internal register is level triggered and not
edge triggered. When the appropriate signal is LOW, the
register becomes transparent. When this signal is returned
HIGH, the digital word currently in the register is latched.
The first set of registers (the Input Registers) are triggered
via the A0, A1, R/W, and CS inputs. Only one of these
registers is transparent at any given time. The second set of
registers (the DAC Registers) are all transparent when LDAC
input is pulled LOW.

Each DAC can be updated independently by writing to the
appropriate Input Register and then updating the DAC
Register. Alternatively, the entire DAC Register set can be
configured as always transparent by keeping LDAC LOW—
the DAC update will occur when the Input Register is
written.

The double buffered architecture is mainly designed so that
each DAC Input Register can be written at any time and then
all DAC output voltages updated simultaneously by pulling
LDAC LOW. It also allows a DAC Input Register to be
written to at any point and the DAC voltage to be synchro­nously changed via a trigger signal connected to LDAC.

DIGITAL TIMING

Figure 4 and Table II provide detailed timing for the digital
interface of the DAC7724 and DAC7725.

DIGITAL INPUT CODING

The DAC7724 and DAC7725 input data is in straight binary
format. The output voltage is given by the following equa­tion:

where N is the digital input code. This equation does not
include the effects of offset (zero-scale) errors.

15

®

DAC7724, 7725

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

RCS

CS LOW for Read 200 ns

t

RDS

R/W HIGH to CS LOW 10 ns

t

RDH

R/W HIGH after CS HIGH 10 ns

t

DZ

CS HIGH to Data Bus in High Impedance 100 ns

t

CSD

CS LOW to Data Bus Valid 100 160 ns

t

WCS

CS LOW for Write 50 ns

t

WS

R/W LOW to CS LOW 0 ns

t

WH

R/W LOW after CS HIGH 0 ns

t

AS

Address Valid to CS LOW 0 ns

t

AH

Address Valid after CS HIGH 0 ns

t

LD

LDAC Delay from CS HIGH 10 ns

t

DS

Data Valid to CS LOW 0 ns

t

DH

Data Valid after CS HIGH 0 ns

t

LWD

LDAC LOW 50 ns

t

RESET

RESET LOW Time 50 ns

t

S

Settling Time 10 µs

TABLE II. Timing Specifications (TA = –40°C to +85°C).

FIGURE 4. Digital Input and Output Timing.

t

RCS

CS

t

RDS

t

RDH

t

AS

t

CSD

t

DZ

t

AH

R/W

A0/A1

Data Out

Data Valid

Data Read Timing

±0.012% of FSR

Error Band

±0.012% of FSR

Error Band

Mid-Scale

RESET

V

OUT

, DAC7725

+FS

–FS

V

OUT

, DAC7724

+FS

–FS

DAC7724/25 Reset Timing

t

RESET

t

S

t

WCS

CS

t

WS

t

AS

t

AH

t

WH

R/W

A0/A1

t

S

±0.012% of FSR

Error Band

±0.012% of FSR

Error Band

LDAC

t

DS

t

DH

Data In

V

OUT

Data Write Timing

t

LWD

t

LD