Datasheet DAC7615PB, DAC7615P, DAC7615EB-1K, DAC7615EB, DAC7615E-1K Datasheet (Burr Brown Corporation)

DAC7615

®

© 1998 Burr-Brown Corporation PDS-1443C Printed in U.S.A. November, 1998

Quad, Serial Input, 12-Bit, Voltage Output

DIGITAL-TO-ANALOG CONVERTER

FEATURES

● LOW POWER: 20mW

● UNIPOLAR OR BIPOLAR OPERATION

● SETTLING TIME: 10µs to 0.012%

● 12-BIT LINEARITY AND MONOTONICITY:

–40°C to +85°C

● DOUBLE-BUFFERED DATA INPUTS

● SMALL 20-LEAD SSOP PACKAGE

APPLICATIONS

● PROCESS CONTROL

● ATE PIN ELECTRONICS

● CLOSED-LOOP SERVO-CONTROL

● MOTOR CONTROL

● DATA ACQUISITION SYSTEMS

● DAC-PER-PIN PROGRAMMERS

DESCRIPTION

The DAC7615 is a quad, serial input, 12-bit, voltage
output digital-to-analog converter (DAC) with guar­anteed 12-bit monotonic performance over the –40°C
to +85°C temperature range. An asynchronous reset
clears all registers to either mid-scale (800H) or zero­scale (000H), selectable via the RESETSEL pin. The
individual DAC inputs are double buffered to allow

for simultaneous update of all DAC outputs. The
device can be powered from a single +5V supply or
from dual +5V and –5V supplies.

Low power and small size makes the DAC7615 ideal
for automatic test equipment, DAC-per-pin program­mers, data acquisition systems, and closed-loop servo­control. The device is available in 16-pin plastic DIP,
16-lead SOIC, and 20-lead SSOP packages and is
guaranteed over the –40°C to +85°C temperature range.

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone] • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: [phone] (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

DAC A

DAC

Register A

Input

Register A

DAC B

DAC

Register B

Input

Register B

DAC C

DAC

Register C

Input

Register C

DAC D

DAC

Register D

Input

Register D

V

REFH

V

DD

V

SS

V

OUTD

V

OUTC

V

OUTB

V

OUTA

V

REFLLOADDACS

GND

CLK

CS

12

SDI

RESETRESETSELLOADREG

Serial-to-

Parallel

Shift

Register

DAC

Select

DAC7615

DAC7615

®

2

DAC7615

SPECIFICATIONS

At TA = –40°C to +85°C, VDD = +5V, VSS = –5V, V

REFH

= +2.5V, and V

REFL

= –2.5V, unless otherwise noted.

DAC7615E, P, U DAC7615EB, PB, UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY

Linearity Error

(1)

VSS = 0V or –5V ±2 ±1 LSB

(2)

Linearity Matching

(3)

VSS = 0V or –5V ±2 ±1 LSB

Differential Linearity Error V

SS

= 0V or –5V ±1 ±1 LSB
Monotonicity 12 ✻ Bits
Zero-Scale Error Code = 000

H

±4 ✻ LSB
Zero-Scale Drift 25 ✻✻ppm/°C
Zero-Scale Matching

(3)

±2 ±1 LSB
Full-Scale Error Code = FFF

H

±4 ✻ LSB
Full-Scale Matching

(3)

±2 ±1 LSB
Zero-Scale Error Code = 00A

H

, VSS = 0V ±8 ✻ LSB

Zero-Scale Drift V

SS

= 0V 5 10 ✻✻ppm/°C

Zero-Scale Matching

(3)

VSS = 0V ±4 ±2 LSB

Full-Scale Error Code = FFF

H

, VSS = 0V ±8 ✻ LSB

Full-Scale Matching

(3)

VSS = 0V ±4 ±2 LSB

Power Supply Rejection 30 ✻ ppm/V

ANALOG OUTPUT

Voltage Output

(4)

VSS = 0V or –5V V

REFL

V

REFH

✻✻V
Output Current –1.25 +1.25 ✻✻mA
Load Capacitance No Oscillation 100 ✻ pF
Short-Circuit Current +5, –15 ✻ mA
Short-Circuit Duration

Indefinite

✻

REFERENCE INPUT

V

REFH

Input Range VSS = 0V or –5V

V

REFL

+1.25

+2.5 ✻✻V

V

REFL

Input Range VSS = 0V 0

V

REFH

–1.25

✻✻V
V

REFL

Input Range VSS = –5V –2.5

V

REFH

–1.25

✻✻V

DYNAMIC PERFORMANCE

Settling Time

(5)

To ±0.012% 5 10 ✻✻ µs

Channel-to-Channel Crosstalk Full-Scale Step 0.1 ✻ LSB

On Any Other DAC, RL = 2kΩ

Output Noise Voltage Bandwidth: 0Hz to 1MHz 40 ✻ nV/√Hz

DIGITAL INPUT/OUTPUT

Logic Family TTL-Compatible CMOS ✻
Logic Levels

V

IH

| I

IH

| ≤ 10µA 2.4 VDD+0.3 ✻✻V

V

IL

| I

IL

| ≤ 10µA –0.3 0.8 ✻✻V

Data Format Straight Binary ✻

POWER SUPPLY REQUIREMENTS

V

DD

4.75 5.25 ✻✻V

V

SS

If VSS ≠ 0V –5.25 –4.75 ✻✻V

I

DD

1.5 1.9 ✻✻ mA

I

SS

–2.1 –1.6 ✻✻ mA

Power Dissipation V

SS

= –5V 15 20 ✻✻ mW

V

SS

= 0V 7.5 10 ✻✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

✻ Specification same as grade to the left.
NOTES: (1) If V

SS

= 0V, specification applies at code 00AH and above. (2) LSB means Least Significant Bit, with V

REFH

equal to +2.5V and V

REFL

equal to –2.5V,
one LSB is 1.22mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error.
(5) If V

SS

= –5V, full-scale step from code 000H to FFFH or vice-versa. If VSS = 0V, full-scale positive step from code 000H to FFFH and negative step from code

FFF

H

to 00AH.

3

®

DAC7615

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

ABSOLUTE MAXIMUM RATINGS

(1)

VDD to VSS........................................................................... –0.3V to +11V

VDD to GND ........................................................................ –0.3V to +5.5V

V

REFL

to VSS...............................................................–0.3V to (VDD – VSS)

VDD to V

REFH

..............................................................–0.3V to (VDD – VSS)

V

REFH

to V

REFL

............................................................–0.3V to (VDD – VSS)

Digital Input Voltage to GND...................................... –0.3V to V

DD

+ 0.3V

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ......................................... –40°C to +85°C

Storage Temperature Range .......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION

MAXIMUM MAXIMUM

LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION

ERROR LINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT

PRODUCT (LSB) (LSB) PACKAGE NUMBER

(1)

RANGE NUMBER

(2)

MEDIA

DAC7615P ±2 ±1 16-Pin DIP 180 –40°C to +85°C DAC7615P Rails
DAC7615PB

"""""DAC7615PB Rails

DAC7615U ±2 ±1 16-Lead SOIC 211 –40°C to +85°C DAC7615U Rails

"" """ "DAC7615U/1K Tape and Reel

DAC7615UB ±1 ±1 16-Lead SOIC 211 –40°C to +85°C DAC7615UB Rails

"" """ "DAC7615UB/1K Tape and Reel

DAC7615E ±2 ±1 20-Lead SSOP 334 –40°C to +85°C DAC7615E Rails

"" """ "DAC7615E/1K Tape and Reel

DAC7615EB ±1 ±1 20-Lead SSOP 334 –40°C to +85°C DAC7615EB Rails

"" """ "DAC7615EB/1K Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7615EB/1K” will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

®

4

DAC7615

PIN CONFIGURATION—P, U Packages

Top View PDIP, SOIC

PIN CONFIGURATION—E Package

Top View SSOP

PIN DESCRIPTIONS—E Package

PIN LABEL DESCRIPTION

1VDDPositive Analog Supply Voltage, +5V nominal.
2V

OUTD

DAC D Voltage Output

3V

OUTC

DAC C Voltage Output

4V

REFL

Reference Input Voltage Low. Sets minimum out-

put voltage for all DACs.
5 NIC Not Internally Connected.
6 NIC Not Internally Connected.
7V

REFH

Reference Input Voltage High. Sets maximum out-

put voltage for all DACs.
8V

OUTB

DAC B Voltage Output
9V

OUTA

DAC A Voltage Output
10 V

SS

Negative Analog Supply Voltage, 0V or –5V nomi-

nal.
11 GND Ground
12 SDI Serial Data Input
13 CLK Serial Data Clock
14 CS Chip Select Input
15 NIC Not Internally Connected.
16 NIC Not Internally Connected.
17 LOADDACS All DAC registers becomes transparent when

LOADDACS is LOW. They are in the latched state

when LOADDACS is HIGH.
18 LOADREG The selected input register becomes transparent

when LOADREG is LOW. It is in the latched state

when LOADREG is HIGH.
19 RESET Asynchronous Reset Input. Sets all DAC registers

to either zero-scale (000

H

) or mid-scale (800H)
when LOW. RESETSEL determines which code is
active.

20 RESETSEL When LOW, a LOW on RESET will cause all DAC

registers to be set to code 000

H

. When RESETSEL
is HIGH, a LOW on RESET will set the registers to
code 800

H

.

PIN DESCRIPTIONS—P, U Packages

PIN LABEL DESCRIPTION

1VDDPositive Analog Supply Voltage, +5V nominal.
2V

OUTD

DAC D Voltage Output

3V

OUTC

DAC C Voltage Output

4V

REFL

Reference Input Voltage Low. Sets minimum out­put voltage for all DACs.

5V

REFH

Reference Input Voltage High. Sets maximum out­put voltage for all DACs.

6V

OUTB

DAC B Voltage Output

7V

OUTA

DAC A Voltage Output

8V

SS

Negative Analog Supply Voltage, 0V or –5V nomi-

nal.
9 GND Ground
10 SDI Serial Data Input
11 CLK Serial Data Clock
12 CS Chip Select Input
13 LOADDACS All DAC registers become transparent when

LOADDACS is LOW. They are in the latched state

when LOADDACS is HIGH.
14 LOADREG The selected input register becomes transparent

when LOADREG is LOW. It is in the latched state

when LOADREG is HIGH.
15 RESET Asynchronous Reset Input. Sets DAC and input

registers to either zero-scale (000

H

) or mid-scale

(800

H

) when LOW. RESETSEL determines which

code is active.
16 RESETSEL When LOW, a LOW on RESET will cause the DAC

and input registers to be set to code 000

H

. When
RESETSEL is HIGH, a LOW on RESET will set the
registers to code 800

H

.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

DD

V

OUTD

V

OUTC

V

REFL

V

REFH

V

OUTB

V

OUTA

V

SS

RESETSEL
RESET
LOADREG
LOADDACS
CS
CLK
SDI
GND

DAC7615P, U

1
2
3
4
5
6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

V

DD

V

OUTD

V

OUTC

V

REFL

NIC
NIC

V

REFH

V

OUTB

V

OUTA

V

SS

RESETSEL
RESET
LOADREG
LOADDACS
NIC
NIC
CS
CLK
SDI
GND

DAC7615E

5

®

DAC7615

TYPICAL PERFORMANCE CURVES: VSS = 0V

At TA = +25°C, VDD = +5V, VSS = 0V, V

REFH

= +2.5V, and V

REFL

= 0V, representative unit, unless otherwise specified.

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A)

200

H

000

H

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B)

000

H

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C)

000

H

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR and DIFFERENTIAL

LINEARITY ERROR vs CODE

(DAC D)

000

H

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR vs CODE

(DAC A, –40°C and +85°C)

000

H

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

+85°C

–40°C

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR vs CODE

(DAC B, –40°C and +85°C)

000

H

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

+85°C

–40°C

200H400H600H800HA00HC00HE00HFFF

H

®

6

DAC7615

TYPICAL PERFORMANCE CURVES: VSS = 0V (CONT)

At TA = +25°C, VDD = +5V, VSS = 0V, V

REFH

= +2.5V, and V

REFL

= 0V, representative unit, unless otherwise specified.

LINEARITY ERROR vs CODE

(DAC C, –40°C and +85°C)

000

H

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

+85°C

–40°C

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR vs CODE

(DAC D, –40°C and +85°C)

000

H

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

+85°C

–40°C

200H400H600H800HA00HC00HE00HFFF

H

POSITIVE SLEW RATE and SETTLING TIME

–2 8–1

Time (µs)

A: Output Voltage (V)

B: Output Voltage, Deviation from +2.5V (LSB)

–0.25

2.25

1.75

2.75

1.25

0.75

0.25

–9

6

3

9

0

–3

–6

0 1 2 3 4 5 6 7

0V

5V

LOADDACS

A

B

NEGATIVE SLEW RATE and SETTLING TIME

–2 8–1

Time (µs)

A: Output Voltage (V)

B: Output Voltage, Deviation from Code 00A

H

(LSB)

–0.25

2.25

1.75

2.75

1.25

0.75

0.25

–9

6

3

9

0

–3

–6

0 1 2 3 4 5 6 7

0V

5V

LOADDACS

AB

7

®

DAC7615

TYPICAL PERFORMANCE CURVES: VSS = –5V

At TA = +25°C, VDD = +5V, VSS = –5V, V

REFH

= +2.5V, and V

REFL

= –2.5V, representative unit, unless otherwise specified.

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A)

000

H

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C)

000

H

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00

–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B)

000

H

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC D)

000

H

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR vs CODE

(DAC A, –40°C and +85°C)

000

H

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

+85°C

–40°C

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

H

LINEARITY ERROR vs CODE

(DAC B, –40°C and +85°C)

000

H

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

+85°C

–40°C

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

H

®

8

DAC7615

TYPICAL PERFORMANCE CURVES: VSS = –5V (CONT)

At TA = +25°C, VDD = +5V, VSS = –5V, V

REFH

= +2.5V, and V

REFL

= –2.5V, representative unit, unless otherwise specified.

LINEARITY ERROR vs CODE

(DAC C, –40°C and +85°C)

200

H

000

H

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

+85°C

–40°C

0.25

0.00

–0.50

–0.25

0.25

400H600H800HA00HC00HE00HFFF

H

600

V

REFH

CURRENT vs CODE

(All DACs Set to Indicated Code)

000

H

FFF

H

400

H

C00

H

800

H

Digital Input Code

V

REH

Current (µA)

0

100

200

300

400

500

0

V

REFL

CURRENT vs CODE

(All DACs Set to Indicated Code)

000

H

FFF

H

400

H

C00

H

800

H

Digital Input Code

V

REL

Current (µA)

–600

–500

–400

–300

–200

–100

POSITIVE SLEW RATE and SETTLING TIME

–2 8–1

Time (µs)

A: Output Voltage (V)

B: Output Voltage, Deviation from +2.5V (LSB)

–3

2

1

3

0

–1

–2

–6

4

2

6

0

–2

–4

0 1 2 3 4 5 6 7

0V

5V

LOADDACS

A

B

NEGATIVE SLEW RATE and SETTLING TIME

–2 8–1

Time (µs)

A: Output Voltage (V)

B: Output Voltage, Deviation from –2.5V (LSB)

–3

2

1

3

0

–1

–2

–6

4

2

6

0

–2

–4

0 1 2 3 4 5 6 7

0V

5V

LOADDACS

A

B

LINEARITY ERROR vs CODE

(DAC D, –40˚C and +85˚C)

000

H

200

H

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00
–0.25
–0.50

0.50

+85˚C

–40˚C

0.25

0.00

–0.50

–0.25

0.25

400H600H800HA00HC00HE00HFFF

H

9

®

DAC7615

THEORY OF OPERATION

The DAC7615 is a quad, serial input, 12-bit, voltage output
DAC. The architecture is a classic R-2R ladder configuration
followed by an operational amplifier that serves as a buffer.
Each DAC has its own R-2R ladder network and output op
amp, but all share the reference voltage inputs. The minimum
voltage output (“zero-scale”) and maximum voltage output
(“full-scale”) are set by external voltage references (V

REFL

and V

REFH

, respectively). The digital input is a 16-bit serial
word that contains the 12-bit DAC code and a 2-bit address
code that selects one of the four DACs (the two remaining
bits are unused). The converter can be powered from a single
+5V supply or a dual ±5V supply. Each device offers a reset
function which immediately sets all DAC output voltages and
internal registers to either zero-scale (code 000H) or mid-scale
(code 800H). The reset code is selected by the state of the
RESETSEL pin (LOW = 000H, HIGH = 800H). See Figures
1 and 2 for the basic operation of the DAC7615.

ANALOG OUTPUTS

When VSS = –5V (dual supply operation), the output
amplifier can swing to within 2.25V of the supply rails,
over the –40°C to +85°C temperature range. With VSS = 0V
(single-supply operation), the output can swing to ground.
Note that the settling time of the output op amp will be
longer with voltages very near ground. Also, care must be
taken when measuring the zero-scale error when VSS = 0V.
If the output amplifier has a negative offset, the output
voltage may not change for the first few digital input codes
(000H, 001H, 002H, etc.) since the output voltage cannot
swing below ground.

The behavior of the output amplifier can be critical in some
applications. Under short-circuit conditions (DAC output
shorted to ground), the output amplifier can sink a great deal
more current than it can source. See the Specifications table
for more details concerning short circuit current.

FIGURE 1. Basic Single-Supply Operation of the DAC7615.

FIGURE 2. Basic Dual-Supply Operation of the DAC7615.

NOTE: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal registers
to code 000

H

(0V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800H (1.25V).

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

DD

V

OUTD

V

OUTC

V

REFL

V

REFH

V

OUTB

V

OUTA

V

SS

RESETSEL

RESET

LOADREG

LOADDACS

CS

CLK

SDI

GND

Reset DACs

(2)

Update Selected Register
Update All DAC Registers
Chip Select
Clock
Serial Data In

DAC7615

(1)

0.1µF

0.1µF

0V to +2.5V

1µF to 10µF

+5V

+

0V to +2.5V

0V to +2.5V
0V to +2.5V

+2.500V

NOTE: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal registers
to code 800

H

(0V). If RESETSEL is LOW, RESET LOW sets all internal registers to code 000H (–2.5V).

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

DD

V

OUTD

V

OUTC

V

REFL

V

REFH

V

OUTB

V

OUTA

V

SS

RESETSEL

RESET

LOADREG

LOADDACS

CS

CLK

SDI

GND

Reset DACs

(2)

Update Selected Register
Update All DAC Registers
Chip Select
Clock
Serial Data In

DAC7615

(1)

0.1µF

0.1µF

–2.5V to +2.5V

1µF to 10µF

+5V

–5V

+

0.1µF

1µF to 10µF

+

–2.5V to +2.5V

–2.500V

0.1µF

+2.500V

–2.5V to +2.5V
–2.5V to +2.5V

+5V

®

10

DAC7615

REFERENCE INPUTS

The reference inputs, V

REFL

and V

REFH

, can be any voltage

between V

SS

+ 2.25V and V

DD

– 2.25V provided that V

REFH

is at least 1.25V greater than V

REFL

. The minimum output

of each DAC is equal to V

REFL

– 1LSB plus a small offset
voltage (essentially, the offset of the output op amp). The
maximum output is equal to V

REFH

plus a similar offset
voltage. Note that VSS (the negative power supply) must
either be connected to ground or must be in the range of –

4.75V to –5.25V. The voltage on VSS sets several bias
points within the converter. If VSS is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not guaranteed.

The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 0.6 milliamp. Bypassing the reference volt­age or voltages with a 0.1µF capacitor placed as close as
possible to the DAC7615 package is strongly recommended.

DIGITAL INTERFACE

Figure 3 and Table I provide the basic timing for the
DAC7615. The interface consists of a serial clock (CLK),
serial data (SDI), a load register signal (LOADREG), and a
“load all DAC registers” signal (LOADDACS). In addition,
a chip select (CS) input is available to enable serial commu­nication when there are multiple serial devices. An asyn-

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

DS

Data Valid to CLK Rising

25 ns

t

DH

Data Held Valid after CLK Rises

20 ns

t

CH

CLK HIGH

30 ns

t

CL

CLK LOW

50 ns

t

CSS

CS LOW to CLK Rising

55 ns

t

CSH

CLK HIGH to CS Rising

15 ns

t

LD1

LOADREG HIGH to CLK Rising

40 ns

t

LD2

CLK Rising to LOADREG LOW

15 ns

t

LDRW

LOADREG LOW Time

45 ns

t

LDDW

LOADDACS LOW Time

45 ns

t

RSSH

RESETSEL Valid to RESET LOW

25 ns

t

RSTW

RESET LOW Time

70 ns

t

S

Settling Time

10 µs

FIGURE 3. DAC7615 Timing.

chronous reset input (RESET) is provided to simplify start­up conditions, periodic resets, or emergency resets to a
known state.

The DAC code and address are provided via a 16-bit serial
interface as shown in Figure 3. The first two bits select the
input register that will be updated when LOADREG goes
LOW (see Table II). The next two bits are not used. The last
12 bits are the DAC code which is provided, most significant
bit first.

TABLE I. Timing Specifications (TA = –40°C to +85°C).

A1

(MSB) (LSB)

SDI

CLK

CS

LOADREG

A0 X X D11 D10 D9 D3 D2 D1 D0

SDI

CLK

LOADDACS

RESET

V

OUT

t

css

t

LD1

t

CL

t

CH

t

DS

t

DH

t

LD2

t

LDRW

t

LDDW

t

S

t

RSTW

t

RSSH

t

CSH

t

S

1 LSB
ERROR BAND

1 LSB
ERROR BAND

RESETSEL

11

®

DAC7615

STATE OF

SELECTED SELECTED STATE OF

INPUT INPUT ALL DAC

A1 A0 LOADREG LOADDACS RESET REGISTER REGISTER REGISTERS

L

(1)

LLH

(2)

H A Transparent Latched

L H L H H B Transparent Latched
H L L H H C Transparent Latched
H H L H H D Transparent Latched

X

(3)

X H L H NONE (All Latched) Transparent
X X H H H NONE (All Latched) Latched
X X X X L ALL Reset

(4)

Reset

(4)

NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care. (4) Resets to either 000H or 800H, per the RESETSEL state (LOW = 000H, HIGH = 800H).
When RESET rises, all registers that are in their latched state retain the reset value.

TABLE II. Control Logic Truth Table.

CS

(1)

CLK

(1)

LOADREG RESET SERIAL SHIFT REGISTER

H

(2)

X

(3)

H H No Change

L

(4)

L H H No Change

L ↑

(5)

H H Advanced One Bit

↑ L H H Advanced One Bit

H

(6)

XL

(7)

H No Change

H

(6)

XHL

(8)

No Change

NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =
Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH
value is suggested in order to avoid a “false clock” from advancing the shift
register and changing the shift register. (7) If data is clocked into the serial
register while LOADREG is LOW, the selected input register will change as the
shift register bits “flow” through A1 and A0. This will corrupt the data in each
input register that has been erroneously selected. (8) RESET LOW causes no
change in the contents of the serial shift register.

TABLE III. Serial Shift Register Truth Table.

If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.

The digital data into the DAC7615 is double-buffered. This
allows new data to be entered for each DAC without disturb­ing the analog outputs. When the new settings have been
entered into the device, all of the DAC outputs can be
updated simultaneously. The transfer from the input regis­ters to the DAC registers is accomplished with a HIGH to
LOW transition on the LOADDACS input.

Because the DAC registers become transparent when
LOADDACS is LOW, it is possible to keep this pin LOW
and update each DAC via LOADREG. However, as each
new data word is entered into the device, the corresponding
output will update immediately when LOADREG is taken
LOW.

Digital Input Coding

The DAC7615 input data is in Straight Binary format. The
output voltage is given by the following equation:

Note that CS and CLK are combined with an OR gate and
the output controls the serial-to-parallel shift register inter­nal to the DAC7615 (see the block diagram on the front of
this data sheet). These two inputs are completely inter­changeable. In addition, care must be taken with the state of
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong input register. where N is the digital input code (in decimal). This equation

does not include the effects of offset (zero-scale) or gain
(full-scale) errors.

(V

REFH

– V

REFL

) • N

4096

V

OUT

= V

REFL

+

®

12

DAC7615

LAYOUT

A precision analog component requires careful layout, ad­equate bypassing, and clean, well-regulated power supplies.
As the DAC7615 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch­ing speed, the more difficult it will be to achieve good
performance from the converter.

Because the DAC7615 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through the GND pin. Ideally, GND would be con­nected directly to an analog ground plane. This plane would
be separate from the ground connection for the digital
components until they were connected at the power entry
point of the system (see Figure 4).

The power applied to VDD (as well as VSS, if not grounded)
should be well regulated and low noise. Switching power
supplies and DC/DC converters will often have high-fre­quency glitches or spikes riding on the output voltage. In
addition, digital components can create similar high-fre­quency spikes as their internal logic switches states. This
noise can easily couple into the DAC output voltage through
various paths between the power connections and analog
output.

As with the GND connection, VDD should be connected to
a +5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 1µF to 10µF and 0.1µF
capacitors shown in Figure 4 are strongly recommended. In
some situations, additional bypassing may be required, such
as a 100µF electrolytic capacitor or even a “Pi” filter made
up of inductors and capacitors—all designed to essentially
lowpass filter the +5V supply, removing the high frequency
noise (see Figure 4).

FIGURE 4. Suggested Power and Ground Connections for a DAC7615 Sharing a +5V Supply with a Digital System.

+5V

Power Supply

Optional

Digital Circuits

DAC7615

Other

Analog

Components

+5V

100µF

1µF to

10µF

Ground

+5V

Ground

V

DD

GND

0.1µF

++