Datasheet DAC7545LU, DAC7545LP, DAC7545KU, DAC7545KP, DAC7545JU Datasheet (Burr Brown Corporation)

1

DAC7545

CMOS 12-Bit Multiplying

DIGITAL-TO-ANALOG CONVERTER

Microprocessor Compatible

FEATURES

● FOUR-QUADRANT MULTIPLICATION

● LOW GAIN TC: 2ppm/

°C typ

● MONOTONICITY GUARANTEED OVER

TEMPERATURE

● SINGLE 5V TO 15V SUPPLY

● TTL/CMOS LOGIC COMPATIBLE

● LOW OUTPUT LEAKAGE: 10nA max

● LOW OUTPUT CAPACITANCE: 70pF max

● DIRECT REPLACEMENT FOR AD7545,

PM-7545

DESCRIPTION

The DAC7545 is a low-cost CMOS, 12-bit four­quadrant multiplying, digital-to-analog converter with
input data latches. The input data is loaded into the
DAC as a 12-bit data word. The data flows through to
the DAC when both the chip select (CS) and the write
(WR) pins are at a logic low.

Laser-trimmed thin-film resistors and excellent CMOS
voltage switches provide true 12-bit integral and dif­ferential linearity. The device operates on a single
+5V to +15V supply and is available in 20-pin plastic
DIP or 20-lead plastic SOIC packages. Devices are
specified over the commercial.

The DAC7545 is well suited for battery or other low
power applications because the power dissipation is
less than 0.5mW when used with CMOS logic inputs
and V

DD

= +5V.

12-Bit

Multiplying DAC

AGND

OUT 1

DB

11

-DB

0

(

Pins 4-15

)

WR

CS

17

Input

Data Latches

12

12

16

19

V

REF

20

R

FB

1

2

18

3

V

DD

DGND

DAC7545

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone] • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: [phone] (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

©

1987 Burr-Brown Corporation PDS-747F Printed in U.S.A. August, 1997

DAC7545

DAC7545

2

DAC7545

SPECIFICATIONS

ELECTRICAL

V

REF

= +10V, V

OUT 1

= 0V, ACOM = DCOM, unless otherwise specified.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

NOTES: (1) Temperature ranges—J, K, L, GL: –40°C to +85°C. (2) This includes the effect of 5ppm max, gain TC. (3) Guaranteed but not tested. (4) DB0-DB11 = 0V
to V

DD

or VDD to 0V. (5) Typical. (6) Minimum. (7) Logic inputs are MOS gates. Typical input current (+25°C) is less than 1nA. (8) Sample tested at +25°C to ensure

compliance.

DAC7545

V

DD

= +5V V

DD

= +15V

PARAMETER GRADE T

A

= +25°CT

MAX-TMIN

(1)

TA = +25°CT

MAX-TMIN

(1)

UNITS TEST CONDITIONS/COMMENTS

STATIC PERFORMANCE

Resolution All 12 12 12 12 Bits
Accuracy J ±2 ±2 ±2 ±2 LSB

K ±1 ±1 ±1 ±1 LSB

L ±1/2 ±1/2 ±1/2 ±1/2 LSB

GL ±1/2 ±1/2 ±1/2 ±1/2 LSB

Differential Nonlinearity J ±4 ±4 ±4 ±4 LSB 10-Bit Monotonic, T

MIN

to T

MAX

K ±1 ±1 ±1 ±1 LSB 10-Bit Monotonic, T

MIN

to T

MAX

L ±1 ±1 ±1 ±1 LSB 12-Bit Monotonic, T

MIN

to T

MAX

GL ±1 ±1 ±1 ±1 LSB 12-Bit Monotonic, T

MIN

to T

MAX

Gain Error (with internal RFB)

(2)

J ±20 ±20 ±25 ±25 LSB D/A register loaded with FFFH.

K ±10 ±10 ±15 ±15 LSB Gain error is adjustable using

L ±5 ±6 ±10 ±10 LSB the circuits in Figures 2 and 3.

GL ±2 ±3 ±6 ±7 LSB

Gain Temperature Coefficient

(3)

(∆Gain/∆Temperature) All ±5 ±5 ±10 ±10 ppm/°C Typical value is 2ppm/°C

for V

DD

= +5

DC Supply Rejection

(3)

(∆Gain/∆VDD) All 0.015 0.03 0.01 0.02 %/% ∆VDD ±5%

Output Leakage Current at Out 1 J, K, L, GL 10 50 10 50 nA DB

0

-DB11 = 0V; WR, CS = 0V

DYNAMIC PERFORMANCE

Current Settling Time

(3)

All2222µs To 1/2LSB. Out1 Load = 100Ω

DAC output measured from
falling edge of WR. CS = 0V

Propagation Delay

(3)

(from digital input All

change to 90% of final analog output) 300 250 ns Out

1

Load = 100Ω. C

EXT

= 13pF

(4)

Glitch Energy All 400 250 nV-s

(5)

V

REF

= ACOM

AC Feedback at I

OUT

1 All 5 5 5 5 mVp-p

(5)

V

REF

= ±10V, 10kHz Sine Wave

REFERENCE INPUT

Input Resistance (pin 19 to AGND) All 7 7 7 7 kΩ

(6)

Input resistance TC = 300ppm/°C

(5)

25 25 25 25 kΩ

AC OUTPUTS

Output Capacitance

(3)

: C

OUT 1

All 70 70 70 70 pF DB0-DB11 = 0V; WR, CS = 0V

C

OUT 2

All 200 200 200 200 pF DB0-DB11 = VDD; WR, CS = 0V

DIGITAL INPUTS

V

IH

(Input HIGH Voltage) All 2.4 2.4 13.5 13.5 V

(6)

VIL (Input LOW Voltage) All 0.8 0.8 1.5 1.5 V
I

IN

(Input Current)

(7)

All ±1 ±10 ±1 ±10 µAVIN = 0 or V

DD

Input Capacitance

(3)

: DB0-DB

11

All5555pFV

IN

= 0V

WR, CS All 20 20 20 20 pF V

IN

= 0V

SWITCHING CHARACTERISTICS

(8)

Chip Select to Write Setup Time, t

CS

All 280 380 180 200 ns

(6)

See Timing Diagram

200 270 120 150 ns

(5)

Chip Select to Write Hold Time, t

CH

All0000ns

(6)

Write Pulse Width, t

WR

All 250 400 160 240 ns

(6)

tCS ≥ tWR, tCH ≥ 0

175 280 100 170 ns

(5)

Data Setup Time, t

DS

All 140 210 90 120 ns

(6)

100 150 60 80 ns

(5)

Data Hold Time, t

DH

All 10 10 10 10 ns

(6)

POWER SUPPLY, I

DD

All 2 2 2 2 mA All Digital Inputs VIL or V

IH

All 100 500 100 500 µA All Digital Inputs 0V or V

DD

All 10 10 10 10 µA

(5)

All Digital Inputs 0V or V

DD

3

DAC7545

TEMPERATURE RELATIVE GAIN ERROR (LSB)

PRODUCT PACKAGE RANGE ACCURACY (LSB) V

DD

= +5V

DAC7545JP Plastic DIP –40°C to +85°C ±2 ±20
DAC7545KP Plastic DIP –40°C to +85°C ±1 ±10
DAC7545LP Plastic DIP –40°C to +85°C ±1/2 ±5
DAC7545GLP Plastic DIP –40°C to +85°C ±1/2 ±2

DAC7545JU Plastic SOIC –40°C to +85°C ±2 ±20
DAC7545KU Plastic SOIC –40°C to +85°C ±1 ±10
DAC7545LU Plastic SOIC –40°C to +85°C ±1/2 ±5
DAC7545GLU Plastic SOIC –40°C to +85°C ±1/2 ±2

PACKAGE DRAWING

PRODUCT PACKAGE NUMBER

(1)

DAC7545JP 20-Pin PDIP 222
DAC7545KP 20-Pin PDIP 222
DAC7545LP 20-Pin PDIP 222
DAC7545GLP 20-Pin PDIP 222

DAC7545JU 20-Pin SOIC 221
DAC7545KU 20-Pin SOIC 221
DAC7545LU 20-Pin SOIC 221
DAC7545GLU 20-Pin SOIC 221

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

ABSOLUTE MAXIMUM RATINGS

(1)

TA = +25°C, unless otherwise noted.

V

DD

to DGND ........................................................................... –0.3V, +17

Digital Input to DGND ...............................................................–0.3V, V

DD

V

RFB

, V

REF

, to DGND ........................................................................ ±25V

V

PIN 1

to DGND ......................................................................... –0.3V, V

DD

AGND to DGND ........................................................................–0.3V, V

DD

Power Dissipation: Any Package to +75°C .................................... 450mW

Derates above +75°C by ................................ 6mW/°C

Operating Temperature:

Commercial J, K, L, GL .................................................. –40°C to +85°C

Storage Temperature...................................................... –65°C to +150°C

Lead Temperature (soldering, 10s)................................................ +300°C

NOTE: (1) Stresses above those listed above may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

PIN CONNECTIONS

ELECTROSTATIC
DISCHARGE SENSITIVITY

Any integral circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada­tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.

PACKAGE INFORMATION

DAC7545

1
2
3
4
5
6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

OUT 1
AGND
DGND

(MSB) DB

11

DB

10

DB

9

DB

8

DB

7

DB

6

DB

5

R

FB

V

REF

V

DD

WR
CS
DB

0

(LSB)

DB

1

DB

2

DB

3

DB

4

ORDERING INFORMATION

Top View DIP/SOIC

4

DAC7545

PAD FUNCTION

1 OUT 1
2 AGND

3 AGND
4 DGND
5 DB11
6 DB10
7 DB9
8 DB8

9 DB7
10 DB6
11 DB

5

12 DB

4

13 DB

3

14 DB

2

15 DB1 (LSB)
16 DB

0

17 CS
18 WR
19 XYR
20 V

DD

21 V

REF

22 R

FB

23 OUT

1

WRITE CYCLE TIMING DIAGRAM

Mode Selection

Write Mode Hold Mode

CS and WR low, DAC responds Either CS or WR high, data bus
to Data Bus (DB

0

-DB11) inputs. (DB0-DB11) is locked out; DAC
holds last data present when
WR or CS assumed high state.

NOTES: VDD = +5V, tR = tF = 20ns. VDD = +15V, tR = tF = 40ns. All inputs signal
rise and fall times measured from 10% to 90% of V

DD

. Timing measurement

reference level is (V

IH

+ VIL)/2.

t

DS

t

DH

V

IH

V

IL

Data

Valid

V

DD

0

t

WR

t

CS

t

CH

V

DD

0

V

DD

0

Data In

(DB

0

-DB11)

WR

CS

PAD FUNCTION

Substrate Bias: Isolated. NC: No Connection

MECHANICAL INFORMATION

MILS (0.001") MILLIMETERS

Die Size 136 x 134 ±5 3.45 x 3.40 ±0.13
Die Thickness 20 ±3 0.51 ±0.08
Min. Pad Size 4 x 4 0.10 x 0.10

Metalization Aluminum

DAC7545 DIE TOPOGRAPHY

23 22

DISCUSSION
OF SPECIFICATIONS

Relative Accuracy

This term (also known as end point linearity) describes the
transfer function of analog output to digital input code.
Relative accuracy describes the deviation from a straight
line after zero and full scale have been adjusted.

Differential Nonlinearity

Differential nonlinearity is the deviation from an ideal 1LSB
change in the output, for adjacent input code changes. A
differential nonlinearity specification of 1LSB guarantees
monotonicity.

Gain Error

Gain error is the difference in measure of full-scale output
versus the ideal DAC output. The ideal output for the
DAC7545 is –(4095/4096)(V

REF

). Gain error may be ad­justed to zero using external trims as shown in the applica­tions section.

Output Leakage Current

The current which appears at OUT 1 with the DAC loaded
with all zeros.

Multiplying Feedthrough Error

The AC output error due to capacitive feedthrough from
V

REF

to OUT 1 with the DAC loaded with all zeros. This test

is performed using a 10kHz sine wave.

Output Current Settling Time

The time required for the output to settle within ±0.5LSB
of final value from a change in code of all zeros to all ones,
or all ones to all zeros.

5

DAC7545

Propagation Delay

The delay of the internal circuitry is measured as the time
from a digital code change to the point at which the
output reaches 90% of final value.

Digital-to-Analog Glitch Impulse

The area of the glitch energy measured in nanovolt-seconds.
Key contributions to glitch energy are internal circuitry
timing differences and charge injected from digital
logic. The measurement is performed with V

REF

= GND and

an OPA600 as the output op amp and G

1

(phase

compensation) = 0pF.

Monotonicity

Monotonicity assures that the analog output will increase
or stay the same for increasing digital input codes. The
DAC7545 is guaranteed monotonic to 12 bits, except the
J grade is specified to be 10-bit monotonic.

Power Supply Rejection

Power supply rejection is the measure of the sensitivity of
the output (full scale) to a change in the power supply
voltage.

CIRCUIT DESCRIPTION

Figure 1 shows a simplified schematic of the digital-to­analog converter portion of the DAC7545. The current from
the V

REF

pin is switched from OUT 1 to AGND by the
FET switch. This circuit architecture keeps the resistance at
the reference pin constant and equal to R

LDR

, so the reference
could be provided by either a voltage or current, AC or DC,
positive or negative polarity, and have a voltage range up to
±20V even with V

DD

= 5V. The R

LDR

is equal to “R” and is

typically 11kΩ.

FIGURE 2. Unipolar Binary Operation.

BINARY CODE ANALOG OUTPUT

MSB LSB

1111 1111 1111 –V

IN

(4095/4096)

1000 0000 0000 –V

IN

(2048/4096) = –1/2V

IN

0000 0000 0001 –VIN (1/4096)
0000 0000 0000 0 V

TABLE I. Unipolar Codes.

The output capacitance of the DAC7545 is code dependent
and varies from a minimum value (70pF) at code 000H to a
maximum (200pF) at code FFFH.

The input buffers are CMOS inverters, designed so that
when the DAC7545 is operated from a 5V supply (V

DD

), the
logic threshold is TTL-compatible. Being simple CMOS
inverters, there is a range of operation where the inverters
operate in the linear region and thus draw more supply

FIGURE 1. Simplified DAC Circuit of the DAC7545.

RR

2R 2R

R

2R

R

2R

R

FB

2R

OUT 1

AGND

DB0

(

LSB

)

DB9DB10DB11

(

MSB

)

V

REF

OPA604

V

IN

R

1

R

2

VDDR

FB

DAC7545

AGND

DGND

OUT 1

DB

0

-DB

11

C

1

33pF

+5V

V

OUT

V

REF

current than normal. Minimizing this transition time through
the linear region and insuring that the digital inputs are
operated as close to the rails as possible will minimize the
supply drain current.

APPLICATIONS

UNIPOLAR OPERATION

Figure 2 shows the DAC7545 connected for unipolar opera­tion. The high-grade DAC7545 is specified for a 1LSB gain
error, so gain adjust is typically not needed. However, the
resistors shown are for adjusting full-scale errors. The value
of R

1

should be minimized to reduce the effects of mis­matching temperature coefficients between the internal and
external resistors. A range of adjustment of 1.5 times the
desired range will be adequate. For example, for a
DAC7545JP, the gain error is specified to be ±25LSB. A
range of adjustment of ±37LSB will be adequate. The
equation below results in a value of 458Ω for the potentiom­eter (use 500Ω).

R

1

= (3 x Gain Error)

R

LADDER

4096

The addition of R

1

will cause a negative gain error. To

compensate for this error, R

2

must be added. The value of R

2

should be one-third the value of R1.
The capacitor across the feedback resistor is used to com-

pensate for the phase shift due to stray capacitances of the
circuit board, the DAC output capacitance, and op amp input
capacitance. Eliminating this capacitor will result in exces­sive ringing and an increase in glitch energy. This capacitor
should be as small as possible to minimize settling time.

The circuit of Figure 2 may be used with input voltages up
to ±20V as long as the output amplifier is biased to handle
the excursions. Table I represents the analog output for four
codes into the DAC for Figure 2.

6

DAC7545

BIPOLAR OPERATION

Figure 3 and Table II illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function
itself uses offset binary code. The inverter, U

1

, on the MSB
line converts two's complement input code to offset binary
code. If the inversion is done in software, U1 may be
omitted.

R

3

, R4, and R5 must match within 0.01% and should be the
same type of resistors (preferably wire-wound or metal foil),
so that their temperature coefficients match. Mismatch of R

3

value to R4 causes both offset and full-scale error. Mismatch
of R

5

to R4 and R3 causes full-scale error.

DIGITALLY CONTROLLED GAIN BLOCK

Figure 4 shows a circuit for digitally controlled gain block.
The feedback for the op amp is made up of the FET switch
and the R-2R ladder. The input resistor to the gain block is
the R

FB

of the DAC7545. Since the FET switch is in the
feedback loop, a “zero code” into the DAC will result in the
op amp having no feedback, and a saturated op amp output.

APPLICATIONS HINTS

CMOS DACs, such as the DAC7545, exhibit a code-depen­dent out resistance. The effect of this is a code-dependent
differential nonlinearity at the amplifier output which
depends on the offset voltage, V

OS

, of the amplifier. Thus
linearity depends upon the potential of OUT 1 and AGND
being exactly equal to each other. Usually the DAC is

connected to an external op amp with its noninverting input
connected to AGND. The op amp selected should have a
low input bias current and low V

OS

and VOS drift over

temperature. The op amp offset voltage should be less than
(25 x 10–6)(V

REF

) over operating conditions. Suitable op
amps are the Burr-Brown OPA37 and the OPA627 for fixed
reference applications and low bandwidth requirement. The
OPA37 has low V

OS

and will not require an offset trim. For
wide bandwidth, high slew rate, or fast settling applications,
the Burr-Brown OPA604 or 1/2 OPA2604 are recommended.

Unused digital inputs should be connected to V

DD

or to
DGND. This prevents noise form triggering the high imped­ance digital input. It is suggested that the unused digital
inputs also be given a path to ground or V

DD

through a 1MΩ

resistor to prevent the accumulation of static charge if the PC
card is unplugged from the system. In addition, in systems
where the AGND to DGND connection is on a backplane, it
is recommended that two diodes be connected in inverse
parallel between AGND and DGND.

FIGURE 4. Digitally Controlled Gain Block.

FIGURE 3. Bipolar Operation (Two's Complement Code).

DATA INPUT ANALOG OUTPUT

MSB LSB

0111 1111 1111 +V

IN

(2047/2048)

0000 0000 0001 +V

IN

(1/2048)
0000 0000 0000 0 V
1111 1111 1111 –V

IN

(1/2048)

1000 0000 0000 –V

IN

(2048/2048)

TABLE II. Two's Complement Code Table for Circuit of

Figure 3.

OPA604

or

1/2 OPA2604

V

IN

R

1

R

2

V

DD

R

FB

DAC7545

AGND

DB

10

-DB

0

OUT 1

Data Input

C

1

33pF

+5V

DB

11

V

REF

V

OUT

R

3

10kΩ

R

4

20kΩ

R

5

20kΩ

R

6

5kΩ 10%

U

1

(See Text)

12

11

Analog Common

2

1

18 20

19

4

OPA604

or

1/2 OPA2604

R

FB

DAC7545

AGND

DGND

OUT

1

DB

0

-DB

11

V

IN

WR

V

OUT

CS

16

+5V

NOTE: There must be
at least 1LSB loaded in
the DAC or the amp will
saturate due to the lack
of feedback.

OPA111

17

18

19

V

OUT

=

–V

IN

DB

11

+

2

DB

10

+

4

DB

9

+ ••• +

8

DB

0

4096

20

7

DAC7545

INTERFACING
TO MICROPROCESSORS

The DAC7545 can be directly interfaced to either an 8- or
16-bit microprocessor through its 12-bit wide data latch
using the CS and WR controls.

An 8-bit processor interface is shown in Figure 5. It uses two
memory addresses, one for the lower 8 bits and one for the
upper 4 bits of data into the DAC via the latch.

FIGURE 5. 8-Bit Processor Interface.

DAC7545

CS

DB

0

DB

7

WR

DB

8

DB

11

Latch

CS

WR

44

8

Q

1

(2)

8-Bit Data Bus

Q

0

(1)

Address Bus

Address

Decode

CPU

WR

DB

7

DB

0

A

15

A

0

NOTES: (1) Q0 = Decoded Address for DAC.
(2) Q

1

= Decoded Address for Latch.