Datasheet DAC1020LCV, DAC1020LCN, DAC1020LJ, DAC1020LCVX Datasheet (NSC)

TL/H/5689

DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter

DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter

May 1996

DAC1020/DAC1021/DAC1022
10-Bit Binary Multiplying D/A Converter
DAC1220/DAC1222
12-Bit Binary Multiplying D/A Converter

General Description

The DAC1020 and the DAC1220 are, respectively, 10 and
12-bit binary multiplying digital-to-analog converters. A de­posited thin film R-2R resistor ladder divides the reference
current and provides the circuit with excellent temperature
tracking characteristics (0.0002%/

§

C linearity error temper­ature coefficient maximum). The circuit uses CMOS current
switches and drive circuitry to achieve low power consump­tion (30 mW max) and low output leakages (200 nA max).
The digital inputs are compatible with DTL/TTL logic levels
as well as full CMOS logic level swings. This part, combined
with an external amplifier and voltage reference, can be
used as a standard D/A converter; however, it is also very
attractive for multiplying applications (such as digitally con­trolled gain blocks) since its linearity error is essentially in­dependent of the voltage reference. All inputs are protected
from damage due to static discharge by diode clamps to V

a

and ground.

This part is available with 10-bit (0.05%), 9-bit (0.10%), and
8-bit (0.20%) non-linearity guaranteed over temperature

(note 1 of electrical characteristics). The DAC1020,
DAC1021 and DAC1022 are direct replacements for the 10­bit resolution AD7520 and AD7530 and equivalent to the
AD7533 family. The DAC1220 and DAC1222 are direct re­placements for the 12-bit resolution AD7521 and AD7531
family.

Features

Y

Linearity specified with zero and full-scale adjust only

Y

Non-linearity guaranteed over temperature

Y

Integrated thin film on CMOS structure

Y

10-bit or 12-bit resolution

Y

Low power dissipation 10 mW@15V typ

Y

Accepts variable or fixed referenceb25VsV

REF

s

25V

Y

4-quadrant multiplying capability

Y

Interfaces directly with DTL, TTL and CMOS

Y

Fast settling timeÐ500 ns typ

Y

Low feedthrough errorÐ(/2 LSB@100 kHz typ

Equivalent Circuit Note. Switches shown in digital high state

TL/H/5689– 1

10-BIT D/A CONVERTERS

Ordering Information

Temperature Range 0§Cto70§C

b

40§Cto85§C

Non-

0.05% DAC1020LCN AD7520LN,AD7530LN DAC1020LCV DAC1020LIV

Linearity

0.10% DAC1021LCN AD7520KN,AD7530KN

0.20% DAC1022LCN AD7520JN,AD7530JN

Package Outline N16A V20A

12-BIT D/A CONVERTERS

Temperature Range 0§Cto70§C

b

40§Ctoa85§C

Linearity

Non-

0.05% DAC1220LCN AD7521LN,AD7531LN DAC1220LCJ AD7521LD,AD7531LD

0.20% DAC1222LCN AD7521JN,AD7531JN DAC1222LCJ AD7521JD,AD7531JD

Package Outline N18A J18A

Note. Devices may be ordered by either part number.

C

1996 National Semiconductor Corporation RRD-B30M96/Printed in U. S. A.

http://www.national.com

Absolute Maximum Ratings (Note 5)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

V

a

to Gnd 17V

V

REF

to Gnd

g

25V

Digital Input Voltage Range V

a

to Gnd

DC Voltage at Pin 1 or Pin 2 (Note 3)

b

100 mV to V

a

Storage Temperature Range

b

65§Ctoa150§C

Lead Temperature (Soldering, 10 sec.)

Dual-In-Line Package (plastic) 260

§

C

Dual-In-Line Package (ceramic) 300

§

C

ESD Susceptibility (Note 4) 800V

Operating Ratings

Min Max Units

Temperature (T

A

)

DAC1020LIV, DAC1220LCJ,

DAC1222LCJ

b

40a85

§

C

DAC1020LCN, DAC1020LCV,

DAC1021LCN 0

a

70

§

C

DAC1022LCN, DAC1220LCN 0

a

70

§

C

DAC1222LCN 0

a

70

§

C

Electrical Characteristics (V

a

e

15V, V

REF

e

10.000V, T

A

e

25§C unless otherwise specified)

DAC1020, DAC1021,

DAC1220, DAC1222

Parameter Conditions DAC1022 Units

Min Typ Max Min Typ Max

Resolution 10 12 Bits

Linearity Error T

MIN

k

T

A

k

T

MAX

,

b

10VkV

REF

k

a

10V,
(Note 1) End Point Adjustment Only
(See Linearity Error in Definition of Terms)

10-Bit Parts DAC1020, DAC1220 0.05 0.05 % FSR
9-Bit Parts DAC1021 0.10 0.10 % FSR
8-Bit Parts DAC1022, DAC1222 0.20 0.20 % FSR

Linearity Error Tempco

b

10VsV

REF

s

a

10V, 0.0002 0.0002 % FS/§C
(Notes 1 and 2)

Full-Scale Error

b

10VsV

REF

s

a

10V, 0.3 1.0 0.3 1.0 % FS
(Notes 1 and 2)

Full-Scale Error Tempco T

MIN

k

T

A

k

T

MAX

, 0.001 0.001 % FS/§C

(Note 2)

Output Leakage Current T

MIN

s

T

A

s

T

MAX

I

OUT 1

All Digital Inputs Low 200 200 nA

I

OUT 2

All Digital Inputs High 200 200 nA

Power Supply Sensitivity All Digital Inputs High, 0.005 0.005 % FS/V

14VsV

a

s

16V, (Note 2),

(Figure 2)

V

REF

Input Resistance 10 15 20 10 15 20 kX

Full-Scale Current Settling R

L

e

100X from 0 to 99. 95%

Time FS

All Digital Inputs Switched 500 500 ns
Simultaneously

V

REF

Feedthrough All Digital Inputs Low, 10 10 mVp-p

V

REF

e

20 Vp-p@100 kHz
J Package (Note 4) 6 9 6 9 mVp-p
N Package 2 5 2 5 mVp-p

Output Capacitance

I

OUT 1

All Digital Inputs Low 40 40 pF
All Digital Inputs High 200 200 pF

I

OUT 2

All Digital Inputs Low 200 200 pF
All Digital Inputs High 40 40 pF

http://www.national.com 2

Electrical Characteristics (V

a

e

15V, V

REF

e

10.000V, T

A

e

25§C unless otherwise specified) (Continued)

DAC1020, DAC1021,

DAC1220, DAC1222

Parameter Conditions DAC1022 Units

Min Typ Max Min Typ Max

Digital Input

(Figure 1)

Low Threshold T

MIN

k

T

A

k

T

MAX

0.8 0.8 V

High Threshold T

MIN

k

T

A

k

T

MAX

2.4 2.4 V

Digital Input Current T

MIN

s

T

A

s

T

MAX

Digital Input High 1 100 1 100 mA
Digital Input Low

b

50

b

200

b

50

b

200 mA

Supply Current All Digital Inputs High 0.2 1.6 0.2 1.6 mA

All Digital Inputs Low 0.6 2 0.6 2 mA

Operating Power Supply

(Figures 1 and 2)

5 15 5 15 V

Range

Note 1: V

REF

e

g

10V and V

REF

e

g

1V. A linearity error temperature coefficient of 0.0002% FS for a 45§C rise only guarantees 0.009% maximum change in

linearity error. For instance, if the linearity error at 25

§

C is 0.045% FS it could increase to 0.054% at 70§C and the DAC will be no longer a 10-bit part. Note,

however, that the linearity error is specified over the device full temperature range which is a more stringent specification since

it includes

the linearity error

temperature coefficient.

Note 2: Using internal feedback resistor as shown in

Figure 3

.

Note 3: Both I

OUT 1

and I

OUT 2

must go to ground or the virtual ground of an operational amplifier. If V

REF

e

10V, every millivolt offset between I

OUT 1

or I

OUT 2

,

0.005% linearity error will be introduced.

Note 4: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 5: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 6: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

JMAX

, iJA, and the ambient temepature, TA. The maximum

allowable power dissipation at any temperature is P

D

e

(T

JMAX

b

TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this

device, T

JMAX

e

125§C, and the typical junction-to-ambient thermal resistance of the J18 package when board mounted is 85§C/W. For the N18 package, iJAis

120

§

C/W, for the N16 this number is 125§C/W, and for the V20 this number is 95§C/W.

Typical Performance Characteristics

TL/H/5689– 2

FIGURE 1. Digital Input Threshold vs

Ambient Temperature

FIGURE 2. Gain Error Variation vs V

a

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Typical Applications

The following applications are also valid for 12-bit systems
using the DAC1220 and 2 additional digital inputs.

Operational Amplifier Bias Current (

Figure 3

)

The op amp bias current, Ib, flows through the 15k internal
feedback resistor. BI-FET op amps have low I

b

and, there-

fore, the 15k

c

Iberror they introduce is negligible; they are

strongly recommended for the DAC1020 applications.

V

OS

Considerations

The output impedance, R

OUT

, of the DAC is modulated by
the digital input code which causes a modulation of the op­erational amplifier output offset. It is therefore recommend­ed to adjust the op amp V

OS.ROUT

isE15k if more than 4

digital inputs are high; R

OUT

isE45k if a single digital input

is high, and R

OUT

approaches infinity if all inputs are low.

Operational Amplifier V

OS

Adjust (

Figure 3

)

Connect all digital inputs, A1 –A10, to ground and adjust the
potentiometer to bring the op amp V

OUT

pin to withing1

mV from ground potential. If V

REF

is less than 10V, a finer

V

OS

adjustment is required. It is helpful to increase the reso-

lution of the V

OS

adjust procedure by connectinga1kX
resistor between the inverting input of the op amp to
ground. After V

OS

has been adjusted, remove the 1 kX.

Full-Scale Adjust (

Figure 4

)

Switch high all the digital inputs, A1 –A10, and measure the
op amp output voltage. Use a 500X potentiometer, as
shown, to bring

ll

V

OUT

ll

to a voltage equal to V

REF

c

1023/1024.

SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER

Op Amp Family C

F

R

i

PV

W

Circuit Settling Circuit Small

Time, t

s

Signal BW

LF357 10 pF 2.4k 25k V

a

1.5 ms1M

LF356 22 pF

%

25k V

a

3 ms 0.5M

LF351 24 pF

%

10k V

b

4 ms 0.5M

LM741 0

%

10k V

b

40 ms 200 kHz

TL/H/5689– 3

V

OUT

eb

V

REF

#

A1

2

a

A2

4

a

A3

8

a

###

A10

1024

J

b

10VsV

REF

s

10V

0

s

V

OUT

s

b

1023

1024

V

REF

where A

N

e

1 if the ANdigital input is high

A

N

e

0 if the ANdigital input is low

FIGURE 3. Basic Connection: Unipolar or 2-Quadrant Multiplying

Configuration (Digital Attenuator)

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Typical Applications (Continued)

FIGURE 4. Full-Scale Adjust

FIGURE 5. Alternate Full-Scale Adjust: (Allows Increasing or Decreasing the Gain)

TL/H/5689– 4

V

OUT 1

eb

V

REF

#

A1

2

a

A2

4

a

A3

8

a

###

A10

1024

J

V

OUT2

e

V

REF

#

A1

2

a

A2

4

a

A3

8

a

###

A10

1024

Jc#

B1

2

a

B2

4

a

B3

8

a

###

B10

1024

J

where V

REF

can be an AC signal

FIGURE 6. Precision Analog-to-Digital Multiplier

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Typical Applications (Continued)

TL/H/5689– 5

V

OUT

eb

V

REF

#

A1

2

a

A2

4

a

###

a

A10

1024

b

1

1024

J

where: ANea1ifANinput is high

AN

eb

1ifANinput is low

COMPLEMENTARY OFFSET BINARY

(BIPOLAR) OPERATION

DIGITAL INPUT V

OUT

0000000000

a

V

REF

0000000001 V

REF

c

1022/1024

0111111111 V

REF

c

2/1024
1000000000 0
1000000001

b

V

REF

c

2/1024

1111111111

b

V

REF

(1022/1024)

Note that:

#

I

OUT 1

a

I

OUT 2

e

V

REF

R

LADDER

c

#

1023

1024

J

#

By doubling the output range we get half the
resolution

#

The 10M resistor, adds a 1 LSB ‘‘thump’’, to
allow full offset binary operation where the out­put reaches zero for the half-scale code. If
symmetrical output excursions are required,
omit the 10M resistor.

FIGURE 7. Bipolar 4-Quadrant Multiplying Configuration

Operational Amplifiers V

OS

Adjust (

Figure 7

)

a) Switch all the digital inputs high; adjust the V

OS

potenti­ometer of op amp B to bring its output to a value equal
to

b

(V

REF

/1024) (V).

b) Switch the MSB high and the remaining digital inputs

low. Adjust the V

OS

potentiometer of op amp A, to bring
its output value to withina1mVfrom ground potential.
For V

REF

k

10V, a finer adjust is necessary, as already

mentioned in the previous application.

Gain Adjust (Full-Scale Adjust)

Assuming that the external 10k resistors are matched to
better than 0.1%, the gain adjust of the circuit is the same
with the one previously discussed.

TL/H/5689– 6

TRUE OFFSET BINARY OPERATION

DIGITAL INPUT V

OUT

1111111111V

REF

c

1022/1024
1000000000 0
0000000000

b

V

REF

t

s

e

1.8 ms

use LM336 for a voltage reference

FIGURE 8. Bipolar Configuration with a Single Op Amp

#

R4e(2A

V

b

b

1) R,

R2

R1

e

A

V

b

A

V

b

b

1

,

R3

a

R1llR2eR; A

V

b

e

V

OUT(PEAK)

V

REF

,Re20k

#

Example: V

REF

e

2V, V

OUT

(swing)

j

g

10V: A

V

b

e

5V

Then R4

e

9R, R1e0.8 R2. If R1e0.2R then R2e0.25R,

R3

e

0.64R

FIGURE 9. Bipolar Configuration with

Increased Output Swing

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Typical Applications (Continued)

V

OUT

e

b

V

REF

#

A1

2

a

A2

4

a

A3

8

a

...

A10

1024

J

where: V

REF

can be an AC signal

#

By connecting the DAC in the feedback loop of an opera­tional amplifier a linear digitally control gain block can be
realized

#

Note that with all digital inputs low, the gain of the amplifier
is infinity, that is, the op amp will saturate. In other words, we
cannot divide the V

REF

by zero!

FIGURE 10. Analog-to-Digital Divider (or Digitally Gain Controlled Amplifier)

V

OUT

e

V

REF

%

A1

2

a

A2

4

a

...

a

A10

1024

A1

2

a

A2

4

a

...

a

A10

1024

–

or V

OUT

e

V

REF

#

1023bN

N

J

where: 0sNs1023

N

e

0 for A

N

e

all zeros

N

e

1 for A10e1, A1– A9e0

.

.

.

N

e

1023 for A

N

e

all 1’s

FIGURE 11. Digitally controlled Amplifier-Attenuator

TL/H/5689– 7

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Typical Applications (Continued)

TL/H/5689– 8

#

Output frequency

e

f

CLK

512

;f

MAX

j

2 kHz

#

Output voltage rangee0Vb10V peak

#

THDk0.2%

#

Excellent amplitude and frequency stability with temperature

#

Low pass filter shown has a 1 kHz corner (for output frequencies below 10 Hz,
filter corner should be reduced)

#

Any periodic function can be implemented by modifying the contents of the look
up table ROM

#

No start up problems

FIGURE 12. Precision Low Frequency Sine Wave Oscillator Using Sine Look-Up ROM

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Typical Applications (Continued)

MM74C00 Ð NAND gates

MM74C32 Ð OR gates

MM74C74 Ð D flip-flop

MM74C193 Ð Binary up/

down counters

TL/H/5689– 9

#

Binary up/down counter digitally ‘‘ramps’’ the DAC
output

#

Can stop counting at any desired 10-bit input code

#

Senses up or down count overflow and automatically
reverses direction of count

FIGURE 13. A Useful Digital Input Code Generator for DAC Attenuator or Amplifier Circuits

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Definition of Terms

Resolution: Resolution is defined as the reciprocal of the

number of discrete steps in the D/A output. It is directly
related to the number of switches or bits within the D/A. For
example, the DAC1020 has 2

10

or 1024 steps while the

DAC1220 has 2

12

or 4096 steps. Therefore, the DAC1020
has 10-bit resolution, while the DAC1220 has 12-bit resolu­tion.

Linearity Error: Linearity error is the maximum deviation
from

a straight line passing through the endpoints of the

D/A transfer characteristic.

It is measured after calibrating

for zero (see V

OS

adjust in typical applications) and full­scale. Linearity error is a design parameter intrinsic to the
device and cannot be externally adjusted.

Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the D/A
full-scale output.

Settling Time: Full-scale settling time requires a zero to full­scale or full-scale to zero output change. Settling time is the
time required from a code transition until the D/A output
reaches within

g

(/2 LSB of final output value.

Full-Scale Error: Full-scale error is a measure of the output
error between an ideal D/A and the actual device output.
Ideally, for the DAC1020 full-scale is V

REF

b

1 LSB. For

V

REF

e

10V and unipolar operation, V

FULL-SCA-

LE

e

10.0000VÐ9.8 mVe9.9902V. Full-scale error is ad-

justable to zero as shown in

Figure 5

.

TL/H/5689– 10

ab1b2

(a) End point test after zero and full-scale adjust.

The DAC has 1 LSB linearity error.

(b) By shifting the full-scale calibration on of the DAC of

Figure (b1)

we could pass the ‘‘best straight line’’ (b2)

test and meet the

g

(/2 linearity error specification.

Note. (a), (b1) and (b2) above illustrate the difference between ‘‘end point’’ National’s linearity test (a) and ‘‘best straight line’’ test. Note that both devices in (a) and
(b2) meet the

g

(/2 LSB linearity error specification but the end point test is a more ‘‘real life’’ way of characterizing the DAC.

Connection Diagrams

DAC102X

Dual-In-Line Package

TL/H/5689– 13

DAC1020

PLCC Package

TL/H/5689– 12

DAC122X

Dual-In-Line Package

TL/H/5689– 11

http://www.national.com 10

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Physical Dimensions inches (millimeters) unless otherwise noted

Cavity Dual-In-Line Package (J)

Order Number DAC1220LCJ or DAC1222LCJ

NS Package Number J18A

Molded Dual-In-Line Package (N)

Order Number DAC1020LCN, DAC1021LCN or DAC1022LCN

NS Package Number N16A

http://www.national.com 12

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number DAC1220LCN, DAC1221LCN or DAC1222LCN

NS Package Number N18A

http://www.national.com13

DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter

DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Plastic Leaded Chip Carrier (V)

Order Number DAC1020LCV or DAC1020LIV

NS Package Number V20A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax:

a

49 (0) 180-530 85 86 13th Floor, Straight Block, Tel: [phone]
Arlington, TX 76017 Email: [e-mail] Ocean Centre, 5 Canton Rd. Fax: [phone]
Tel: [phone] Deutsch Tel:

a

49 (0) 180-530 85 85 Tsimshatsui, Kowloon
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a

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a

49 (0) 180-532 93 58 Tel: [phone]

http://www.national.com

Italiano Tel:a49 (0) 180-534 16 80 Fax: [phone]

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.