Datasheet DAC1008LCN, DAC1006LCWM, DAC1006LCN Datasheet (NSC)

DAC1006/DAC1007/DAC1008 mP Compatible,
Double-Buffered D to A Converters

General Description

The DAC1006/7/8 are advanced CMOS/Si-Cr 10-, 9- and
8-bit accurate multiplying DACs which are designed to inter­face directly with the 8080, 8048, 8085, Z-80 and other pop­ular microprocessors. These DACs appear as a memory lo­cation or an I/O port to the mP and no interfacing logic is
needed.

These devices, combined with an external amplifier and
voltage reference, can be used as standard D/A converters;
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentially independent of the voltage reference.
They become equally attractive in audio signal processing
equipment as audio gain controls or as programmable at­tenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control.

All of these DACs are double buffered. They can load all 10
bits or two 8-bit bytes and the data format is left justified.
The analog section of these DACs is essentially the same
as that of the DAC1020.

The DAC1006 series are the 10-bit members of a family of
microprocessor-compatible DAC’s (MICRO-DAC
applications requiring other resolutions, the DAC0830 series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are avail­able alternatives.

Part

Ý

(bits)

Pin Description

Accuracy

DAC1006 10

DAC1007 9 20

DAC1008 8

MICRO-DACTMand BI-FETTMare trademarks of National Semiconductor Corp.

For left­justified
data

TM

’s). For

Features

Y

Uses easy to adjust END POINT specs, NOT BEST
STRAIGHT LINE FIT

Y

Low power consumption

Y

Direct interface to all popular microprocessors

Y

Integrated thin film on CMOS structure

Y

Double-buffered, single-buffered or flow through digital
data inputs

Y

Loads two 8-bit bytes or a single 10-bit word

Y

Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)

Y

Works withg10V referenceÐfull 4-quadrant multiplica­tion

Y

Operates STAND ALONE (without mP) if desired

Y

Available in 0.3×standard 20-pin package

Y

Differential non-linearity selection available as special
order

Key Specifications

Y

Output Current Settling Time 500 ns

Y

Resolution 10 bits

Y

Linearity 10, 9, and 8 bits

Y

Gain Tempco

Y

Low Power Dissipation 20 mW
(including ladder)

Y

Single Power Supply 5 to 15 V

January 1995

(guaranteed over temp.)

b

0.0003% of FS/§C

DC

DAC1006/DAC1007/DAC1008 mP Compatible,

Double-Buffered D to A Converters

Typical Application

DAC1006/1007/1008

* NOTE: FOR DETAILS OF BUS

CONNECTION SEE SECTION 6.0

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/H/5688

TL/H/5688– 1

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

Voltage at Any Digital Input VCCto GND

Voltage at V

Storage Temperature Range

Package Dissipation at T

DC Voltage Applied to I

(Note 4)

)17V

REF

CC

Input

b

e

25§C (Note 3) 500 mW

A

or I

OUT1

OUT2

65§Ctoa150§C

b

100 mV to V

DC

g

25V

CC

ESD Susceptibility (Note 11) 800V

Lead Temp. (Soldering, 10 seconds)

Dual-In-Line Package (plastic) 260
Dual-In-Line Package (ceramic) 300

Operating Ratings (Note 1)

s

s

T

Temperature Range T

Part numbers with

MIN

‘‘LCN’’ and ‘‘LCWN’’ suffix 0

Voltage at Any Digital Input VCCto GND

T

A

MAX

Cto70§C

§

C

§

C

§

Electrical Characteristics

Tested at V

e

4.75 VDCand 15.75 VDC,T

CC

Parameter Conditions

Resolution 10 10 bits

Linearity Error Endpoint adjust only 4,7

Differential Endpoint adjust only 4,7

Nonlinearity T

Monotonicity T

Gain Error Using internal R

Gain Error Tempco T

Power Supply All digital inputs

Rejection latched high

Reference Input

Resistance 10 15 20 10 15 20 kX

Output Feedthrough V

Error All data inputs 90 90 mV

Output I

Capacitance I

OUT1
OUT2

I

OUT1

I

OUT2

Supply Current Drain T

k

k

T

T

MIN

b

DAC1006 0.05 0.05 % of FSR
DAC1007 0.1 0.1 % of FSR
DAC1008 0.2 0.2 % of FSR

MIN

b

DAC1006 0.1 0.1 % of FSR
DAC1007 0.2 0.2 % of FSR
DAC1008 0.4 0.4 % of FSR

MIN

b

DAC1006 10 10 bits
DAC1007 9 9 bits
DAC1008 8 8 bits

b

MIN

Using internal R

V

CC

REF

T

A

10VsV

10VsV

10VsV

10VsV

MAX

REF

k

k

T

T

A

MAX

REF

k

k

T

T

A

MAX

REF

REF

k

k

T

T

A

MAX

e

14.5V to 15.5V 0.003 0.008 % FSR/V

11.5V to 12.5V 0.004 0.010 % FSR/V

4.75V to 5.25V 0.033 0.10 % FSR/V

e

20V

p-p

latched low

All data inputs 60 60 pF

latched low 250 250 pF

All data inputs 250 250 pF

latched high 60 60 pF

s

s

T

MIN

T

A

MAX

e

25§C, V

A

s

a

10V 5

s

a

10V 5

s

a

10V 5

fb

s

a

10V 5b1.0g0.3 1.0

fb

e

10.000 VDCunless otherwise noted

REF

e

12V

V

See

Note

CC

to 15V

DC

Min. Typ. Max. Min. Typ. Max.

6

6

4,6

6
9

b

0.0003b0.001

,fe100 kHz

6 0.5 3.5 0.5 3.5 mA

g

5%

DC

g

5% Units

e

V

CC

b

1.0g0.3 1.0 % of FS

g

5V

5%

DC

b

0.0006b0.002 % of FS/§C

p-p

2

Electrical Characteristics

Tested at V

e

4.75 VDCand 15.75 VDC,T

CC

Parameter Conditions

Output Leakage T

Current I

OUT1

I

OUT2

Digital Input T

Voltages Low level

s

T

MIN

A

All data inputs

latched low 10 200 200 nA

All data inputs

latched high 200 200 nA

s

T

MIN

A

LCN and LCWM suffix 0.8, 0.8 0.7, 0.8 V

High level (all parts) 2.0 2.0 V

Digital Input T

Currents Digital inputs

MIN

s

T

A

Digital inputsl2.0V 1.0

Current Settling t

Time

Write and XFER t

Pulse Width T

Data Set Up Time t

Data Hold Time t

Control Set Up t

Time T

Control Hold Time t

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify

the power dissipation) removes concern for heat sinking.

Note 4: For current switching applications, both I
degraded by approximately V

Note 5: Guaranteed at V

Note 6: T

Note 7: The unit ‘‘FSR’’ stands for ‘‘Full Scale Range.’’ ‘‘Linearity Error’’ and ‘‘Power Supply Rejection’’ specs are based on this unit to eliminate dependence on a

particular V
guarantees that after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within

0.05%

Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t
of only 100 ns. The entire write pulse must occur within the valid data interval for the specified tW,tDS,tDH, and tSto apply.

Note 9: Guaranteed by design but not tested.

Note 10: A 200 nA leakage current with R

Note 11: Human body model, 100 pF discharged through a 1.5 kX resistor.

e

MIN

REF

c

V

of a straight line which passes through zero and full scale.

REF

S

WVIL

DSVIL

DHVIL

CSVIL

CHVIL

REF

0§C and T

MAX

value and to indicate the true performance of the part. The ‘‘Linearity Error’’ specification of the DAC1006 is ‘‘0.05% of FSR (MAX).’’ This

e

V

0V, V

IL

e

0V, V

e

A

s

T

T

MIN

A

e

0V, V

e

T

A

s

T

T

MIN

A

e

OV, V

e

T

A

s

T

T

MIN

A

e

0V, V

e

A

s

T

T

MIN

A

e

0V, V

e

T

A

s

T

T

MIN

A

d

V

. For example, if V

OS

REF

e

g

10 VDCand V

e

70§C for ‘‘LCN’’ and ‘‘LCWM’’ suffix parts.

e

fb

REF

20K and V

e

25§C, V

A

s

T

MAX

s

T

MAX

s

T

MAX

k

0.8V

e

5V 500 500 ns

IH

e

5V,

IH

25§C 8 150 60 320 200 ns

s

T

MAX

e

5V,

IH

25§C 9 150 80 320 170 ns

s

T

MAX

e

5V

IH

25§C 9 200 100 320 220 ns

s

T

MAX

e

5V,

IL

25§C 9 150 60 320 180 ns

s

T

MAX

e

5V,

IH

25§C 9 10 0 10 0 ns

s

T

MAX

and I

OUT1

OUT2

e

10Vthena1mVoffset, VOS,onI

REF

e

g

1VDC.

e

10V corresponds to a zero error of (200c10

REF

e

10.000 VDCunless otherwise noted (Continued)

REF

e

g

12V

V

See

Note

CC

to 15V

Min. Typ. Max. Min. Typ. Max.

5%

DC

g

5% Units

DC

e

5V

DC

g

5%

V

CC

6

6

6

b

b

40

150

a

10 1.0

b

b

40

150 mA

a

10 mA

9 320 100 500 250 ns

320 120 500 250 ns

250 120 500 320 ns

320 100 500 260 ns

10 0 10 0 ns

must go to ground or the ‘‘Virtual Ground’’ of an operational amplifier. The linearity error is

OUT1

or I

will introduce an additional 0.01% linearity error.

OUT2

) of 320 ns. A typical part will operate with t

W

b

9

c

20c103)c100d10 which is 0.04% of FS.

DC
DC

DC
DC

W

3

Switching Waveforms

Typical Performance Characteristics

Errors vs. Supply Voltage Errors vs. Temperature Write Width, t

TL/H/5688– 2

W

Control Setup Time, t

Digital Threshold
vs. Supply Voltage

CS

Data Setup Time, t

4

DS

Digital Input Threshold
vs. Temperature

Data Hold Time, t

DH

TL/H/5688– 3

Block and Connection Diagrams

DAC1006/1007/1008 (20-Pin Parts)

DAC1006/1007/1008

(20-Pin Parts)

Dual-In-Line Package

Top View

See Ordering Information

USE DAC1006/1007/1008
FOR LEFT JUSTIFIED DATA

TL/H/5688– 5

DAC1006/1007/1008ÐSimple Hookup for a ‘‘Quick Look’’

*A TOTAL OF 10
INPUT SWITCHES
& 1K RESISTORS

Notes:

eb

1. For V

2. SW1 is a normally closed switch. While SW1 is closed, the DAC register is latched and new data

can be loaded into the input latch via the 10 SW2 switches.

When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes.

10.240 VDCthe output voltage steps are approximately 10 mV each.

REF

TL/H/5688– 28

TL/H/5688– 7

5

1.0 DEFINITION OF PACKAGE PINOUTS

R

1.1 Control Signals (All control signals are level actuated.)

: Chip Select Ð active low, it will enable WR.

CS

WR: Write Ð The active low WR is used to load the digital

data bits (DI) into the input latch. The data in the input latch
is latched when WR

is high. The 10-bit input latch is split
into two latches; one holds 8 bits and the other holds 2 bits.
The Byte1/Byte2
latches when Byte1/Byte2

control pin is used to select both input

e

1 or to overwrite the 2-bit input

latch when in the low state.

Byte1/Byte2

: Byte Sequence Control Ð When this control

is high, all ten locations of the input latch are enabled. When
low, only two locations of the input latch are enabled and
these two locations are overwritten on the second byte
write. On the DAC1006, 1007, and 1008, the Byte1/Byte2
must be low to transfer the 10-bit data in the input latch to
the DAC register.

XFER

: Transfer Control Signal, active low Ð This signal, in

combination with others, is used to transfer the 10-bit data
which is available in the input latch to the DAC register Ð
see timing diagrams.

1.2 Other Pin Functions

DI

(ie0 to 9): Digital Inputs Ð DI0is the least significant bit

i

(LSB) and DI

I

OUT1

digital input code of all 1s and is zero for a digital input code

is the most significant bit (MSB).

g

: DAC Current Output1ÐI

is a maximum for a

OUT1

of all 0s.

I

: DAC Current Output2ÐI

OUT2

I

,or

OUT1

I

OUT1

a

I

OUT2

1023 V

e

1024 R

REF

is a constant minus

OUT2

where Rj15 kX.

: Feedback Resistor Ð This is provided on the IC chip

FB

for use as the shunt feedback resistor when an external op
amp is used to provide an output voltage for the DAC. This
on-chip resistor should always be used (not an external re­sistor) because it matches the resistors used in the on-chip
R-2R ladder and tracks these resistors over temperature.

V

: Reference Voltage Input Ð This is the connection for

REF

the external precision voltage source which drives the R-2R
ladder. V
the analog voltage input for a 4-quadrant multiplying DAC

can range fromb10 toa10 volts. This is also

REF

application.

V

: Digital Supply Voltage Ð This is the power supply pin

CC

for the part. V
optimum for
independent of V
tics and Description in Section 3.0, T

can be froma5toa15 VDC. Operation is

CC

a

15V. The input threshold voltages are nearly

. (See Typical Performance Characteris-

CC

inputs.)

GND: Ground Ð the ground pin for the part.

1.3 Definition of Terms

Resolution: Resolution is directly related to the number of

switches or bits within the DAC. For example, the DAC1006

10

has 2

or 1024 steps and therefore has 10-bit resolution.

Linearity Error: Linearity error is the maximum deviation
from a

straight line passing through the endpoints of the

DAC transfer characteristic.

for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.

National’s linearity test (a) and the ‘‘best straight line’’ test
(b) used by other suppliers are illustrated below. The ‘‘best
straight line’’ requires a special zero and FS adjustment for
each part, which is almost impossible for user to determine.
The ‘‘end point test’’ uses a standard zero and FS adjust­ment procedure and is a much more stringent test for DAC
linearity.

Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output (which is the worst case).

a. End Point Test After Zero and FS Adj. b. Best Straight Line

2

L compatible logic

It is measured after adjusting

TL/H/5688– 8

6

Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within

g

(/2 LSB of
the final output value. Full-scale settling time requires a zero
to full-scale or full-scale to zero output change.

Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC1006 series, full-scale is V
For V

LE

able to zero.

eb

10V and unipolar operation, V

REF

e

10.0000Vb9.8mVe9.9902V. Full-scale error is adjust-

b

REF

FULL-SCA-

1 LSB.

Monotonicity: If the output of a DAC increases for increas­ing digital input code, then the DAC is monotonic. A 10-bit
DAC with 10-bit monotonicity will produce an increasing an­alog output when all 10 digital inputs are exercised. A 10-bit
DAC with 9-bit monotonicity will be monotonic when only
the most significant 9 bits are exercised. Similarly, 8-bit
monotonicity is guaranteed when only the most significant 8
bits are exercised.

2.0 DOUBLE BUFFERING

These DACs are double-buffered, microprocessor compati­ble versions of the DAC1020 10-bit multiplying DAC. The
addition of the buffers for the digital input data not only al­lows for storage of this data, but also provides a way to
assemble the 10-bit input data word from two write cycles
when using an 8-bit data bus. Thus, the next data update for
the DAC output can be made with the complete new set of
10-bit data. Further, the double buffering allows many DACs
in a system to store current data and also the next data. The
updating of the new data for each DAC is also not time
critical. When all DACs are updated, a common strobe sig­nal can then be used to cause all DACs to switch to their
new analog output levels.

3.0 TTL COMPATIBLE LOGIC INPUTS

To guarantee TTL voltage compatibility of the logic inputs, a
novel bipolar (NPN) regulator circuit is used. This makes the
input logic thresholds equal to the forward drop of two di­odes (and also matches the temperature variation) as oc­curs naturally in TTL. The basic circuit is shown in

Figure 1

A curve of digital input threshold as a function of power
supply voltage is shown in the Typical Performance Charac­teristics section.

4.0 APPLICATION HINTS

The DC stability of the V
factor to maintain accuracy of the DAC over time and tem-

source is the most important

REF

perature changes. A good single point ground for the analog
signals is next in importance.

These MICRO-DAC converters are CMOS products and
reasonable care should be exercised in handling them prior
to final mounting on a PC board. The digital inputs are pro­tected, but permanent damage may occur if the part is sub­jected to high electrostatic fields. Store unused parts in con­ductive foam or anti-static rails.

4.1 Power Supply Sequencing & Decoupling

Some IC amplifiers draw excessive current from the Analog
inputs to V

b

when the supplies are first turned on. To pre­vent damage to the DAC Ð an external Schottky diode con­nected from I
prevent destructive currents in I
or LF356 is used Ð these diodes are not required.

OUT1

or I

to ground may be required to

OUT2

OUT1

or I

. If an LM741

OUT2

The standard power supply decoupling capacitors which are
used for the op amp are adequate for the DAC.

.

FIGURE 1. Basic Logic Threshold Loop

7

TL/H/5688– 9

4.2 Op Amp Bias Current & Input Leads

The op amp bias current (I

TM

FET

op amps have very low bias current, and therefore

) CAN CAUSE DC ERRORS. BI-

B

the error introduced is negligible. BI-FET op amps are
strongly recommended for these DACs.

The distance from the I
input of the op amp should be kept as short as possible to

pin of the DAC to the inverting

OUT1

prevent inadvertent noise pickup.

5.0 ANALOG APPLICATIONS

The analog section of these DACs uses an R-2R ladder
which can be operated both in the current switching mode
and in the voltage switching mode.

The major product changes (compared with the DAC1020)
have been made in the digital functioning of the DAC. The
analog functioning is reviewed here for completeness. For
additional analog applications, such as multipliers, attenua­tors, digitally controlled amplifiers and low frequency sine
wave oscillators, refer to the DAC1020 data sheet. Some
basic circuit ideas are presented in this section in addition to
complete applications circuits.

5.1 Operation in Current Switching Mode

The analog circuitry,

Figure 2

, consists of a silicon-chromi­um (Si-Cr) thin film R-2R ladder which is deposited on the
surface oxide of the monolithic chip. As a result, there is no
parasitic diode connected to the V
diffused resistors were used. The reference voltage input
(V

) can therefore range fromb10V toa10V.

REF

pin as would exist if

REF

The digital input code to the DAC simply controls the posi­tion of the SPDT current switches, SW0 to SW9. A logical 1
digital input causes the current switch to steer the avail-

DIGITAL INPUT CODE

able ladder current to the I
switches operate in the current mode with a small voltage

output pin. These MOS

OUT1

drop across them and can therefore switch currents of ei­ther polarity. This is the basis for the 4-quadrant multiplying
feature of this DAC.

5.1.1 Providing a Unipolar Output Voltage with the
DAC in the Current Switching Mode

A voltage output is provided by making use of an external
op amp as a current-to-voltage converter. The idea is to use
the internal feedback resistor, R
op amp to the inverting (

, from the output of the

FB

b

) input. Now, when current is
entered at this inverting input, the feedback action of the op
amp keeps that input at ground potential. This causes the
applied input current to be diverted to the feedback resistor.
The output voltage of the op amp is forced to a voltage
given by:

V

OUT

eb

(I

OUT1

c

RFB)

Notice that the sign of the output voltage depends on the
direction of current flow through the feedback resistor.

In current switching mode applications, both current output
pins (I
accomplished as shown in

OUT1

and I

) should be operated at 0 VDC. This is

OUT2

Figure 3

. The capacitor, CC,is
used to compensate for the output capacitance of the DAC
and the input capacitance of the op amp. The required feed­back resistor, R
nally tied to I
resistor will not provide the needed matching and tempera-

, is available on the chip (one end is inter-

FB

) and must be used since an external

OUT1

ture tracking. This circuit can therefore be simplified as

FIGURE 2. Current Mode Switching

FIGURE 3. Converting I

OUT

to V

8

OP AMP CCpF Rjts mS

LF356 22

OUT

LF351 24

LF357 10 2.4k 1.5

%

%

TL/H/5688– 10

3

4

shown in
has been changed to provide a positive output voltage. Note
that the output current, I
pin.

5.1.2 Providing a Bipolar Output Voltage with the

The addition of a second op amp to the circuit of
can be used to generate a bipolar output voltage from a
fixed reference voltage
significance to the MSB of the digital input word to allow two
quadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize the full four­quadrant multiplication.

The applied digital word is offset binary which includes a
code to output zero volts without the need of a large valued
resistor common to existing bipolar multiplying DAC circuits.
Offset binary code can be derived from 2’s complement
data (most common for signed processor arithmetic) by in­verting the state of the MSB in either software or hardware.
After doing this the output then responds in accordance to
the following expression:

Figure 4

, where the sign of the reference voltage

, now flows through the R

OUT1

DAC in the Current Switching Mode

Figure 5

. This, in effect, gives sign

D

c

e

V

V

O

REF

512

FB

Figure 4

where V
decimal equivalent of the 2’s complement processor data.

b

(

512sD
applied digital input is interpreted as the decimal equivalent
of a true binary word, V

V

O

With this configuration, only the offset voltage of amplifier 1
need be nulled to preserve linearity of the DAC. The offset
voltage error of the second op amp has no effect on lineari­ty. It presents a constant output voltage error and should be
nulled only if absolute accuracy is needed. Another advan­tage of this configuration is that the values of the external
resistors required do not have to match the value of the
internal DAC resistors; they need only to match and temper­ature track each other.

A thin film 4 resistor network available from Beckman Instru­ments, Inc. (part no. 694-3-R10K-D) is ideally suited for this
application. Two of the four available 10 kX resistor can be
paralleled to form R in
used separately as the resistors labeled 2R.

Operation is summarized in the table below:

can be positive or negative and D is the signed

REF

s

a

511 or 1000000000sDs0111111111). If the

can be found by:

512

OUT

J

Figure 5

and the other two can be

Db512

e

V

REF

#

0sDs1023

2’s Comp. 2’s Comp. Applied True Binary V

(Decimal) (Binary) Digital Input (Decimal)

a

511 0111111111 1111111111 1023 V

a

256 0100000000 1100000000 768 V

0 0000000000 1000000000 512 0 0

b

1 1111111111 0111111111 511

b

256 1100000000 0100000000 256

b

512 1000000000 0000000000 0

V

l

l

REF

with: 1 LSB

e

512

FIGURE 4. Providing a Unipolar Output Voltage

FIGURE 5. Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode

Applied

REF

b

a

b

b

V

b

REF

1 LSB

V

REF

V

REF

1 LSB

/2

/2

REF

OUT

b

V

l

b

a

b

V

REF

a

1 LSB

l

REF

V

/2

l

l

REF

a

1 LSB

V

/2

l

l

REF

a

V

l

l

REF

TL/H/5688– 11

9

5.2 Analog Operation in the Voltage Switching Mode

Some useful application circuits result if the R-2R ladder is
operated in the voltage switching mode. There are two very
important things to remember when using the DAC in the
voltage mode. The reference voltage (

a

V) must always be
positive since there are parasitic diodes to ground on the
I

pin which would turn on if the reference voltage went

OUT1

negative. To maintain a degradation of linearity less than

g

0.005%, keepaVs3VDCand VCCat least 10V more
positive than
voltage switching mode. This operation appears unusual,
since a reference voltage (
and the voltage output is the V
shown in

This V
gain stage as shown in

a

V.

Figures 6

Figure 8

.

range can be scaled by use of a non-inverting

OUT

and7show these errors for the

a

V) is applied to the I

pin. This basic idea is

REF

Figure 9

.

OUT1

pin

FIGURE 6 FIGURE 7

DIGITAL INPUT CODE

Notice that this is unipolar operation since all voltages are
positive. A bipolar output voltage can be obtained by using a
single op amp as shown in
code of all zeros, the output voltage from the V
zero volts. The external op amp now has a single input of

a

V and is operating with a gain ofb1 to this input. The

output of the op amp therefore will be at

Figure 10

. For a digital input

pin is

REF

b

V for a digital
input of all zeros. As the digital code increases, the output
voltage at the V

Notice that the gain of the op amp to voltages which are
applied to the (
which are applied to the input resistor, R, is

pin increases.

REF

a

) input isa2 and the gain to voltages

b

1. The output
voltage of the op amp depends on both of these inputs and
is given by:

e(a

V

OUT

V) (b1)aV

REF

(a2)

FIGURE 8. Voltage Mode Switching

FIGURE 9. Amplifying the Voltage Mode Output (Single Supply Operation)

10

TL/H/5688– 12

FIGURE 10. Providing a Bipolar Output Voltage with a Single Op Amp

FIGURE 11. Increasing the Output Voltage Swing

The output voltage swing can be expanded by adding 2
resistors to

Figure 10

resistors are used to attenuate the
gain, A

(b), from theaV terminal to the output of the op

V

amp determines the most negative output voltage,
(when the V
zero) with the component values shown. The complete dy­namic range of V
input of the op amp. As the voltage at the V
from 0V to
range from

a

V voltage ofa2.500 VDC. The 2.5 VDCreference voltage

a

b

as shown in

voltage at theainput of the op amp is

REF

is provided by the gain from the (a)

OUT

V(1023/1024) the output of the op amp will

Figure 11

a

. These added

V voltage. The overall

b4(a

pin ranges

REF

10 VDCtoa10V (1023/1024) when using a

can be easily developed by using the LM336 zener which
can be biased through the R
to V

.

CC

5.3 Op Amp V
Switching Mode

Adjust (Zero Adjust) for Current

OS

internal resistor, connected

FB

Proper operation of the ladder requires that all of the 2R
legs always go to exactly 0 V
voltage, V
every millivolt of V
error. At first this seems unusually sensitive, until it becomes

, of the external op amp cannot be tolerated as

OS

will introduce 0.01% of added linearity

OS

(ground). Therefore offset

DC

clear the 1 mV is 0.01% of the 10V reference! High resolu­tion converters of high accuracy require attention to every
detail in an application to achieve the available performance
which is inherent in the part. To prevent this source of error,
the V

of the op amp has to be initially zeroed. This is the

OS

‘‘zero adjust’’ of the DAC calibration sequence and should
be done first.

TL/H/5688– 13

If the V
er. Note that no ‘‘dc balancing’’ resistance should be used

is to be adjusted there are a few points to consid-

OS

in the grounded positive input lead of the op amp. This re­sistance and the input current of the op amp can also create

V)

errors. The low input biasing current of the BI-FET op amps
makes them ideal for use in DAC current to voltage applica­tions. The V
digital input of all zeros to force I
can be temporarily connected from the inverting input to
ground to provide a dc gain of approximately 15 to the V
of the op amp and make the zeroing easier to sense.

of the op amp should be adjusted with a

OS

e

0mA.A1kXresistor

OUT

OS

5.4 Full-Scale Adjust

The full-scale adjust procedure depends on the application
circuit and whether the DAC is operated in the current
switching mode or in the voltage switching mode. Tech­niques are given below for all of the possible application
circuits.

5.4.1 Current Switching with Unipolar Output Voltage

After doing a ‘‘zero adjust,’’ set all of the digital input levels
HIGH and adjust the magnitude of V

V

OUT

eb

(ideal V

REF

)

1023

1024

REF

for

This completes the DAC calibration.

11

5.4.2 Current Switching with Bipolar Output Voltage

The circuit of

Figure 12

shows the 3 adjustments needed.
The first step is to set all of the digital inputs LOW (to force
I

to 0) and then trim ‘‘zero adj.’’ for zero volts at the

OUT1

inverting input (pin 2) of 0A1. Next, with a code of all zeros
still applied, adjust ‘‘

e

g

V
be opposite that of the applied reference.

OUT

(ideal V

l

Finally, set all of the digital inputs HIGH and adjust ‘‘
adj.’’ for V
this time will be the same as that of the reference voltage.

OUT

The addition of the 200X resistor in series with the V
of the DAC is to force the circuit gain error from the DAC to
be negative. This insures that adding resistance to R
the 500X pot, will always compensate the gain error of the

b

FS adj.’’, the reference voltage, for

)l. The sign of the output voltage will

REF

e

V

(511/512). The sign of the output at

REF

REF

fb

a

FS

pin

, with

DAC.

5.4.3 Voltage Switching with a Unipolar Output Voltage

Refer to the circuit of
LOW. Trim the ‘‘zero adj.’’ for V
set all digital inputs HIGH and trim the ‘‘FS Adj.’’ for:

e(a

OUT

V)#1

V

a

R

1

R

2

Figure 13

1023

1024

J

and set all digital inputs

e

g

0V

OUT

DC

1 mV. Then

5.4.4 Voltage Switching with a Bipolar Output Voltage

Refer to

Figure 14

b

‘‘

FS Adj.’’ for V
HIGH and trim the ‘‘
V

. Test the zero by setting the MS digital input HIGH and

DC

all the rest LOW. Adjust V
recheck the full-scale values.

and set all digital inputs LOW. Trim the

eb

2.5 VDC. Then set all digital inputs

OUT

a

FS Adj.’’ for V

of ampÝ3, if necessary, and

OS

OUT

ea

2.5 (511/512)

s

b

V

V

REF

OUT

511

s

a

V

REF

512

#

J

FIGURE 12. Full Scale Adjust Ð Current Switching with Bipolar Output Voltage

FIGURE 13. Full Scale Adjust Ð Voltage Switching with a Unipolar Output Voltage

TL/H/5688– 14

12

FIGURE 14. Voltage Switching with a Bipolar Output Voltage

6.0 DIGITAL CONTROL DESCRIPTION

The DAC1006 series of products can be used in a wide
variety of operating modes. Most of the options are shown
in Table 1. Also shown in this table are the section numbers
of this data sheet where each of the operating modes is
discussed. For example, if your main interest in interfacing
to a mP with an 8-bit data bus you will be directed to Section

6.1.0.

The first consideration is ‘‘will the DAC be interfaced to a mP
with an 8-bit or a 16-bit data bus or used in the stand-alone
mode?’’ For the 8-bit data bus, a second selection is made
on how the 2nd digital data buffer (the DAC Latch) is updat­ed by a transfer from the 1st digital data buffer (the Input
Latch). Three options are provided: 1) an automatic transfer
when the 2nd data byte is written to the DAC, 2) a transfer
which is under the control of the mP and can include more
than one DAC in a simultaneous transfer, or 3) a transfer
which is under the control of external logic. Further, the data
format can be either left justified or right justified.

When interfacing to a mP with a 16-bit data bus only two
selections are available: 1) operating the DAC with a single
digital data buffer (the transfer of one DAC does not have to

2) operating with a double digital data buffer for simulta­neous transfer, or updating, of more than one DAC.

For operating without a mP in the stand alone mode, three
options are provided: 1) using only a single digital data buff­er, 2) using both digital data buffers Ð ‘‘double buffered,’’ or

3) allowing the input digital data to ‘‘flow through’’ to provide
the analog output without the use of any data latches.

To reduce the required reading, only the applicable sections
of 6.1 through 6.4 need be considered.

6.1 Interfacing to an 8-Bit Data Bus

Transferring 10 bits of data over an 8-bit bus requires two
write cycles and provides four possible combinations which
depend upon two basic data format and protocol decisions:

1. Is the data to be left justified (considered as fractional
binary data with the binary point to the left) or right justi­fied (considered as binary weighted data with the binary
point to the right)?

2. Which byte will be transferred first, the most significant
byte (MS byte) or the least significant byte (LS byte)?

be synchronized with any other DACs in the system), or

Table 1

Operating Mode Automatic Transfer mP Control Transfer External Transfer

Section Figure No. Section Figure No. Section Figure No.

Data Bus

8-Bit Data Bus (6.1.0)

Left Justified (6.1.1) 6.2.1 16 6.2.2 16 6.2.3 16

16-Bit Data Bus (6.3.0)

Single Buffered Double Buffered Flow Through

6.3.1 17 6.3.2 17 Not Applicable

Stand Alone (6.4.0)

Single Buffered Double Buffered Flow Through

6.4.1 17 6.4.2 17 NA

TL/H/5688-15

13

These data possibilities are shown in

Figure 15

. Note that
the justification of data depends on how the 10-bit data
word is located within the 16-bit data source (CPU) register.
In either case, there is a surplus of 6 bits and these are
shown as ‘‘don’t care’’ terms (‘‘

c

’’) in this figure.

All of these DACs load 10 bits on the 1st write cycle. A
particular set of 2 bits is then overwritten on the 2nd write
cycle, depending on the justification of the data. For all left
justified data options, the 1st write cycle must contain the
MS or Hi Byte data group.

6.1.1 For Left Justified Data

For applications which require left justified data, DAC1006 –
1008 can be used. A simplified logic diagram which shows
the external connections to the data bus and the internal
functions of both of the data buffer registers (Input Latch
and DAC Register) is shown in

Figure 16

. These

DAC1006/1007/1008 (20-Pin Parts for Left Justified Data)

parts require the MS or Hi Byte data group to be transferred
on the 1st write cycle.

6.2 Controlling Data Transfer for an 8-Bit Data Bus

Three operating modes are possible for controlling the
transfer of data from the Input Latch to the DAC Register,
where it will update the analog output voltage. The simplest
is the automatic transfer mode, which causes the data
transfer to occur at the time of the 2nd write cycle. This is
recommended when the exact timing of the changes of the
DAC analog output are not critical. This typically happens
where each DAC is operating individually in a system and
the analog updating of one DAC is not required to be syn­chronized to any other DAC. For synchronized DAC updat­ing, two options are provided: mP control via a common
XFER

strobe or external update timing control via an exter-

nal strobe. The details of these options are now shown.

FIGURE 15. Fitting a 10-Bit Data Word into 16 Available Bit Locations

TL/H/5688– 16

FIGURE 16. Input Connections and Controls for DAC1006/1007/1008 Left Justified Data

TL/H/5688– 17

14

6.2.1 Automatic Transfer

This makes use of a double byte (double precision) write.
The first byte (8 bits) is strobed into the input latch and the
second byte causes a simultaneous strobe of the two re­maining bits into the input latch and also the transfer of the
complete 10-bit word from the input latch to the DAC regis­ter. This is shown in the following timing diagram; the point
in time where the analog output is updated is also indicated
on this diagram.

DAC1006/1007/1008 (20-Pin Parts)

*SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL

TL/H/5688– 18

6.2.2 Transfer Using mP Write Stroke

The input latch is loaded with the first two write strobes. The
XFER

signal is provided by external logic, as shown below,
to cause the transfer to be accomplished on a third write
strobe. This is shown in the following diagram:

DAC1006/1007/1008 (20-Pin Parts)

6.2.3 Transfer Using an External Strobe

This is similar to the previous operation except the XFER
signal is not provided by the mP. The timing diagram for this
is:

DAC1006/1007/1008 (20-Pin Parts)

TL/H/5688– 20

6.3 Interfacing to a 16-Bit Data Bus

The interface to a 16-bit data bus is easily handled by con­necting to 10 of the available bus lines. This allows a wiring
selected right justified or left justified data format. This is
shown in the connection diagram of

Figure 17

, where the
use of DB6 to DB15 gives left justified data operation. Note
that any part number can be used and the Byte1/Byte2

con-

trol should be wired Hi.

TL/H/5688– 19

15

FIGURE 17. Input Connections and Logic for DAC1006/1007/1008 with 16-Bit Data Bus

Three operating modes are possible: flow through, single
buffered, or double buffered. The timing diagrams for these
are shown below:

6.3.1 Single Buffered
DAC1006/1007/1008 (20-Pin Parts)

TL/H/5688– 21

6.4 Stand Alone Operation

For applications for a DAC which are not under mP control
(stand alone) there are two basic operating modes, single
buffered and double buffered. The timing diagrams for these
are shown below:

6.4.1 Single Buffered
DAC1006/1007/1008 (20-Pin Parts)

6.3.2 Double Buffered
DAC1006/1007/1008 (20-Pin Parts)

*For a connection diagram of this operating mode use

TL/H/5688– 22

Figure 16

for the Logic and

16

6.4.2 Double Buffered
DAC1006/1007/1008 (20-Pin Parts)*

Figure 17

for the Data Input connections.

TL/H/5688– 23

7.0 MICROPROCESSOR INTERFACE

The logic functions of the DAC1006 family have been ori­ented towards an ease of interface with all popular mPs. The
following sections discuss in detail a few useful interface
schemes.

7.1 DAC1001/1/2 to INS8080A Interface

Figure 18

illustrates the simplicity of interfacing the

DAC1006 to an INS8080A based microprocessor system.

The circuit will perform an automatic transfer of the 10 bits
of output data from the CPU to the DAC register as outlined
in Section 6.2.1, ‘‘Controlling Data Transfer for an 8-Bit Data
Bus.’’

Since a double byte write is necessary to control the DAC
with the INS8080A, a possible instruction to achieve this is a
PUSH of a register pair onto a ‘‘stack’’ in memory. The 16­bit register pair word will contain the 10 bits of the eventual
DAC input data in the proper sequence to conform to both

NOTE: DOUBLE BYTE STORES CAN BE USED.

e.g. THE INSTRUCTION SHLD F001 STORES THE L

REG INTO B1 AND THE H REG INTO B2 AND

TRANSFERS THE RESULT TO THE DAC REGISTER.

THE OPERAND OF THE SHLD INSTRUCTION MUST

BE AN ODD ADDRESS FOR PROPER TRANSFER.

FIGURE 18. Interfacing the DAC1000 to the INS8080A CPU Group

17

TL/H/5688– 24

the requirements of the DAC (with regard to left justified
data) and the implementation of the PUSH instruction which
will output the higher order byte of the register pair (i.e.,
register B of the BC pair) first. The DAC will actually appear
as a two-byte ‘‘stack’’ in memory to the CPU. The auto-dec­rementing of the stack pointer during a PUSH allows using
address bit 0 of the stack pointer as the Byte1/Byte2
XFER

strobes if bit 0 of the stack pointer addressb1,

b

(SP

1), is a ‘‘1’’ as presented to the DAC. Additional ad-

and

dress decoding by the DM8131 will generate a unique DAC
chip select (CS) and synchronize this CS to the two memory
write strobes of the PUSH instruction.

To reset the stack pointer so new data may be output to the
same DAC, a POP instruction followed by instructions to
insure that proper data is in the DAC data register pair be­fore it is ‘‘PUSHED’’ to the DAC should be executed, as the
POP instruction will arbitrarily alter the contents of a register
pair.

Another double byte write instruction is Store H and L Direct
(SHLD), where the HL register pair would temporarily con­tain the DAC data and the two sequential addresses for the
DAC are specified by the instruction op code. The auto in­crementing of the DAC address by the SHLD instruction
permits the same simple scheme of using address bit 0 to
generate the byte number and transfer strobes.

7.2 DAC1006 to MC6820/1 PIA Interface

In

Figure 19

the DAC1006 is interfaced to an M6800 system
through an MC6820/1 Peripheral Interface Adapter (PIA). In
this case the CS pin of the DAC is grounded since the PIA is
already mapped in the 6800 system memory space and no
decoding is necessary. Furthermore, by using both Ports A
and B of the PIA the 10-bit data transfer, assumed left
justified again in two 8-bit bytes, is greatly simplified. The
HIGH byte is loaded into Output Register A (ORA) of the

PIA, and the LOW byte is loaded into ORB. The 10-bit data
transfer to the DAC and the corresponding analog output
change occur simultaneously upon CB2 going LOW under
program control. The 10-bit data word in the DAC register
will be latched (and hence V
brought back HIGH.

will be fixed) when CB2 is

OUT

If both output ports of the PIA are not available, it is possible
to interface the DAC1006 through a single port without
much effort. However, additional logic at the CB2(or CA2)
lines or access to some of the 6800 system control lines will
be required.

7.3 Noise Considerations

A typical digital/microprocessor bus environment is a tre­mendous potential source of high frequency noise which
can be coupled to sensitive analog circuitry. The fast edges
of the data and address bus signals generate frequency
components of 10’s of megahertz and can cause noise
spikes to appear at the DAC output. These noise spikes
occur when the data bus changes state or when data is
transferred between the latches of the device.

In low frequency or DC applications, low pass filtering can
reduce these noise spikes. This is accomplished by over­compensating the DAC output amplifier by increasing the
value of the feedback capacitor (C

C

in

Figure 3

).

In applications requiring a fast transient response from the
DAC and op amp, filtering may not be feasible. Adding a
latch, DM74LS374, as shown in

Figure 20

isolates the de­vice from the data bus, thus eliminating noise spikes that
occur every time the data bus changes state. Another meth­od for eliminating noise spikes is to add a sample and hold
after the DAC op amp. This also has the advantage of elimi­nating noise spikes when changing digital codes.

FIGURE 19. DAC1000 to MC6820/1 PIA Interface

18

TL/H/5688– 25

NOTE: DATA HOLD TIME REDUCED TO THAT OF DM74LS374 (&10 ns)

FIGURE 20. Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling

FIGURE 21. Digitally Controlled Amplifier/Attenuator

7.4 Digitally Controlled Amplifier/Attenuator

An unusual application of the DAC,

Figure 21

, applies the
input voltage via the on-chip feedback resistor. The lower
op amp automatically adjusts the V
I

is equal to the input current (VIN/RfB). The magnitude

OUT1

of this V
in the DAC register. I
magnitude of V
converts I

e

V

OUT

voltage depends on the digital word which is

REF IN

OUT2

V

IN

#

and the digital word. The second op amp

IN

to a voltage, V

1023bN

N

then depends upon both the

OUT2

OUT

, where 0kNs1023.

J

voltage such that

REF IN

, which is given by:

TL/H/5688– 26

Note that N

e

0 (or a digital code of all zeros) is not allowed

or this will cause the output amplifier to saturate at either

g

V

, depending on the sign of VIN.

MAX

To provide a digitally controlled divider, the output op amp
can be eliminated. Ground the I
V

is now taken from the lower op amp (which also drives

OUT

the V

input of the DAC). The expression for V

REF

given by

V

IN

V

OUT

eb

M

e

where M

fractional binary number).

kMk

0

Digital input (expressed as a

1.

pin of the DAC and

OUT2

19

OUT

is now

Ordering Information

For Left Justified Data Ð 20-pin package.

Accuracy

0.05% (10-bit) DAC1006LCN DAC1006LCWM

0.10% (9-bit) DAC1007LCN

0.20% (8-bit) DAC1008LCN

Package Outline N20A M20B

FIGURE 22. Digital to Synchro Converter

Temperature Range

toa70§C

0

§

TL/H/5688– 27

20

Physical Dimensions inches (millimeters)

Order Number DAC1006LCWM

NS Package Number M20B

21

Physical Dimensions inches (millimeters) (Continued)

Order Number DAC1006LCN, DAC1007LCN or DAC1008LCN

NS Package Number N20A

Double-Buffered D to A Converters

DAC1006/DAC1007/DAC1008 mP Compatible,

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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Corporation Europe Hong Kong Ltd. Japan Ltd.

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Arlington, TX 76017 Email: [e-mail] Ocean Centre, 5 Canton Rd. Fax: [phone]
Tel: [phone] Deutsch Tel: (
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