Datasheet DAC08 Datasheet (ANALOG DEVICES)

8-Bit, High Speed, Multiplying D/A Converter

FEATURES

Fast settling output current: 85 ns
Full-scale current prematched to ±1 LSB
Direct interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to 0.1% maximum over temperature range
High output impedance and compliance: −10 V to +18 V
Complementary current outputs
Wide range multiplying capability: 1 MHz bandwidth
Low FS current drift: ±10 ppm/°C
Wide power supply range: ±4.5 V to ±18 V
Low power consumption: 33 mW @ ±5 V
Low cost

GENERAL DESCRIPTION

The DAC08 series of 8-bit monolithic digital-to-analog convert­ers provide very high speed performance coupled with low cost
and outstanding applications flexibility.

Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20-to-1
reference current range. Matching to within 1 LSB between
reference and full-scale currents eliminates the need for full-

(Universal Digital Logic Interface)

DAC08

scale trimming in most applications. Direct interface to all
popular logic families with full noise immunity is provided by
the high swing, adjustable threshold logic input.

High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential
operation to effectively double the peak-to-peak output swing.
In many applications, the outputs can be directly converted to
voltage without the need for an external op amp. All DAC08
series models guarantee full 8-bit monotonicity, and nonlineari­ties as tight as ±0.1% over the entire operating temperature
range are available. Device performance is essentially unchanged
over the ±4.5 V to ±18 V power supply range, with 33 mW
power consumption attainable at ±5 V supplies.

The compact size and low power consumption make the DAC08
attractive for portable and military/aerospace applications;
devices processed to MIL-STD-883, Level B are available.

DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, LCD display drivers, high speed modems, and other
applications where low cost, high speed, and complete
input/output versatility are required.

FUNCTIONAL BLOCK DIAGRAM

V+ V

13 1 5 6 7 8 9 10 11 12

DAC08

BIAS
NETWORK

14

V

(+)

REF

15

V

(–)

REF

REFERENCE

AMPLIFIER

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

LC

CURRENT

SWITCHES

(MSB)

B1

V–COMP

B2 B3 B4 B5 B6 B7

316

Figure 1.

(LSB)

B8

I

OUT

4
2

I

OUT

00268-C-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

DAC08

TABLE OF CONTENTS

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Typical E l e ctric a l Characte r i s tics ............................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Connections ............................................................................... 6

Test and Burn-In Circuits................................................................ 7

Typical Performance Characteristics ............................................. 8

Basic Connections.......................................................................... 11

Application Information................................................................ 13

Reference Amplifier Setup ........................................................ 13

Reference Amplifier Compensation for Multiplying
Applications

Logic Inputs................................................................................. 13

Analog Output Currents ........................................................... 14

Power Supplies ............................................................................ 14

Temperature Performance......................................................... 14

Multiplying Operation............................................................... 14

Settling Time............................................................................... 14

ADI Current Output DACs........................................................... 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 18

................................................................................ 13

REVISION HISTORY

11/04—Rev. B to Rev. C

Changed SO to SOIC .........................................................Universal

Removed DIE......................................................................Universal

Changes to Figure 30, Figure 31, Figure 32................................. 12

Change to Figure 33 ....................................................................... 15

Added Table 4.................................................................................. 16

Updated Outline Dimensions....................................................... 17

Changes to Ordering Guide.......................................................... 18

2/02—Rev. A to Rev. B

Edits to SPECIFICATIONS............................................................. 2

Edits to ABSOLUTE MAXIMUM RATING ................................ 3

Edits to ORDERING GUIDE.......................................................... 3

Edits to WAFER TEST LIMITS...................................................... 5

Edit to Figure 13 ............................................................................... 8

Edits to Figures 14 and 15 ............................................................... 9

Rev. C | Page 2 of 20

DAC08

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VS = ±15 V, I
DAC08C, unless otherwise noted. Output characteristics refer to both I

Table 1.

DAC08A/DAC08H DAC08E DAC08C
Parameter

Resolution 8 8 8 Bits
Monotonicity 8 8 8 Bits
Nonlinearity NL ±0.1 ±0.19 ±0.39 %FS
Settling Time t

Propagation Delay

Each Bit t

All Bits Switched t
Full-Scale Tempco1 TCI
DAC08E ±50
Output Voltage

Compliance V

(True Compliance) Change <1/2 LSB, R

Full Range Current I

Full Range Symmetry I
Zero-Scale Current I
Output Current

Range
I

V
V− = −12 V
Output Current

Noise
Logic Input Levels

Logic 0 V

Logic 1 V
Logic Input Current VLC = 0 V

Logic 0 I

Logic 1 I
Logic Input Swing V
Logic Threshold

Range
Reference Bias

Current
Reference Input dI/dt REQ = 200 Ω 4 8 4 8 4 8 mA/µs

Slew Rate RL = 100 Ω
C
Power Supply

Sensitivity
PSSI
I

= 2.0 mA, –55°C ≤ TA ≤ +125°C for DAC08/DAC08A, 0°C ≤ TA ≤ +70°C for DAC08E and DAC08H, −40°C to +85°C for

REF

I

OUT

Symbol

S

PLH

PHL

FS

OC

and

OUT

Conditions Min Typ Max Min Typ Max Min Typ Max Unit

To ±1/2 LSB, all bits
switched on or off,

1

= 25°C

T

A

85 135 85 150 85 150 ns

TA = 25°C1 35 60 35 60 35 60 ns
35 60 35 60 35 60 ns
±10 ±50 ±10 ±80 ±10 ±80 ppm/°C

Full-scale current

>

OUT

−10 +18 −10 +18 –10 +18 V

.

20 MΩ typ
V

FR4

FRS

ZS

I

OR1

OR2

= 10.000 V R14, R15 =

REF

5.000 kΩ T
I

FR4

− I

= 25°C

A

FR2

0.1 1 0.2 2 0.2 4 µA
R14, R15 = 5.000 kΩ 2.1 2.1 2.1 mA

V

= +15.0 V,

REF

1.984 1.992 2.000 1.94 1.99 2.04 1.94 1.99 2.04 mA

±0.5 ±4 ±1 ±8 ±2 ±16 µA

V− = −10 V

= +25.0 V, 4.2 4.2 4.2 mA

REF

I

IL

IL

IL

IH

IS

V

THR

I

15

PSSI

FS+

FS–

= 2 mA 25 25 25 nA

REF

VLC = 0 V 0.8 0.8 0.8 V
2 2 2 V

VIN = −10 V to +0.8 V −2 −10 −2 −10 −2 −10 µA
VIN = 2.0 V to 18 V 0.002 10 0.002 10 0.002 10 µA
V− = −15 V −10 +18 −10 +18 −10 +18 V
VS = ±15 V1 −10 +13.5 −10 +13.5 −10 +13.5 V

−1 −3 −1 −3 −1 −3 µA

= 0 pF. See Figure 7.

C

1

V+ = 4.5 V to 18 V ±0.0003 ±0.01 ±0.0003 ±0.01 ±0.0003 ±0.01 %∆IO/%∆V+

V− = −4.5 V to −18 V ±0.002 ±0.01 ±0.002 ±0.01 ±0.002 ±0.01 %∆IO/%∆V−

= 1.0 mA

REF

Rev. C | Page 3 of 20

DAC08

DAC08A/DAC08H DAC08E DAC08C
Parameter

Power Supply Current I+ VS = ±5 V, I
I− −4.3 −5.8 −4.3 −5.8 −4.3 −5.8 mA
I+ VS = +5 V, −15 V, 2.4 3.8 2.4 3.8 2.4 3.8 mA
I− I
I+ VS = ±15 V, 2.5 3.8 2.5 3.8 2.5 3.8 mA
I− I
Power Dissipation P

I

135 174 135 174 135 174 mW

1

Guaranteed by design.

TYPICAL ELECTRICAL CHARACTERISTICS

VS = ±15 V, and I

Table 2.

Parameter Symbol Conditions All Grades Typical Unit

Reference Input Slew Rate dI/dt 8 mA/µs
Propagation Delay t
Settling Time t

Symbol

D

= 2.0 mA, unless otherwise noted. Output characteristics apply to both I

REF

Conditions Min Typ Max Min Typ Max Min Typ Max Unit

= 1.0 mA 2.3 3.8 2.3 3.8 2.3 3.8 mA

REF

= 2.0 mA −6.4 −7.8 −6.4 −7.8 −6.4 −7.8 mA

REF

= 2.0 mA −6.5 −7.8 −6.5 −7.8 −6.5 −7.8 mA

REF

±5 V, I

= 1.0 mA +5 V,

REF

−15 V,
= 2.0 mA ±15 V, I

REF

2.0 mA

, t

PLH

PHL

S

REF

33 48 33 48 33 48 mW

=

108 136 103 136 108 136 mW

TA = 25°C, any bit 35 ns
To ±1/2 LSB, all bits switched on or

= 25°C

off, T

A

OUT

and

.

I

OUT

85 ns

Rev. C | Page 4 of 20

DAC08

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Operating Temperature

DAC08AQ, DAC08Q −55°C to +125°C
DAC08HQ, DAC08EQ, DAC08CQ,

0°C to +70°C

DAC08HP, DAC08EP

DAC08CP, DAC08CS −40°C to +85°C
Junction Temperature (TJ) −65°C to +150°C
Storage Temperature Q Package −65°C to +150°C
Storage Temperature P Package −65°C to +125°C
Lead Temperature (Soldering, 60 sec) 300°C
V+ Supply to V− Supply 36 V
Logic Inputs V− to V− + 36 V
V

LC

V− to V+
Analog Current Outputs (at VS− = 15 V) 4.25 mA
Reference Input (V

to V15) V− to V+

14

Reference Input Differential Voltage

(V14 to V15) ±18 V

Reference Input Current (I14) 5.0 mA

Package Type θ

1

JA

θ

Unit

JC

16-Lead CERDIP (Q) 100 16 °C/W
16-Lead PDIP (P) 82 39 °C/W
20-Terminal LCC (RC) 76 36 °C/W
16-Lead SOIC (S) 111 35 °C/W

1

θJA is specified for worst-case mounting conditions, that is, θJA is specified for

device in socket for CERDIP, PDIP, and LCC packages; θ
device soldered to printed circuit board for SOIC package.

is specified for

JA

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 5 of 20

DAC08

PIN CONNECTIONS

1

V

LC

I

2

OUT

V–

3

OUT

B2
B3
B4

DAC08

4

TOP VIEW

(Not To Scale)

5

6

7

8

I

(MSB) B1

Figure 2. 16-Lead Dual In-Line Package

(Q and P Suffixes)

16

COMP
V

15

V

14

V+

13

12

B8 (LSB)
B7

11

10

B6

9

B5

REF

REF

(–)
(+)

00268-C-002

V

REF

V

REF

COMP

I

I

(+)
(–)

V

OUT

OUT

V+

LC

V–

1

2

3

DAC08

4

TOP VIEW

(Not To Scale)

5

6

7

8

16

B8 (LSB)
B7

15

B6

14

B5

13

12

B4
B3

11

10

B2

9

B1 (MSB)

00268-C-003

Figure 3. 16-Lead SOIC

(S Suffix)

(–)

LC

REF

V

NC

V

COMP

20 19123

V

18

REF

V+

17

NC

16
15

B8 (LSB)
B7

14

B5

B6

B4

NC

I

OUT

NC

(MSB) B1

OUT

I

4

V–

5

DAC08

TOP VIEW

6

(Not To Scale)

7

B2

8

10 11 12 13

9

B3

NC = NO CONNECT

Figure 4. DAC08RC/883 20-Lead LCC

(RC Suffix)

(+)

00268-C-004

Rev. C | Page 6 of 20

DAC08

TEST AND BURN-IN CIRCUITS

R

0V
TYPICALVALUES:

=5kΩ

R

IN

=10V

+V

IN

+V

REF

OPTIONAL RESISTOR

R

REF

≈

EQ

P

14

15 16

FOR OFFSET INPUTS

NO CAP

IN

R
200Ω

R

Figure 5. Pulsed Reference Operation

R

4

2

L

R

L

00268-C-006

C2

C1 R1

16 15 14 13 12 11 10 9

+18V

R1 = 9kΩ
C1 = 0.001µF
C2, C3 = 0.01µF

DAC08

12345678

C3

–18V MIN

Figure 6. Burn-In Circuit

00268-C-007

Rev. C | Page 7 of 20

DAC08

TYPICAL PERFORMANCE CHARACTERISTICS

1V

2.5V

0.5V

–0.5mA

I

OUT

–2.5mA

0mA

1.0mA

2.0mA

100mV

R

EQ

R

L

C

C

≈ 200Ω
= 100Ω
= 0

200ns/DIVISION

Figure 7. Fast Pulsed Reference Operation

200ns

I

I

OUT

OUT

00268-C-008

OUTPUT

SETTLING

, OUTPUT CURRENT (mA)

FS

I

2.4V

0.4V

–1/2LSB

0V

+1/2LSB

SETTLINGTIMEFIXTURE
I

FS

1/2LSB= 4µA

5

TA = T

MIN

ALL BITS HIGH

4

3

2

1

ALL BITS SWITCHED ON

1V

10mV

=2mA,RL=1kΩ

Figure 10. Full-Scale Settling Time

TO T

MAX

LIMIT FOR
V– = –5V

LIMIT FOR

V– = –15V

50ns

50ns/DIVISION

00268-C-011

(0000|0000) (1111|1111)

I

REF

= 2mA

00268-C-009

Figure 8. True and Complementary Output Operation

100mV

2V

50ns/DIVISION

50ns

00268-C-010

2.4V

0.4V

8µA

5mV

0V

0

Figure 9. LSB Switching

0

0

1234 5

I

, REFERENCE CURRENT (mA)

REF

00268-C-012

Figure 11. Full-Scale Current vs. Reference Current

500

400

300

200

PROPAGATION DELAY (ns)

100

0

1LSB = 7.8µA

0.005 0.02 0.10 0.50 2.00

IFS, OUTPUT FULL-SCALE CURRENT (mA)

Figure 12. LSB Propagation Delay vs. I

1LSB = 61nA

FS

10.000.01 0.05 0.20 1.00 5.00

00268-C-013

Rev. C | Page 8 of 20

DAC08

10

R14 = R15 = 1kΩ

8

≤

500V

R

L

6

ALL BITS ON

= 0V

V

R15

4
2

0
–2
–4

CC = 15pF, VIN = 2.0V p-p

–6

CENTERED AT +1.0V

RELATIVE OUTPUT (dB)

–8

LARGE SIGNAL

–10

= 15pF, VIN = 50mV p-p

C

C

CENTERED AT +200mV

–12

SMALL SIGNAL

–14

0.1

0.2

0.5

1.0

FREQUENCY (MHz)

Figure 13. Reference Input Frequency Response

4.0
TA = T

TO T

MIN

3.6

3.2

2.8

2.4

2.0

1.6

1.2

OUTPUT CURRENT (mA)

0.8

0.4

0

–14

MAX

NOTE: POSITIVE COMMON-MODE
RANGE IS ALWAYS (V+) –1.5V

V– = –15V V– = –5V V+ = +15V

–10 –6

V15, REFERENCE COMMON-MODE VOLTAGE (V)

–2 2 6

Figure 14. Reference Amp Common-Mode Range

10

8

6

4

LOGIC INPUT (µA)

2

0

–12

–8–40481216

LOGIC INPUT VOLTAGE (V)

Figure 15. Logic Input Current vs. Input Voltage

2

1

2.0 10.0

I

REF

ALL BITS ON

I

= 2mA

REF

I

= 1mA

REF

= 0.2mA

10 14

5.0

18

00268-C-014

00268-C-015

00268-C-016

2.0

1.6

1.2

(V)

LC

–V

TH

0.8

V

0.4

0

–50

0 50 100 150

TEMPERATURE (°C)

Figure 16. V

− VLC vs. Temperature

TH

00268-C-017

4.0
TA = T

3.6

3.2

2.8

2.4

2.0

1.6

1.2

OUTPUT CURRENT (mA)

0.8

0.4

0

–14

TO T

MIN

MAX

V– = –15V V– = –5V I

–10 –6

–2 2 6 10 14

OUTPUTVOLTAGE (V)

I

REF

I

REF

REF

ALL BITS ON

= 2mA

= 1mA

= 0.2mA

18

00268-C-018

Figure 17. Output Current vs. Output Voltage (Output Voltage Compliance)

28

24

20

16

12

SHADED AREA INDICATES PERMISSIBLE
OUTPUT VOLTAGE RANGE FOR V– = –15V.

8

I

≤

2.0mA.

REF

4

FOR OTHER V– OR I
SEE OUTPUT CURRENT VS. OUTPUT

0

OUTPUT V OLTAGE ( V)

VOLTAGE CURVE.

–4

–8

–12

–50 0 50 100 150

,

REF

TEMPERATURE (°C)

00268-C-019

Figure 18. Output Voltage Compliance vs. Temperature

Rev. C | Page 9 of 20

DAC08

1.8

1.6

1.4

1.2

1.0

0.8

0.6

OUTPUT CURRENT (mA)

0.4

0.2

0

–12 0 4 8 16–8

10

8
7

6

5

4

3

2

POWER SUPPLY CURRENT (mA)

1
0

01020

B1

I

= 2.0mA

REF

B2

= 0.0V).

LC

B4

V– = –5V



V– = –15V

–4 12

NOTE:
B1 THROUGH B8 HAVE IDENTICAL TRANSFER
CHARACTERISTICS. BITS ARE FULLY SWITCHED WITH LESS
THAN 1/2 LSB ERROR, AT LESS THAN ±100mV FROM ACTUAL
THRESHOLD. THESE SWITCHING POINTS ARE GUARANTEED
TO LIE BETWEEN 0.8V AND 2.0V OVER THE OPERATING
TEMPERATURE RANGE (V

LOGIC INPUT VOLTAGE (V)

B5

B3

Figure 19. Bit Transfer Characteristics

ALL BITS HIGH OR LOW

I–

I+

294 6 8 12 14 16 18

V+, POSITIVE POWER SUPPLY (V dc)

Figure 20. Power Supply vs. V+

00268-C-020

00268-C-021

10

BITS MAY BE HIGH OR LOW

8
7

6

5

4
3

2

POWER SUPPLY CURRENT (mA)

1
0

0––29–4 –6 –8 –10 –12 –14 –16 –18

V–, NEGATIVE POWER SUPPLY (V dc)

I– WITH I

I– WITH I

I– WITH I

REF

REF

REF

= 2mA

= 1mA

= 0.2mA

I+

20

00268-C-022

Figure 21. Power Supply Current vs. V−

10

ALL BITS HIGH OR LOW

9

8

7

6

5

4

3
2

POWER SUPPLY CURRENT (mA)

1

0

–50 0 50 100 150

V– = –15V

I

= 2.0mA

REF

V+ = +15V

TEMPERATURE (°C)

I–

I+

00268-C-023

Figure 22. Power Supply Current vs. Temperature

Rev. C | Page 10 of 20

DAC08

V

V

A

BASIC CONNECTIONS

+V

REF

R

REF

I

REF

I

IN

14

IN

R

≈ R15

REF

IN

+V

R

IN

I

REF

REF

HIGH INPUT

IMPEDANCE

R

R15

(OPTIONAL)

MUST BE ABOVE PEAK POSITIVE SWING OF V

+V

REF

14

15

15

≥ PEAK NEGATIVE SWING OF I

REF

14

15

Figure 23. Accommodating Bipolar References

V

REF

10V

I

REF

39kΩ
10kΩ

= 2.000mA

I

REF

POT

MSB

B1 B2 B3 B4B5 B6 B7

14

= 2.000mA

LOW T.C.

4.5kΩ
(+) ≈ 2mA

I

REF

≈1V

APPROX

5kΩ

MSB

B1

B2 B3 B4 B5 B6 B7

14

14

15

LSB

B8

I

I

O

O

Figure 27. Recommended Full-Scale Adjustment Circuit

IN

IN

00268-C-024

IO + IO = IFR FOR

E

O

5.000kΩ

4

5.000kΩ

2

E

O

FULL RANGE
HALF SCALE +LSB
HALF SCALE
HALF SCALE –LSB
ZERO SCALE +LSB
ZERO SCALE

Figure 25. Basic Unipolar Negative Operation

LSB

B8

I

I

O

O

10V

10kΩ 10kΩ

4

E

O

2

E

O

POS. FULL RANGE
POS. FULL RANGE –LSB
ZERO SCALE +LSB
ZERO SCALE
ZERO SCALE –LSB
NEG. FULL SCALE +LSB
NEG. FULL SCALE

Figure 26. Basic Bipolar Output Operation

00268-C-028

I

+V

I

FR

LL LOGIC STATES

REF

REF

R

REF

(R14)

R15

+V

255

REF

=

×

R

256

REF

B3

B2

B1

1

1

1

0

0

1

0

0

1

1

1

0

0

0

0

0

0

0

B1

1
1
1
1
0
0
0

–V

Figure 24. Basic Positive Reference Operation

B4

B2

REF

IFS≈

1
0
0
1
0
0

1
1
0
0
1
0
0

V

V

REF

REF

0.1µF

B5

B3

MSB

B1

B2B3 B4 B5 B6 B7

(+)

56789101112

14

(–)

15

316131

V– V+

C

0.1µF

V–

B8

B7

B6

1

1

1

1
1
1
0
0
0

1
1
0
0
1
0
0

–V

R

1

0

0

0

0

0

1

1

1

1

0

0

0

0

0

B4

B5

B6

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

0

0

0

0

0

0

R

REF

14

R15

15

NOTE

REF

R

REF

REF

BIAS CURRENT CANCELLATION.

C

COMP

1.992

1.008

1.000

0.992

0.008

0.000

B7

1
1
0
0
1
0
0

SETS IFS; R15 IS FOR

LSB

B8

I

O

4

2

I

O

FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE:

= 10.000V

V

REF

= 5.000kΩ

R

REF

R15 = R
CC = 0.01µF
V

V

V+

LC

I

I

O

O

0.000

–9.960

0.984

–5.040

0.992

–5.000

1.000

–4.960

1.984

–0.040

1.992

0.000

B8

E

O

–9.920

1

–9.840

0

–0.080

1

0.000

0

+0.080

1

+9.920

1

+10.000

0

= 0V (GROUND)

LC

E

O

–0.000
–4.920
–4.960
–5.000
–9.920
–9.960

E

O

+10.000

+9.920
+0.160
+0.080

0.000
–9.840
–9.920

4

2

REF

E

O

00268-C-027

Figure 28. Basic Negative Reference Operation

I

O

I

O

00268-C-026

00268-C-029

00268-C-025

Rev. C | Page 11 of 20

DAC08

.

.

T

15V

2

10V

REF01*

4

*OR ADR01

5.000kΩ

6

V

O

5

5.0kΩ

+15V –15V

10kΩ

MSB

B1

B2 B3 B4 B5 B6 B7

C

–V

V+

LSB

B8

I

O

4

2

I

V

O

LC

C

Figure 29. Offset Binary Operation

R

L

I

O

4

I

2

FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC)
CONNECT INVERTING INPUT OF OP AMP TO IO (PIN 2): CONNECT IO (PIN 4)
TO GROUND.

AD8671

O

0 TO –I

IFR = I

255
256

E

O

×

R

FR

L

REF

Figure 30. Positive Low Impedance Output Operation

V

= VLC 1.4V

TH

15V CMOS
V

= 7.6V

15V

TH

TTL, DTL,

=1.4V

V

TH

V

LC

1

9.1k

6.2k

Ω

Ω

0.1µF

V

LC

5.0kΩ

+15V

AD8671

–15V

00268-C-031

13k

39k

B1

B2

B3

B4

B5

B6

B7

POS. FULL RANGE

E

ZERO SCALE

O

NEG. FULL SCALE +1LSB
NEG. FULL SCALE

1

1

1

1

1

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

B8

1

1

1

0

0

0

0

0

1

0

0

0

I

O

4

I

O

2

FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC)
CONNECT NONINVERTING INPUT OF OP AMP TO IO (PIN 2): CONNECT IO (PIN 4)

O GROUND.

AD8671

R

0 TO –I

L

IFR = I

Figure 31. Negative Low Impedance Output Operation

V

LC

Ω

CMOS, HTL, NMOS

V+

20k

Ω

2N3904

"A"

20k

Ω

3k

2N3904

Ω

TO PIN 1

V

LC

R3
400

µ

A

"A"

ECL

Ω

2N3904

Ω

2N3904

Ω

3k

TO PIN 1

6.2k

E

O

+4.960

0.000
–4.960
–5.000

255
256

FR

00268-C-030

E

O

×

R

L

REF

00268-C-032

–5.2V

TEMPERATURE COMPENSATING VLC CIRCUITS

00268-C-033

Figure 32. Interfacing with Various Logic Families

Rev. C | Page 12 of 20

DAC08

APPLICATION INFORMATION

REFERENCE AMPLIFIER SETUP

The DAC08 is a multiplying D/A converter in which the output
current is the product of a digital number and the input
reference current. The reference current may be fixed or may
vary from nearly zero to 4.0 mA. The full-scale output current
is a linear function of the reference current and is given by

255

256

REF

= I

14

where I

In positive reference applications, an external positive reference
voltage forces current through R14 into the V
(Pin 14) of the reference amplifier. Alternatively, a negative
reference may be applied to V
flows from ground through R14 into V
reference case. This negative reference connection has the
advantage of a very high impedance presented at Pin 15. The
voltage at Pin 14 is equal to and tracks the voltage at Pin 15 due
to the high gain of the internal reference amplifier. R15 (nomi­nally equal to R14) is used to cancel bias current errors; R15
may be eliminated with only a minor increase in error.

Bipolar references may be accommodated by offsetting V
Pin 15. The negative common-mode range of the reference
amplifier is given by V
The positive common-mode range is V+ less 1.5 V.

When a dc reference is used, a reference bypass capacitor is
recommended. A 5.0 V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a reference,
R14 should be split into two resistors with the junction bypas­sed to ground with a 0.1 µF capacitor.

For most applications, the tight relationship between I
eliminates the need for trimming I
trimming can be accomplished by adjusting the value of R14, or
by using a potentiometer for R14. An improved method of full­scale trimming that eliminates potentiometer T.C. effects is
shown in the recommended full-scale adjustment circuit
(Figure 27).

Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative
common-mode range. The recommended range for operation
with a dc reference current is 0.2 mA to 4.0 mA.

II ×=

REFFR

REF(–)

– = V− plus (I

CM

terminal

REF(+)

at Pin 15; reference current

as in the positive

REF(+)

or

REF

× 1 kΩ) plus 2.5 V.

REF

and IFS

REF

If required, full-scale

REF.

REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS

AC reference applications require the reference amplifier to be
compensated using a capacitor from Pin 16 to V−. The value of
this capacitor depends on the impedance presented to Pin 14;
for R14 values of 1.0 kΩ, 2.5 kΩ, and 5.0 kΩ, minimum values

are 15 pF, 37 pF, and 75 pF. Larger values of R14 require

of C

C

proportionately increased values of C
so the ratio of C

(pF) to R14 (kΩ) = 15.

C

for proper phase margin,

C

For fastest response to a pulse, low values of R14 enabling small

values should be used. If Pin 14 is driven by a high impedance

C

C

such as a transistor current source, none of the preceding values
suffice, and the amplifier must be heavily compensated, which
decreases overall bandwidth and slew rate. For R14 = 1 kΩ and

= 15 pF, the reference amplifier slews at 4 mA/µs, enabling a

C

C

transition from I

= 0 to I

REF

= 2 mA in 500 ns.

REF

Operation with pulse inputs to the reference amplifier can be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (I

= 0) condition. Full-scale transition (0 mA to 2 mA)

REF

occurs in 120 ns when the equivalent impedance at Pin 14 is
200 Ω and C
which is relatively independent of the R

= 0. This yields a reference slew rate of 16 mA/µs,

C

and VIN values.

IN

LOGIC INPUTS

The DAC08 design incorporates a unique logic input circuit
that enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made
possible by the large input swing capability, 2 µA logic input
current, and completely adjustable logic threshold voltage. For
V− = −15 V, the logic inputs may swing between −10 V and
+18 V. This enables direct interface with 15 V CMOS logic, even
when the DAC08 is powered from a 5 V supply. Minimum
input logic swing and minimum logic threshold voltage are
given by

V− + (I

The logic threshold may be adjusted over a wide range by placing
an appropriate voltage at the logic threshold control pin (Pin 1,

). Figure 16 shows the relationship between VLC and VTH

V

LC

over the temperature range, with V
For TTL and DTL interface, simply ground Pin 1. When
interfacing ECL, an I
other logic families, see Figure 32. For general set-up of the
logic control circuit, note that Pin 1 sources 100 µA typical;
external circuitry should be designed to accommodate this
current.

× 1 kΩ) + 2.5 V

REF

= 1 mA is recommended. For interfacing

REF

nominally 1.4 above VLC.

TH

Rev. C | Page 13 of 20

DAC08

Fastest settling times are obtained when Pin 1 sees a low
impedance. If Pin 1 is connected to a 1 kΩ divider, for example,
it should be bypassed to ground by a 0.01 µF capacitor.

ANALOG OUTPUT CURRENTS

Both true and complemented output sink currents are provided

I

O

+

where I
a 1 (logic high) is applied to each logic input. As the binary
count increases, the sink current at Pin 4 increases proportionally,
in the fashion of a positive logic DAC. When a 0 is applied to
any input bit, that current is turned off at Pin 4 and turned on at
Pin 2. A decreasing logic count increases
inverted logic DAC. Both outputs may be used simultaneously.
If one of the outputs is not required, it must be connected to
ground or to a point capable of sourcing I
unused output pin open.

Both outputs have an extremely wide voltage compliance
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive compli­ance is 36 V above V− and is independent of the positive supply.
Negative compliance is given by

V− + (I

The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection and
in other balanced applications such as driving center-tapped
coils and transformers.

POWER SUPPLIES

The DAC08 operates over a wide range of power supply
voltages from a total supply of 9 V to 36 V. When operating at
supplies of ±5 V or lower, I
reference current operation decreases power consumption and
increases negative compliance (Figure 11), reference amplifier
negative common-mode range (Figure 14), negative logic input
range (Figure 15), and negative logic threshold range (Figure 16).
For example, operation at −4.5 V with I
recommended because negative output compliance would be
reduced to near zero. Operation from lower supplies is possible;
however, at least 8 V total must be applied to ensure turn-on of
the internal bias network.

Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible because no ground connection is required: however, an
artificial ground may be used to ensure logic swings, etc., remain
between acceptable limits. Power consumption is calculated as
follows:

A useful feature of the DAC08 design is that supply current is
constant and independent of input logic states. This is useful in

= IFS. Current appears at the true (IO) output when

O

I

O

as in a negative or

; do not leave an

FS

× 1 kΩ) + 2.5 V

REF

≤ 1 mA is recommended. Low

REF

= 2 mA is not

REF

()( )()( )

D

−−+++= VIVIP

cryptographic applications and further reduces the size of the
power supply bypass capacitors.

TEMPERATURE PERFORMANCE

The nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating tempera­ture range. Full-scale output current drift is low, typically
±10 ppm/°C, with zero-scale output current and drift essentially
negligible compared to 1/2 LSB.

The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approxi­mately 10% at –55°C. At +125°C, an increase of about 15% is
typical.

The reference amplifier must be compensated by using a
capacitor from Pin 16 to V−. For fixed reference operation, a

0.01 µF capacitor is recommended. For variable reference
applications, refer to the Reference Amplifier Compensation for
Multiplying Applications section.

MULTIPLYING OPERATION

The DAC08 provides excellent multiplying performance with
an extremely linear relationship between I

and I

FS

over a

REF

range of 4 µA to 4 mA. Monotonic operation is maintained over
a typical range of I

from 100 µA to 4.0 mA.

REF

SETTLING TIME

The DAC08 is capable of extremely fast settling times, typically
85 ns at I
board layout must be used to obtain full performance potential
during testing and application. The logic switch design enables
propagation delays of only 35 ns for each of the 8 bits. Settling
time to within 1/2 LSB of the LSB is therefore 35 ns, with each
progressively larger bit taking successively longer. The MSB
settles in 85 ns, thus determining the overall settling time of
85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.
The output capacitance of the DAC08, including the package, is
approximately 15 pF; therefore the output RC time constant
dominates settling time if R

Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for I
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.

Measuring the settling time requires the ability to accurately
resolve ±4 µA; therefore a 1 kΩ load is needed to provide
adequate drive for most oscilloscopes. The settling time fixture
shown in Figure 33 uses a cascade design to permit driving a
1 kΩ load with less than 5 pF of parasitic capacitance at the
measurement node. At I

= 2.0 mA. Judicious circuit design and careful

REF

> 500 Ω.

L

values. The principal advantage of higher I

REF

values of less than 1.0 mA, excessive

REF

REF

Rev. C | Page 14 of 20

DAC08

+

RC damping of the output is difficult to prevent while main­taining adequate sensitivity. However, the major carry from
01111111 to 10000000 provides an accurate indicator of settling
time. This code change does not require the normal 6.2 time
constants to settle to within ±0.2% of the final value, and thus
settling time is observed at lower values of I

REF

.

DAC08 switching transients or “glitches” are very low and can
be further reduced by small capacitive loads at the output at a

V

V

0.7V

REF

FORTURN-ON,V
FORTURN-OFF,VL=0.7V

CL

V

R

R15

REF

0.1µF

14

15

0.1µF

513678 9 10 11 12

+15V

IN

DAC08

316

–15V

L

MINIMUM

CAPACITANCE

4

2

0.01µF

0.1µF

Figure 33. Settling Time Measurement

=2.7V

I

OUT

minor sacrifice in settling time. Fastest operation can be
obtained by using short leads, minimizing output capacitance
and load resistor values, and by adequate bypassing at the
supply, reference, and V

terminals. Supplies do not require

LC

large electrolytic bypass capacitors because the supply current
drain is independent of input logic states; 0.1 µF capacitors at
the supply pins provide full transient protection.

Q1

V

L

1kΩ

1µF

1kΩ

2kΩ100kΩ

50µF

1µF

+5V

Q2

–15V

15kΩ

V

OUT

PROBE

1

×

+0.4V

0V
0V

–0.4V

0.1µF

00268-C-034

Rev. C | Page 15 of 20

DAC08

ADI CURRENT OUTPUT DACS

Table 4 lists the latest DACS available from Analog Devices.

Table 4.

Model Bits Outputs Interface Package Comments

AD5425 8 1 SPI, 8-bit load MSOP-10 Fast 8-bit load; see also AD5426
AD5426 8 1 SPI MSOP-10 See also AD5425 fast load
AD5450 8 1 SPI SOT23-8 See also AD5425 fast load
AD5424 8 1 Parallel TSSOP-16
AD5429 8 2 SPI TSSOP-16
AD5428 8 2 Parallel TSSOP-20
AD5432 10 1 SPI MSOP-10
AD5451 10 1 SPI SOT23-8
AD5433 10 1 Parallel TSSOP-20
AD5439 10 2 SPI TSSOP-16
AD5440 10 2 Parallel TSSOP-24
AD5443 12 1 SPI MSOP-10 See also AD5452 and AD5444
AD5452 12 1 SPI SOT23-8 Higher accuracy version of AD5443; see also AD5444
AD5445 12 1 Parallel TSSOP-20
AD5444 12 1 SPI MSOP-10 Higher accuracy version of AD5443; see also AD5452
AD5449 12 2 SPI TSSOP-16
AD5415 12 2 SPI TSSOP-24 Uncommitted resistors
AD5447 12 2 Parallel TSSOP-24
AD5405 12 2 Parallel LFCSP-40 Uncommitted resistors
AD5453 14 1 SPI SOT23-8
AD5553 14 1 SPI MSOP-8
AD5556 14 1 Parallel TSSOP-28
AD5446 14 1 SPI MSOP-10 MSOP version of AD5453; compatible with AD5443, AD5432, AD5426
AD5555 14 2 SPI TSSOP-16
AD5557 14 2 Parallel TSSOP-38
AD5543 16 1 SPI MSOP-8
AD5546 16 1 Parallel TSSOP-28
AD5545 16 2 SPI TSSOP-16
AD5547 16 2 Parallel TSSOP-38

Rev. C | Page 16 of 20

DAC08

OUTLINE DIMENSIONS

0.785 (19.94)

0.765 (19.43)

0.745 (18.92)

16
1

0.100 (2.54)
BSC

0.015 (0.38)

0.180 (4.57)
MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095AC

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

Figure 34. 16-Lead PDIP (N-16)

Dimensions shown in inches and (mm)

10.00 (0.3937)

9.80 (0.3858)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

16

1

BSC

0.51 (0.0201)

0.31 (0.0122)

1.75 (0.0689)

1.35 (0.0531)

1.27 (0.0500)

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MS-012AC

Figure 36. 16-Lead SOIC (R-16A)

Dimensions shown in inches and (mm)

9
8

MIN

9

6.20 (0.2441)

5.80 (0.2283)

8

SEATING
PLANE

0.295 (7.49)

0.285 (7.24)

0.275 (6.99)

SEATING
PLANE

0.25 (0.0098)

0.17 (0.0067)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

8°
0°

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

× 45°

0.005

(0.13)

MIN

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.098 (2.49)
MAX

16

PIN 1

18

0.840 (21.34) MAX

0.100
(2.54)

BSC

9

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81)
MIN

SEATING
PLANE

Figure 35. 16-Lead CERDIP (Q-16)

Dimensions shown in inches and (mm)

0.075 (1.91)

0.100 (2.54)

0.064 (1.63)

0.358 (9.09)

0.342 (8.69)
SQ

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.358

(9.09)

MAX

0.088 (2.24)

0.054 (1.37)

SQ

0.095 (2.41)

0.075 (1.90)

0.011 (0.28)

0.007 (0.18)
R TYP

0.075 (1.91)
REF

0.055 (1.40)

0.045 (1.14)

REF

19

18

14

13

20

1

BOTTOM

VIEW

0.150 (3.81)
BSC

Figure 37. 20-Terminal Leadless Chip Carrier (E-20)

Dimensions shown in inches and (mm)

0.320 (8.13)

0.290 (7.37)

15°

0°

0.200 (5.08)
REF

0.100 (2.54) REF

0.015 (0.38)
MIN

3

4

0.028 (0.71)

0.022 (0.56)

0.050 (1.27)

8

BSC

9

45° TYP

0.015 (0.38)

0.008 (0.20)

Rev. C | Page 17 of 20

DAC08

ORDERING GUIDE

1

Model

DAC08AQ ±0.10%
DAC08AQ/883C2±0.10%
DAC08HP ±0.10% 0°C to 70°C PDIP-16 N-16 25
DAC08HQ ±0.10% 0°C to 70°C CERDIP-16 Q-16 25
DAC08Q ±0.19%
DAC08RC/883C2±0.19%
DAC08EP ±0.19% 0°C to 70°C PDIP-16 N-16 25
DAC08EQ ±0.19% 0°C to 70°C CERDIP-16 Q-16 25
DAC08ES ±0.19% 0°C to 70°C SOIC-16 R-16A (Narrow Body) 47
DAC08ES-REEL ±0.19% 0°C to 70°C SOIC-16 R-16A (Narrow Body) 2500
DAC08ESZ

3

DAC08ESZ-REEL3±0.19% 0°C to 70°C SOIC-16 R-16A (Narrow Body) 2500
DAC08CP ±0.39%
DAC08CPZ

3

DAC08CS ±0.39%
DAC08CS-REEL ±0.39%
DAC08CSZ

3

DAC08CSZ-REEL3±0.39%

1

Devices processed in total compliance to MIL-STD-883. Consult the factory for the 883 data sheet.

2

For availability and burn-in information on the SOIC and PLCC packages, contact your local sales office.

3

Z = Pb-free part.

NL Temperature Range Package Description Package Option No. Parts Per Container

−55°C to +125°C

−55°C to +125°C

−55°C to +125°C

−55°C to +125°C

CERDIP-16 Q-16 25
CERDIP-16 Q-16 25

CERDIP-16 Q-16 25
LCC-20 E-20 55

±0.19% 0°C to 70°C SOIC-16 R-16A (Narrow Body) 47

PDIP-16 N-16 25
PDIP-16 N-16 25
SOIC-16 R-16A (Narrow Body) 47
SOIC-16 R-16A (Narrow Body) 2500
SOIC-16 R-16A (Narrow Body) 47
SOIC-16 R-16A (Narrow Body) 2500

±0.39%

±0.39%

−40°C to +85°C

−40°C to +85°C

−40°C to +85°C

−40°C to +85°C

−40°C to +85°C

−40°C to +85°C

Rev. C | Page 18 of 20

DAC08

NOTES

Rev. C | Page 19 of 20

DAC08

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C00268–0–11/04(C)

Rev. C | Page 20 of 20