Datasheet E28F016SA-150, E28F016SA-120, E28F016SA-100, E28F016SA-080, E28F016SA-070 Datasheet (Intel Corporation)

E







28F016SA 16-MBIT

(1 MBIT X 16, 2 MBIT X 8)

FlashFile™ MEMORY

Includes Commercial and Extended Temperature Specifications

n

User-Selectable 3.3V or 5V V

n

User-Configurable x8 or x16 Operation

n

70 ns Maximum Access Time

n

28.6 MB/sec Burst Write Transfer Rate

n

1 Million Typical Erase Cycles per
Block

n

56-Lead, 1.2 mm x 14 mm x 20 mm
TSOP Package

n

56-Lead, 1.8 mm x 16 mm x 23.7 mm
SSOP Package

Intel’s 28F016SA 16-Mbit FlashFile™ memory is a revolutionary architect ure which is the ideal choice f or
designing embedded direct-execut e code and mass s torage data/fi le flash mem ory systems. With innovative
capabilities, low-power, extended temperat ure operation and high read/program performance, the 28F016SA
enables the design of truly mobile, high-performance communications and computing products.

The 28F016SA is the highest dens ity, highest performance nonv olatile read/program sol ution for solid-s tate
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit
FlashFile memory), extended cy cling, extended temperature operation, flexible V
performance and selectiv e block locking provide highly flexibl e memory components suitable for Resident
Flash Arrays, high-density mem ory cards and PCMCIA-ATA flas h drives. The 28F016SA dual read voltage
enables the design of memory cards which can be int erchangeably read/written i n 3.3V and 5.0V systems. Its
x8/x16 architecture al lows optimizat ion of the memory-t o-processor interfac e. Its high read perform ance and
flexible block locking enable both storage and execution of operating systems and application software.
Manufactured on Intel’s 0.6 µm ETOX IV process technology, the 28F016SA is the most cost-effective,
highest density monolithic 3.3V FlashFile memory.

CC

n

Revolutionary Architecture

Pipelined Command Execution
Program during Erase
Command Superset of Intel
28F008SA

n

1 mA Typical ICC in Static Mode

n

1 µA Typical Deep Power-Down

n

32 Independently Lockable Blocks

n

State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology

, fast program and read

CC

November 1996 Order Number: 290489-004

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

COPYRIGHT © INTEL CORPORATION, 1996 CG-041493

E 28F016SA

CONTENTS

PAGE PAGE

1.0 INTRODUCTION.............................................5

1.1 Product Overview ........................................5

2.0 DEVICE PINOUT.............................................6

2.1 Lead Descriptions........................................8

3.0 MEMORY MAPS...........................................12

3.1 Extended Status Register Memory Map..... 13

4.0 BUS OPERATIONS, COMMANDS AND

STATUS REGISTER DEFINITIONS.............14

4.1 Bus Operations for Word-Wide Mode
(BYTE# = V

4.2 Bus Operations for Byte-Wide Mode
(BYTE# = V

4.3 28F008SA–Compatible Mode Command

Bus Definitions..........................................15

4.4 28F016SA–Performance Enhancement

Command Bus Definitions.........................16

4.5 Compatible Status Register ....................... 18

4.6 Global Status Register...............................19

4.7 Block Status Register ................................20

5.0 ELECTRICAL SPECIFICATIONS.................21

5.1 Absolute Maximum Ratings ....................... 21

5.2 Capacitance...............................................22

5.3 Timing Nomenclature................................. 23

5.4 DC Characteristics (V

5.5 DC Characteristics

= 5.0V ± 10%, 5.0V ± 5%)................29

(V

CC

)........................................... 14

IH

)...........................................14

IL

= 3.3V ± 10%)..... 26

CC

5.6 AC Characteristics–Read Only

Operations.................................................32

5.7 Power-Up and Reset Timings.....................37

5.8 AC Characteristics for WE#–Controlled

Command Write Operations......................38

5.9 AC Characteristics for CE#–Controlled

Command Write Operations......................42

5.10 AC Characteristics for Page Buffer Write

Operations.................................................46

5.11 Erase and Word/Byte Program
Performance, Cycling Performance and

Suspend Latency.......................................49

6.0 DERATING CURVES.....................................50

7.0 MECHANICAL SPECIFICATIONS FOR

TSOP............................................................52

8.0 MECHANICAL SPECIFICATIONS FOR

SSOP............................................................53

APPENDIX A: Device Nomenclature and

Ordering Information ..................................54

APPENDIX B: Additional Information...............55

3

28F016SA E

REVISION HISTORY

Number Description

-001 Original Version

-002 — Added 56-Lead SSOP Package

-003

-004

— Separated AC Reading Timing Specs t

Reads
— Modified Device Nomenclature
— Added Ordering Information
— Added Page Buffer Typical Program Performance numbers
— Added Typical Erase Suspend Latencies
— For I

(Deep Power-Down current) BYTE# must be at CMOS levels

CCD

— Added SSOP package mechanical specifications
— Revised document status from “Advanced Information” to “Preliminary”

— Section 5.11: Renamed specification “Erase Suspend Latency Time to Program” as
“Auto Erase Suspend Latency Time to Program”

— Section 5.7: Added specifications t
— TSOP dimension A1 = 0.05 mm (min)
— SSOP dimension B = 0.40 mm (max)
— Minor cosmetic changes

Update:
—Changed Deep Power Down Current
— Changed Standby Current
— Changed Sleep Mode Current
Combined Commercial and Extended Temperature information into single datasheet

PHEL3

AVEL

, t

, t

for Extended Status Register

AVGL

PHEL5

4

E 28F016SA

1.0 INTRODUCTION

The documentation of the Int el 28F016SA memory

device includes this datasheet, a detailed user’s
manual, and a number of application notes, all of
which are referenced at the end of this datasheet.

The datasheet is intended to give an overview of the
chip feature-set and of the operating AC/DC
specifications.

User’s Manual

the user modes, system interface examples and
detailed descriptions of all principles of operation. It
also contains the full list of software algorithm
flowcharts, and a brief sect ion on compatibility with
Intel 28F008SA.

The 16-Mbit Flash Product Family

provides complete descriptions of

1.1 Product Overview

The 28F016SA is a high-performance 16-Mbit
(16,777,216 bit) block erasable nonvolati le random
access memory organized as either 1 Mword x
16 or 2 Mbyte x 8. The 28F016SA i ncludes thirty­two 64-KB (65,536) blocks or thirty-two 32-KW
(32,768) blocks. A chip memory map is shown in
Figure 4.

The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and results in greater
product reliability and ease-of-use.

Among the significant enhancements on the
28F016SA:

• 3.3V Low Power Capability

• Improved Program Performance

• Dedicated Block Program/Erase Protection

A 3/5# input pin reconfigures the device internally
for optimized 3.3V or 5.0V read/program operation.

The 28F016SA will be available in a 56-lead,

1.2 mm thick, 14 mm x 20 mm TSOP type I
package or a 56-lead, 1.8 mm thick, 16 mm x

23.7 mm SSOP package. The TSOP form factor
and pinout allow for very high board layout
densities. SSOP packaging provides relaxed lead
spacing dimensions.

A Command User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.

Internal algorithm automation allows word/byte
programs and block erase operations to be
executed using a two-write c ommand sequence to
the CUI in the same way as the 28F008SA 8-Mbit
FlashFile memory.

A superset of commands have been added to t he
basic 28F008SA command-set to achieve higher
program performance and provide additional
capabilities. These new commands and features
include:

• Page Buffer Writes to Flash

• Command Queueing Capability

• Automatic Data Programs during Erase

• Software Locking of Memory Blocks

• Two-Byte Successive Programs in 8-bit

Systems

• Erase All Unlocked Blocks
Writing of memory data is performed in either byte

or word increments typically within 6 µs, a 33%
improvement over the 28F008SA. A block erase
operation erases one of the 32 blocks in typically

0.6 sec, independent of the ot her blocks, which is a
65% improvement over the 28F008SA.

Each block can be writt en and erased a mini mum of
100,000 cycles. Systems can achieve typically one­million block erase cycles by providing wear-leveling
algorithms and graceful block retirement. These
techniques have already been employed in many
flash file systems. Additionally, wear leveling of
block erase cycles can be used to minimize the
program/erase performance differences across
blocks.

The 28F016SA incorporates two Page Buffers of
256 bytes (128 words) each to allow page data
writes. This feature can improve a system write
performance by up to 4.8 t imes over previ ous flash
memory devices.

All operations are started by a sequence of
command writes to the device. Three Status
Registers (described in detai l later) and a RY/BY#
output pin provide information on the progress of
the requested operation.

While the 28F008SA requires an operation to
complete before the next operation can be
requested, the 28F016SA allows queueing of the
next operation while the memory executes the
current operation. This elim inates system overhead

5

28F016SA E

when writing several bytes in a row to the array or
erasing several blocks at the same time. The
28F016SA can also perform program operations to
one block of memory while performing erase of
another block.

The 28F016SA provides user-selectable block
locking to protect code or data such as device
drivers, PCMCIA card i nformation, ROM -executable
O/S or application code. Each block has an
associated nonvolatil e loc k-bit whic h det ermines the
lock status of t he block. In addition, the 28F016SA
has a master Write Protect pin (WP#) which
prevents any modifications to memory blocks
whose lock-bits are set.

The 28F016SA contains three types of Status
Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile

memory’s Status Register. This register, when
used alone, provides a straight forward upgrade
capability to the 28F016SA from a 28F008SA­based design.

• A Global Status Regist er (GSR) which informs
the system of Command Queue status, Page
Buffer status, and ov erall Write State Machine
(WSM) status.

• 32 Block Status Regi s ters (BSRs) which provide
block-specific status information such as the
block lock-bit status.

The GSR and BSR memory maps for by te-wi de and
word-wide modes are shown in Figures 5
and 6.

The 28F016SA incorporates an open drain RY/BY #
output pin. This feature allows the user to OR-tie
many RY/BY# pins together in a multiple memory
configuration such as a Resident Flash Array.

Other configurations of t he RY/BY# pin are enabled
via special CUI commands and are described in
detail in the

16-Mbit Flash Product Family User’s

Manual.

The 28F016SA also incorporates a dual c hip-enable
function with two input pins, CE

# and CE1#. These

0

pins have exactly the same functionality as the
regular chip-enable pin CE# on the 28F008SA. For
minimum chip designs, CE
to use CE

# as the chip enable input. The

0

# may be tied to ground

1

28F016SA uses the logical combination of these
6

two signals to enable or disable the entire chip. Both
CE

# and CE1# must be active low to enable the

0

device and, if either one becomes i nactive, the c hip
will be disabled. This feature, along with the open
drain RY/BY# pin, allows the system designer to
reduce the number of control pins used in a large
array of 16-Mbit devices.

The BYTE# pin allows either x8 or x16
read/programs to the 28F016SA. BYTE# at logic
low selects 8-bit mode with address A

selecting

0

between low byte and high byte. On the other hand,
BYTE# at logic high enables 16-bit operation with
address A
address A

becoming the lowest order addres s and

1

is not used (don’t care). A device bl ock

0

diagram is shown in Figure 1.
The 28F016SA is specified f or a maximum access

time of 70 ns (t

) at 5.0V operation (4.75V to

ACC

5.25V) over the commercial temperature range
(0°C to +70°C). A corresponding m aximum access
time of 120 ns at 3.3V (3.0V to 3.6V and 0°C to
+70°C) is achieved for reduced power c onsumption
applications.

The 28F016SA incorporates an Automatic Power
Saving (APS) feature which substantially reduces
the active current when the device is in the static
mode of operation (addresses not switching).

In APS mode, the typical I

current is 1 mA at 5.0V

CC

(0.8 mA at 3.3V).
A deep power-down mode of operation is invoked

when the RP# (called PWD# on the 28F008SA) pin
transitions low. This mode brings the device power
consumption to less than 1.0 µA, typically, and
provides additional write protection by acting as a
device reset pin during power transitions. A reset
time is required from RP# switching high until
outputs are again valid. In the deep power-down
state, the WSM is reset (any current operation will
abort) and the CSR, GSR and BSR registers are
cleared.

A CMOS standby mode of operation is enabled
when either CE

# or CE1# transitions high and RP #

0

stays high with all input control pins at CMOS
levels. In this m ode, the device typically draws an
I

standby current of 50 µA.

CC

2.0 DEVICE PINOUT

The 28F016SA 56-lead TSOP Type I pinout
configuration is shown in
SSOP pinout configuration is shown in Figure 3.

Figure 2. The 56-lead

E 28F016SA

#

Output

Buffer

DQ

8-15

Output

Buffer

DQ

ID

Register

CSR

0-7

Input

Buffer

Data

Queue

Registers

Page

Buffers

Input

Buffer

I/O Logic

3/5#
BYTE#

Output Multiplexer

ESRs

0-20

A

Input

Buffer

Y

Decoder

Data

Comparator

Y Gating/Sensing

CUI

CE0

CE1#

OE#
WE#
WP#

RP#

Address

Queue

Latches

Address
Counter

X

Decoder

Program/Erase
Voltag e S witch

Block 1

Block 0

64-Kbyte

64-Kbyte

Block 30

Block 31

64-Kbyte

64-Kbyte

WSM

RY/BY#

V

3/5#

V

CC

GND

PP

Figure 1. 28F016SA Block Diagram

Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers

0489_01

7

28F016SA E

2.1 Lead Descriptions

Symbol Type Name and Function

A

0

A

1–A15

A

16–A20

DQ

0–DQ7

DQ

8–DQ15

CE0#,CE1# INPUT CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,

RP# INPUT RESET/POWER-DOWN: RP# low places the device in a deep power-

OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when

WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue

INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the

device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A

input buffer is turned off when BYTE# is

0

high).

INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.

A

selects 1 of 1024 rows, and A

6–15

selects 16 of 512 columns. These

1–5

addresses are latched during data programs.

INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks. These

addresses are latched during data programs, block erase and lock block
operations.

INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write

cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is deselected or the outputs are
disabled.

INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program

operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is
deselected or the outputs are disabled.

decoders and sense amplifiers. With either CE

# or CE1# high, the device

0

is deselected and power consumption reduces to standby levels upon
completion of any current data program or block erase operations. Both
CE

#, CE1# must be low to select the device.

0

All timing specifications are the same for both signals. Device selection
occurs with the latter falling edge of CE
CE

# or CE1# disables the device.

0

# or CE1#. The first rising edge of

0

down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).

low. The outputs float to tri-state off when OE# is high.

NOTE:

CEx# overrides OE#, and OE# overrides WE#.

Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.

Page Buffer addresses are latched on the falling edge of WE#.

8

E 28F016SA

2.1 Lead Descriptions (Continued)

Symbol Type Name and Function

RY/BY# OPEN DRAIN

WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile

BYTE# INPUT BYTE ENABLE: BYTE# low places device in x8 mode. All data is then

3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V

V

PP

V

CC

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY:

NC NO CONNECT:

OUTPUT

SUPPLY ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks

SUPPLY DEVICE POWER SUPPLY (3.3V ± 10%, 5.0V ± 10%, 5.0V ± 5%):

READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY/BY# high
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or block erase is suspended, or the
device is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE# or CE
RY/BY# Pin Disable command is issued.

lock-bit for each block. When WP# is low, those locked blocks as
reflected by the Block-Lock Status bits (BSR.6), are protected from
inadvertent data programs or block erases. When WP# is high, all blocks
can be written or erased regardless of the state of the lock-bits. The WP#
input buffer is disabled when RP# transitions low (deep power-down
mode).

input or output on DQ
the high and low byte. BYTE# high places the device in x16 mode, and
turns off the A
address.

operation. 3/5# low configures internal circuits for 5.0V operation.

Reading the array with 3/5# high in a 5.0V system could damage the
device.
There is a significant delay from 3/5# switching to valid data.

or writing words/bytes/pages into the flash array.

Do not leave any power pins floating.

Do not leave any ground pins floating.

Lead may be driven or left floating.

input buffer. Address A1 then becomes the lowest order

0

, and DQ

0–7

#,CE1# are high), except if a

0

float. Address A

8–15

NOTES:

selects between

0

9

28F016SA E

28F032SA 28F016SV 28F032SA28F016SV

3/5#

CE #

1

CE #

2

A
A
A
A
A

V

CC

A
A
A
A

CE #

0

V

PP

RP#

A
A

A
A

GND

A
A
A
A
A
A
A

3/5#

3/5#

CE #

CE #

1

NCNC NC

NC

A
A
A
A
A
V

CC

A
A
A
A

CE #

V

RP#

A
A

A
A

GND

A
A
A
A
A
A
A

A

20

A

19

A

18

A

17

A

16

V
A

15

A

14

A

13

A

12

CE #

0

V

PP

RP#

A

11

A

10

9
8

GND

7
6
5
4
3
2
1

20
19
18
17
16

15
14
13
12

11
10

9
8

7
6
5
4
3
2
1

1
2

1

3

4

20

5

19

6

18

7

17

8

16

9

CC

10

15

11

14

12

13

13

12

14

0

15

PP

16
17

11

18

10

19

A

9

20

A

8

21
22

A

7

23

A

6

24

A

5

A

25

4

26

A

3

27

A

2

28

A

1

E28F016SA

56-LEAD TSOP PINOUT

1.2 mm x 14 mm x 20 mm
TOP VIEW

NOTE:

56-Lead TSOP Mechanical Diagrams and Dimensions are shown at the end of this specification.

Figure 2. TSOP Pinout Configuration

56

WP#

55

WE#

54

OE#

53

RY/BY#

52

DQ15DQ15DQ

51

DQ

50

DQ14DQ14DQ

49

DQ

48

GND

47

DQ

46

DQ5DQ5DQ

45

DQ

44

DQ4DQ4DQ

43

V

42

GND

41

DQ11DQ11DQ

40

DQ

39

DQ10DQ10DQ

38

DQ

37

V

36

DQ

35

DQ

34

DQ

33

DQ

32

A0A

31

BYTE#

30

NC

29

NC

WP#

WP#

WE#

WE#

OE#

OE#

RY/BY#

RY/BY#

15

DQ

DQ

7

DQ

6

GND
DQ

13

DQ

12

V

CC

GND
DQ

3

DQ

2

V

CC

DQ

9

DQ

1

DQ

8

DQ

0

BYTE#
NC
NC

7

7

14

DQ

6

6

GND
DQ

13

13

5

DQ

12

12
4

V

CC

CC

GND

11

DQ

3

3

10

DQ

2

2

V

CC

CC

DQ

9

9

DQ

1

1

DQ

8

8

DQ

0

0

A

0

0

BYTE#
NC
NC

0489_02

10

E 28F016SA

28F016SV

CE #

0

A

12

A

13

A

14

A

15

3/5#

CE #

1

NC

A

20

A

19

A

18

A

17

A

16

V

CC

GND

DQ

6

DQ

14

DQ

7

DQ

15

RY/BY#

OE#
WE#
WP#

DQ

13

DQ

5

DQ

12

DQ

4

V

CC

CE #

0

A

12

A

13

A

14

A

15

3/5#

CE #

1

NC
A

20

A

19

A

18

A

17

A

16

V

CC

GND

DQ
DQ

14

DQ
DQ

15

RY/BY#

OE#
WE#

WP#
DQ
DQ
DQ
DQ

V

CC

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

6

DA28F016SA
56-LEAD SSOP

STANDARD PINOUT

1.8 mm x 16 mm x 23.7 mm
TOP VIEW

17
18

7

19
20

21
22
23
24

13

25

5

26

12

27

4

28

56
55

54
53
52
51
50

49
48
47
46

45
44

43
42
41
40
39

38
37
36
35
34
33
32
31
30
29

V
RP#

A
A
A
A
A

A
A
A
A

A
GND

A
V
DQ
DQ
DQ

DQ
A
BYTE#
NC
NC
DQ

DQ
DQ
DQ
GND

V

PP

PP

RP#
A

11
10
9
1
2
3
4
5
6
7

11

A

10

A

9

A

1

A

2

A

3

A

4

A

5

A

6

A

7

GND
A

8

8

V

CC

CC

DQ
DQ
DQ
DQ
A

9
1
8
0

0

9
1
8
0

0

BYTE#

NC
NC

DQ
DQ

DQ
DQ

2
10
3
11

2
10
3
11

GND

0489_17

28F016SV

Figure 3. SSOP Pinout Configuration

11

28F016SA E

3.0 MEMORY MAPS

A

[20-0]

1FFFFF

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

0489_03

12

Figure 4. 28F016SA Memory Map (Byte-Wide Mode)

E 28F016SA

3.1 Extended Status Register Memory Map

x8 MODE A[20-0]

RESERVED

GSR

RESERVED

BSR 31

RESERVED
RESERVED

1F0006H
1F0005H
1F0004H
1F0003H

1F0002H
1F0001H
1F0000H

.
.
.

010002H

RESERVED

000006H

RESERVED

GSR

RESERVED

BSR 0
RESERVED
RESERVED

000005H
000004H

000003H
000002H

000001H
000000H

0489_04

x16 MODE A[20-1]

RESERVED

GSR

RESERVED

BSR 31

RESERVED

RESERVED

F8003H

F8002H

F8001H

F8000H

.
.
.

08001H

RESERVED

00003H

RESERVED

GSR

RESERVED

BSR 0

RESERVED
RESERVED

00002H

00001H

00000H

0489_05

Figure 5. Extended Status Register Memory

Map (Byte-Wide Mode)

Figure 6. Extended Status Register Memory

Map (Word-Wide Mode)

13

28F016SA E

4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS

4.1 Bus Operations for Word-Wide Mode (BYTE# = V

Mode Notes RP# CE1#CE0# OE# WE# A

Read 1,2,7 V
Output Disable 1,6,7 V
Standby 1,6,7 V

Deep Power-Down 1,3 V
Manufacturer ID 4 V
Device ID 4 V
Write 1,5,6 V

V

IH

V

IH

V

IH

V
V

IL

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

V

IH

V

IH

V

IL
IL
IH

IL
IH

IL

V

IH

X X X High Z X

XXXXXHigh Z V

V

IL

V

IL

V

IL

V

IL
IL
IL

IL

V

IL

V

IH

)

IH

DQ

1

V

IH

V

IH

V

IH

V

IH

V

XD
X High Z X

V

IL

V

IH

XDINX

IL

OUT

0089H V
66A0H V

0–15

RY/BY#

X

OH
OH
OH

4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE1#CE0# OE# WE# A

Read 1,2,7 V
Output Disable 1,6,7 V
Standby 1,6,7 V

Deep Power-Down 1,3 V
Manufacturer ID 4 V
Device ID 4 V
Write 1,5,6 V

NOTES:

1. X can be V

2. RY/BY# output is open drain. When the WSM is ready, block erase is suspended or the device is in deep power-down
mode. RY/BY# will be at V
operation is in progress.

3. RP# at GND ± 0.2V ensures the lowest deep power-down current.

4. A

and A1 at VIL provide manufacturer ID codes in x8 and x16 modes, respectively. A0 and A1 at VIH provide device ID

0

codes in x8 and x16 modes, respectively. All other addresses are set to zero.

5. Commands for different block erase operations, data program operations or lock-block operations can only be successfully
completed when V

6. While the WSM is running, RY/BY# in level-mode (default) stays at V
V

OH

7. RY/BY# may be at V
data program operation.

or VIL for address or control pins except for RY/BY#, which is either VOL or VOH.

IH

if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM

OH

= V

.

PP

PPH

when the WSM is not busy or in erase suspend mode.

while the WSM is busy performing various operations; for example, a Status Register read during a

OL

V

IH

V

IH

V

IH

V
V

IL

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

V

IH

V

IH

V

IL

V

IL

IH

IL

IH

V

IL
IH

IH

V

IH

X X X High Z X

XXXXXHigh Z V

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

OL

V

IL
IL
IH

until all operations are complete. RY/BY# goes to

IH

V

IH

V

IL

DQ

0

XD

0–7

OUT

RY/BY#

X High Z X

V
V

IL

IH

89H V
A0H V

XDINX

X

OH
OH
OH

14

E 28F016SA

4.3 28F008SA–Compatible Mode Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data

Read Array Write X xxFFH Read AA AD
Intelligent Identifier 1 Write X xx90H Read IA ID
Read Compatible Status Register 2 Write X xx70H Read X CSRD
Clear Status Register 3 Write X xx50H
Word/Byte Program Write X xx40H Write PA PD
Alternate Word/Byte Program Write X xx10H Write PA PD
Block Erase/Confirm Write X xx20H Write BA xxD0H
Erase Suspend/Resume Write X xxB0H Write X xxD0H

ADDRESS DATA

A = Array Address AD = Array Data
BA = Block Address CSRD = CSR Data
IA = Identifier Address ID = Identifier Data
PA = Program Address PD = Program Data

X = Don’t Care

NOTES:

1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters data program, block erase, or suspend operations.

3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits.

4. The upper byte of the data bus (DQ

) during command writes is a “Don’t Care” in x16 operation of the device.

8–15

(4)

Oper Addr Data

See Status Register definitions.

15

28F016SA E

4.4 28F016SA–Performance Enhancement Command Bus Definitions

First Bus Cycle Second Bus Cycle Third Bus Cycle

Command Mode Notes Oper Addr Data

Read Extended
Status Register

Page Buffer Swap 7 Write X xx72H
Read Page Buffer Write X xx75H Read PBA PD
Single Load to Page

Buffer
Sequential Load to

Page Buffer

Page Buffer Write to
Flash

Two-Byte Program x8 3 Write X xxFBH Write A0WD(L,H) Write PA WD(H,L)
Lock Block/Confirm Write X xx77H Write BA xxD0H
Upload Status

Bits/Confirm
Upload Device

Information
Erase All Unlocked

Blocks/Confirm
RY/BY# Enable to

Level-Mode
RY/BY# Pulse-On-

Write
RY/BY# Pulse-On-

Erase
RY/BY# Disable 8 Write X xx96H Write X xx04H
Sleep 11 Write X xxF0H
Abort Write X xx80H

x8 4,6,10 Write X xxE0H Write X BCL Write X BCH

x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH

x8 3,4,9,10 Write X xx0CH Write A0BC(L,H) Write PA BC(H,L)

x16 4,5,10 Write X xx0CH Write X WCL Write PA WCH

1 Write X xx71H Read RA GSRD

Write X xx74H Write PBA PD

2 Write X xx97H Write X xxD0H

Write X xx99H Write X xxD0H

Write X xxA7H Write X xxD0H

8 Write X xx96H Write X xx01H

8 Write X xx96H Write X xx02H

8 Write X xx96H Write X xx03H

(12)

Oper Addr Data

BSRD

(12)

Oper Addr Data

ADDRESS DATA

BA = Block Address AD = Array Data WC (L,H) = Word Count (Low, High)
PBA = Page Buffer Address PD = Page Buffer Data BC (L,H) = Byte Count (Low, High)
RA = Extended Register Address BSRD = BSR Data WD (L,H) = Write Data (Low, High)
PA = Program Address GSRD = GSR Data

X = Don’t Care

16

E 28F016SA

NOTES:

1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register Memory Maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.

3. A

is automatically complemented to load the second byte of data. BYTE# must be at VIL.

0

The A

value determines which WD/BC is supplied first: A

4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the

5. In x16 mode, only the lower byte DQ

6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.

7. This command allows the user to swap between available Page Buffers (0 or 1).

8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.

9. Program address, PA, is the destination address in the flash array which must match the source address in the Page

10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.

11. To ensure that the 28F016SA’s power consumption during sleep mode reaches the deep power-down current level, the

12. The upper byte of the data bus (DQ

0

Page Buffer contents into more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.

is used for WCL and WCH. The upper byte DQ

0–7

Buffer. Refer to the

system also needs to de-select the chip by taking either or both CE

16-Mbit Flash Product Family User’s Manual

) during command writes is a “Don’t Care” in x16 operation of the device.

8–15

= 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

0

is a don’t care.

8–15

.

# or CE1# high.

0

17

28F016SA E

operation again.

provide continuous indication of V

’s level only after the Data

4.5 Compatible Status Register

WSMS ESS ES DWS VPPS R R R

76543210

NOTES:

CSR.7 = WRITE STATE MACHINE STATUS

1 = Ready
0 = Busy

CSR.6 = ERASE-SUSPEND STATUS

1 = Erase Suspended
0 = Erase In Progress/Completed

CSR.5 = ERASE STATUS

1 = Error In Block Erasure
0 = Successful Block Erase

CSR.4 = DATA WRITE STATUS

1 = Error in Data Program
0 = Data Program Successful

CSR.3 = VPP STATUS

1 = V
0 = V

Low Detect, Operation Abort

PP

OK

PP

CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.

RY/BY# output or WSMS bit must be checked to
determine completion of an operation (erase
suspend, block erase or data program) before the
appropriate Status bit (ESS, ES or DWS) is
checked for success.

If DWS and ES are set to “1” during a block

erase attempt, an improper command sequence
was entered. Clear the CSR and attempt the

The VPPS bit, unlike an A/D converter, does not

level. The

WSM interrogates V

PP

PP

Program or Block Erase command sequences
have been entered, and informs the system if
V

has not been switched on. VPPS is not

PP

guaranteed to report accurate feedback between
V

PPL

and V

PPH

.

18

E 28F016SA

or DOS) is checked for success.

4.6 Global Status Register

WSMS OSS DOS DSS QS PBAS PBS PBSS

76543210

NOTES:

GSR.7 = WRITE STATE MACHINE STATUS

1 = Ready
0 = Busy

GSR.6 = OPERATION SUSPEND STATUS

1 = Operation Suspended
0 = Operation in Progress/Completed

GSR.5 = DEVICE OPERATION STATUS

1 = Operation Unsuccessful
0 = Operation Successful or Currently

Running

GSR.4 = DEVICE SLEEP STATUS

1 = Device in Sleep
0 = Device Not in Sleep

MATRIX 5/4

0 0 = Operation Successful or Currently

Running

0 1 = Device in Sleep Mode or Pending

Sleep

1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or

Aborted

GSR.3 = QUEUE STATUS

1 = Queue Full
0 = Queue Available

GSR.2 = PAGE BUFFER AVAILABLE STATUS

1 = One or Two Page Buffers Available
0 = No Page Buffer Available

GSR.1 = PAGE BUFFER STATUS

1 = Selected Page Buffer Ready
0 = Selected Page Buffer Busy Selected Page Buffer is currently busy with WSM

GSR.0 = PAGE BUFFER SELECT STATUS

1 = Page Buffer 1 Selected
0 = Page Buffer 0 Selected

NOTE:

1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.

[1]

RY/BY# output or WSMS bit must be checked
to determine completion of an operation (block
lock, erase suspend, any RY/BY# reconfig­uration, Upload Status Bits, block erase or data
program) before the appropriate Status bit (OSS

If operation currently running, then GSR.7 = 0.
If device pending sleep, then GSR.7 = 0.

Operation aborted: Unsuccessful due to Abort
command.

The device contains two Page Buffers.

operation.

19

28F016SA E

4.7 Block Status Register

BS BLS BOS BOAS QS VPPS R R

76543210

NOTES:

BSR.7 = BLOCK STATUS

1 = Ready
0 = Busy

BSR.6 = BLOCK-LOCK STATUS

1 = Block Unlocked for Program/Erase
0 = Block Locked for Program/Erase

BSR.5 = BLOCK OPERATION STATUS

1 = Operation Unsuccessful
0 = Operation Successful or Currently

Running

BSR.4 = BLOCK OPERATION ABORT STATUS

1 = Operation Aborted
0 = Operation Not Aborted

MATRIX 5/4

0 0 = Operation Successful or

Currently Running
0 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted Operation halted via Abort command.

BSR.3 = QUEUE STATUS

1 = Queue Full
0 = Queue Available

BSR.2 = V

STATUS

PP

1 = VPP Low Detect, Operation Abort
0 = V

PP

OK

BSR.1–0 = RESERVED FOR FUTURE ENHANCEMENTS

These bits are reserved for future use; mask them out when polling the BSRs.

NOTE:

1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.

[1]

RY/BY# output or BS bit must be checked to
determine completion of an operation (block lock,
erase suspend, any RY/BY# reconfiguration, Upload
Status Bits, block erase or data program) before the
appropriate Status bits (BOS, BLS) is checked for
success.

The BOAS bit will not be set until BSR.7 = 1.

20

E 28F016SA

5.0 ELECTRICAL SPECIFICATIONS

5.1 Absolute Maximum Ratings*

Temperature under Bias.....................0°C to +80°C

Storage Temperature....................–65°C to +125°C

VCC = 3.3V ± 10% Systems

Sym Parameter Notes Min Max Units Test Conditions

TAOperating Temperature, Commercial 1 0 70 °C Ambient Temperature
VCCVCC with Respect to GND 2 –0.2 7.0 V

VPPV
V

I Current into Any Non-Supply Pin 5 ± 30 mA
I

OUT

= 5.0V ± 10% , VCC = 5.0V ± 5% Systems

V

CC

Sym Parameter Notes Min Max Units Test Conditions

TAOperating Temperature, Commercial 1 0 70 °C Ambient Temperature
VCCVCC with Respect to GND 2 –0.2 7.0 V

VPPV
V Voltage on Any Pin (Except VCC, VPP)

I Current into Any Non-Supply Pin 5 ± 30 mA
I

OUT

NOTES:

1. Operating temperature is for commercial product defined by this specification.

2. Minimum DC voltage is –10% on input/output pins. During transitions, this level may undershoot to –2.0V for periods

<20 ns. Maximum DC voltage on input/output pins is V
periods <20 ns.

3. Maximum DC voltage on V

4. Output shorted for no more than one second. No more than one output shorted at a time.

5. This specification also applies to pins marked “NC.”

6. 5% V

Supply Voltage with Respect to GND 2,3 –0.2 14.0 V

PP

Voltage on Any Pin (Except V
with Respect to GND

Output Short Circuit Current 4 100 mA

Supply Voltage with Respect to GND 2,3 –0.2 14.0 V

PP

with Respect to GND

Output Short Circuit Current 4 100 mA

may overshoot to +14.0V for periods <20 ns.

PP

specifications refer to the 28F016SA-070 in its High Speed Test configuration.

CC

CC

, VPP)

(6)

NOTICE: This is a production datasheet. The specifications
are subject to change without notice. Verify with your local
Intel Sales office that you have the latest datasheet before
finalizing a design.

* WARNING: Stressing the device beyond the “Absolute

Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.

V

2 –0.5

2 –2.0 7.0 V

+ 10% which, during transitions, may overshoot to V

CC

CC

+0.5

V

+ 2.0V for

CC

21

28F016SA E

5.2 Capacitance

For a 3.3V System:

Symbol Parameter Notes Typ Max Units Test Conditions

C

C

C

IN

OUT

LOAD

Capacitance Looking into an
Address/Control Pin

Capacitance Looking into an
Output Pin

Load Capacitance Driven by
Outputs for Timing Specifications

Equivalent Testing Load Circuit 2.5 ns 50Ω Transmission Line

For a 5.0V System:

Symbol Parameter Notes Typ Max Units Test Conditions

C

C

C

IN

OUT

LOAD

Capacitance Looking into an
Address/Control Pin

Capacitance Looking into an
Output Pin

Load Capacitance Driven by
Outputs for Timing Specifications

Equivalent Testing Load Circuit for
V

± 10%

CC

Equivalent Testing Load Circuit for
V

± 5%

CC

NOTE:

1. Sampled, not 100% tested.

1 68pFT

1 8 12 pF T

1 50 pF For V

= +25°C, f = 1.0 MHz

A

= +25°C, f = 1.0 MHz

A

CC

Delay

1 68pFT

1 8 12 pF T

1 100 pF For V

30 pF For V

2.5 ns

2.5 ns

= +25°C, f = 1.0 MHz

A

= +25°C, f = 1.0 MHz

A

CC

CC

25Ω Transmission Line

Delay

83Ω Transmission Line

Delay

= 3.3V ± 10%

= 5.0V ± 10%

= 5.0V ± 5%

22

E 28F016SA

5.3 Timing Nomenclature

All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of five characters. Some common examples are defined below:

t

CEtELQV

t

OEtGLQV

t

ACCtAVQV

t

AStAVWH

t

DHtWHDX

A Address Inputs H High
D Data Inputs L Low
Q Data Outputs V Valid

E CE# (Chip Enable) X Driven, but not necessarily valid

F BYTE# (Byte Enable) Z High Impedance
G OE# (Output Enable)

W WE# (Write Enable)

P RP# (Deep Power-Down Pin)
R RY/BY# (Ready Busy)

V Any Voltage Level

Y 3/5# Pin

5V VCC at 4.5V Minimum
3V VCC at 3.0V Minimum

time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V)

time(t) from OE# (G) going low (L) to the outputs (Q) becoming valid (V)
time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)

time(t) from address (A) valid (V) to WE# (W) going high (H)
time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)

Pin Characters Pin States

23

28F016SA E

2.4
INPUT OUTPUT

0.45

AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins at V

(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.

Figure 7. Transient Input/Output Reference Waveform (VCC = 5.0V ± 10%)

2.0
TEST POINTS

0.8 0.8

for Standard Test Configuration

(1)

2.0

IH

3.0

1.5

OUTPUT

0.0

1.5

TEST POINTSINPUT

AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V.

Input rise and fall times (10% to 90%) <10 ns.

Figure 8. Transient Input/Output Reference Waveform (VCC = 3.3V ± 10%)

High Speed Reference Waveform

(2)

(VCC = 5.0V ± 5%)

NOTES:

1. Testing characteristics for 28F016SA-080/28F016SA-100.

2. Testing characteristics for 28F016SA-070/28F016SA-120/28F016SA-150.

0489_06

0489_07

24

E 28F016SA

2.5 ns of 25 Transmission Line

From Output
under Test

Figure 9. Transient Equivalent Testing Load Circuit (VCC = 5.0V ± 10%)

From Output
under Test

Total Capacitance = 100 pF

2.5 ns of 50 Transmission Line

Ω

Test
Point

Ω

Test
Point

Total Capacitance = 50 pF

0489_08

0489_09

Figure 10. Transient Equivalent Testing Load Circuit (VCC = 3.3V ± 10%)

2.5 ns of 83

From Output
under Test

Figure 11. High Speed Transient Equivalent Testing Load Circuit (VCC = 5.0V ± 5%)

Ω

Transmission Line

Total Capacitanc e = 30 pF

Test
Point

0489_10

25

28F016SA E

5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

Vcc = 3.3V ±10%, T

3/5# = Pin Set High for 3.3V Operations

Sym Parameter Notes Typ Max Typ Max Units Test Conditions

I
I

Input Load Current 1 ± 1 ± 1 µA

IL

Output Leakage

LO

Current

I

CCS

VCC Standby
Current

I

CCD

VCC Deep Power­Down Current

I

1VCC Read Current 1,4,5 30 35 30 40 mA

CCR

I

2VCC Read Current 1,4,5 15 20 15 25 mA

CCR

I

CCWVCC

Program Current
for Word or Byte
V

I

CCE

I

CCES

CC

Current
VCC Erase Suspend
Current

0°C to +70°C, –40°C to +85°C

A =

Temp Comm Extended

1,5,6 50 100 70 250 µA

Block Erase

= VCC Max

V

CC

V

= VCC or GND

IN

= VCC Max

V

1 ± 10 ± 10 µA

CC

V

= VCC or GND

IN

= V

V

CC

CC

Max

CE0#, CE1#, RP#, = V

0.2V

BYTE#, WP#, 3/5# = V

± 0.2V or GND ± 0.2V

= VCC Max

V

14110mA

CC

CE

#, CE1#, RP# = V

0

BYTE#, WP#, 3/5# = V

or V

IL

115

335

RP# = GND ± 0.2V

µA

BYTE# = GND ± 0.2V or

± 0.2V

V

CC

= VCC Max

V

CC

CMOS: CE

#, CE1# =

0

GND ± 0.2V, BYTE# =
GND ± 0.2V or V

0.2V, Inputs = GND ±

0.2V or V

CC

± 0.2V

TTL: CE0#, CE1# = VIL,

BYTE# = V
Inputs = V

f = 8 MHz, I

= VCC Max

V

CC

CMOS: CE

or VIH,

IL

or V

IL

= 0 mA

OUT

#, CE1# =

0

GND ± 0.2V, BYTE# =
GND ± 0.2V or V

0.2V, Inputs = GND ±

0.2V or V

CC

± 0.2V

TTL: CE0#, CE1# = VIL,

BYTE# = V
Inputs = V

f = 4 MHz, I

IL

OUT

or VIH,

IL

or V

= 0 mA

1 8 12 8 12 mA Program in Progress

1 6 12 6 12 mA Block Erase in Progress

1,2 3 6 3 6 mA

CE0#, CE1# = V
Block Erase Suspended

IH

IH

IH

CC

CC

IH

CC

±

±

±

CC

IH

26

E 28F016SA

5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

(Continued)

Vcc = 3.3V ±10%, T

3/5# = Pin Set High for 3.3V Operations

Sym Parameter Notes Typ Max Typ Max Units Test Conditions

I

PPS

VPP Standby/

I

PPR

Read Current

PPD

VPP Deep Power­Down Current

I

0°C to +70°C, –40°C to +85°C

A =

Temp Comm Extended

1 ± 1 ± 10 ± 1 ± 10 µA V

65 200 65 200 µA V

1 0.2 5 0.2 5 µA RP# = GND ± 0.2V

PP

PP

≤ V
> V

CC

CC

27

28F016SA E

5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

(Continued)

Vcc = 3.3V ± 10%, T

3/5# = Pin Set High for 3.3V Operations

Sym Parameter Notes Min Typ Max Units Test Conditions

I

PPW

VPP Program Current for
Word or Byte

I

PPE

I

PPES

V
V

V

V

V

V

V
V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

2. I

3. Block erases, word/byte programs and lock block operations are inhibited when V

4. Automatic Power Savings (APS) reduces I

5. CMOS Inputs are either V

6. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.

VPP Block Erase
Current

VPP Erase Suspend
Current

Input Low Voltage –0.3 0.8 V

IL

Input High Voltage 2.0 V

IH

Output Low Voltage 0.4 V

OL

Output High Voltage 2.4 V

OH1

OH2

VPP during Normal

PPL

Operations
VPP during Program/

PPH

Erase Operations
VCC Program/Erase

LKO

Lock Voltage

valid for all product versions (package and speeds).

is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of

CCES

I

and I

CCES

range between V

Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.

CCR

0°C to +70°C, –40°C to +85°C

A =

.

and V

PPH

.

PPL

± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

CC

Temp Comm/Extended

V

11015mA

1 4 10 mA

1 65 200 µA

CC

PP

Program in Progress
V

PP

Block Erase in Progress
V

PP

Block Erase Suspended

V

+

0.3
V

CC

I

OL

V

CC

I

OH

V

CC

–0.2

V

CC

V

I

OH

3 0.0 6.5 V

3 11.4 12.0 12.6 V

2.0 V

= 3.3V, VPP = 12.0V, T = 25°C. These currents are

CC

and not guaranteed in the

to less than 1 mA in static operation.

CCR

PP = VPPL

= V

PPH

= V

PPH

= V

PPH

= VCC Min

= 4 mA

= VCC Min

= –2.0 mA

= VCC Min

= –100 µA

28

E 28F016SA

5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

V

= 5.0V ± 10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

CC

3/5# Pin Set Low for 5V Operations

Temp Comm Extended

Sym Parameter Notes Typ Max Typ Max Units Test Conditions

V

= V

I

I

Input Load Current 1 ± 1 ± 1 µA

IL

LO

Output Leakage

1 ± 10 ± 10 µA

Current

I

VCC Standby Current 1,5,6 50 100 70 250 µA

CCS

24210mA

I

CCD

VCC Deep Power-

1151060µA

Down Current

I

1VCC Read Current 1,4,5 50 60 55 70 mA

CCR

I

2VCC Read Current 1,4,5 30 35 30 35 mA

CCR

I

CCWVCC

Program Current

1 25 35 25 35 mA Program in Progress

for Word or Byte

I

CCE

I

CCES

VCC Block Erase
Current
VCC Erase Suspend
Current

1 18 25 18 25 mA Block Erase in Progress

1,2 5 10 5 10 mA

CC

V

IN

V

CC

V

IN

V

CC

CE0#, CE1#, RP# = V
BYTE#, WP#, 3/5# = V

V

CC

CE0#, CE1#, RP# = V
BYTE#, WP#, 3/5#

RP# = GND ± 0.2V
BYTE# = GND ± 0.2V or

V

CC

CMOS: CE
GND ±

TTL: CE0#, CE1# = VIL,

f = 10 MHz, I
V

CC

CMOS: CE

TTL: CE0#, CE1# = VIL,

f = 5 MHz, I

CE
Block Erase Suspended

Max

CC

or GND

= V

CC

= V

Max

CC

= V

or GND

CC

= V

Max

CC

CC

0.2V
± 0.2V or GND ± 0.2V

CC

= V

Max

or

V

V

CC

CC

IL

± 0.2V

=

IH

V

IH

= VCC Max

#, CE1# =

0

0.2V, BYTE# = GND ±

0.2V or V

± 0.2V,

CC

Inputs = GND ± 0.2V or
V

± 0.2V

CC

BYTE# = V
Inputs = V

IL

OUT

IL

or V

or VIH,

IH

= 0 mA

= VCC Max

#, CE1# =

0

GND ± 0.2V, BYTE# =
GND ± 0.2V or V

CC

±

0.2V, Inputs = GND ±

0.2V or V
BYTE# = V

Inputs = V

#, CE1# = V

0

CC

IL

OUT

± 0.2V

or VIH,

IL

or V

= 0 mA

IH

IH

±

29

28F016SA E

5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

(Continued)

= 5.0V ± 10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

V

CC

3/5# Pin Set Low for 5V Operations

Temp Comm Extended

Sym Parameter Notes Typ Max Typ Max Units Test Conditions

I
I

I

PPS

VPP Standby/Read
Current

PPR

VPP Deep Power-

PPD

Down Current

1 ± 1 ± 10 ± 1 ± 10 µA V

65 200 65 200 µA V

PP

PP

≤ V

> V

CC

CC

1 0.2 5 0.2 5 µA RP# = GND ± 0.2V

30

E 28F016SA

5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

(Continued)

= 5.0V ± 10%, 5.0V ± 5%,TA = 0°C to +70°C, -40°C to +85°C

V

CC

3/5# Pin Set Low for 5V Operations

Temp Comm/Extended

Sym Parameter Notes Min Typ Max Units Test Conditions

I

PPW

I

PPE

I

PPES

V
V

V

Program Current for

PP

1 7 12 mA V
Word or Byte
VPP Block Erase

1 5 10 mA V
Current
VPP Erase Suspend

1 65 200 µA V
Current
Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 2.0 V

IH

CC

= V

PP

PPH

Program in Progress

= V

PP

PPH

Block Erase in Progress

= V

PP

PPH

Block Erase Suspended

V

+0.5

V

V

V

V

Output Low Voltage 0.45 V V

OL

Output High Voltage 0.85

OH1

OH2

V

CC

V

CC

–0.4

VPP during Normal

PPL

3 0.0 6.5 V

= V

CC

= 5.8 mA

Min

I

CC

OL

VVCC = VCC Min

I

= –2.5 mA

OH

VV

= V

CC

I

= –100 µA

OH

CC

Min

Operations

V

VPP during Program/

PPH

11.4 12.0 12.6 V

Erase Operations

V

VCC Program/Erase

LKO

2.0 V

Lock Voltage

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V
valid for all product versions (package and speeds).

2. I

3. Block erases, word/byte programs and lock block operations are inhibited when V

4. Automatic Power Saving (APS) reduces I

5. CMOS Inputs are either V

6. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.

is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of

CCES

I

and I

CCES

range between V

Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.

CCR

.

and V

PPH

.

PPL

± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

CC

to less than 2 mA in static operation.

CCR

= 5.0V, VPP = 12.0V, T = 25°C. These currents are

CC

PP = VPPL

and not guaranteed in the

31

28F016SA E

5.6 AC Characteristics–Read Only Operations:

COMMERCIAL AND EXTENDED TEMPERATURE

= 3.3V ± 10%, TA = 0°C to +70°C, –40°C to +85°C

V

CC

Temp Commercial Extended

Speed –120 –150 –150

Sym Parameter V

t
t
t
t

Read Cycle Time 120 150 150 ns

AVAV

Address to Output Delay 120 150 150 ns

AVQV

CE# to Output Delay 2 120 150 150 ns

ELQV

RP# High to Output

PHQV

Delay
t
t
t
t
t
t

OE# to Output Delay 2 45 50 50 ns

GLQV

CE# to Output in Low Z 3 0 0 0 ns

ELQX

CE# to Output in High Z 3 30 35 35 ns

EHQZ

OE# to Output in Low Z 3 0 0 0 ns

GLQX

OE# to Output in High Z 3 15 20 20 ns

GHQZ

Output Hold from

OH

Address, CE# or OE#

Change, Whichever

Occurs First
t

FLQV

t
t

BYTE# to Output Delay 3 120 150 150 ns

FHQV

BYTE# Low to Output in

FLQZ

High Z

t

ELFL

t

CE# Low to BYTE# High

ELFH

or Low

CC

Load 50 pF

Notes Min Max Min Max Min Max

620 750 750 ns

3000ns

3 304040ns

3555ns

(1)

3.3V ± 10% Units

For Extended Status Register Reads

Symbol Parameter V

32

t

AVEL

t

AVGL

Address Setup to CE# Going Low 3,4 0 0 ns
Address Setup to OE# Going Low 3,4 0 0 ns

Temp Commercial Extended

Speed –120 –150

CC

3.3V ± 10% Units

Load 50 pF

Notes Min Max Min Max

E 28F016SA

5.6 AC Characteristics–Read Only Operations:
COMMERCIAL AND EXTENDED TEMPERATURE

V

= 5.0V ± 10%, 5.0V ± 5%, TA = 0°C to +70°C. –40°C to +85°C

CC

Temp Commercial Comm/Ext

Speed –70 –80 –100

Sym Parameter V

t
t
t
t
t
t
t
t
t
t

t
t

t
t

t

Read Cycle Time 70 80 100 ns

AVAV

Address to Output Delay 70 80 100 ns

AVQV

CE# to Output Delay 2 70 80 100 ns

ELQV

RP# to Output Delay 400 480 550 ns

PHQV

OE# to Output Delay 2 30 35 40 ns

GLQV

CE# to Output in Low Z 3 0 0 0 ns

ELQX

CE# to Output in High Z 3 25 30 30 ns

EHQZ

OE# to Output in Low Z 3 0 0 0 ns

GLQX

OE# to Output in High Z 3 15 15 15 ns

GHQZ

Output Hold from

OH

Address, CE# or OE#
Change, Whichever
Occurs First

BYTE# to Output Delay

FLQV
FHQV

BYTE# Low to Output in

FLQZ

High Z
CE# Low to BYTE# High

ELFL

or Low

ELFH

Load 30 pF 50 pF 50%

Notes Min Max Min Max Min Max

5.0V ± 5%V 5.0V ± 10%V 5.0V ± 10%V Units

CC

3000ns

3 70 80 100 ns

3 253030ns
3555ns

(1)

(Continued)

33

28F016SA E

For Extended Status Register Reads

Temp Commercial Commercial Comm/Ext

Load 30 pF 50 pF 50 pF

Versions

(5)

VCC ± 5% 28F016SA-070

VCC ± 10% 28F016SA-080

Sym Parameter Notes Min Max Min Max Min Max

t

AVEL

Address

3,4 0 0 0 ns
Setup to CE#
Going Low

t

AVGL

Address

3,4 0 0 0 ns
Setup to OE#
Going Low

NOTES:

1. See AC Input/Output Reference Waveforms for timing measurements,

2. OE# may be delayed up to t

3. Sampled, not 100% tested.

4. This timing parameter is used to latch the correct BSR data onto the outputs.

5. Device speeds are defined as:
70/80 ns at V

120 ns at V
100 ns at V
150 ns at V

6. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for High Speed Test Configuration.

7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.

ELQV–tGLQV

= 5.0V equivalent to

CC

= 3.3V

CC

= 5.0V equivalent to

CC

= 3.3V

CC

after the falling edge of CE# without impact on t

(6)

Figures 7 and 8.

(7)

28F016SA-100

.

ELQV

Units

(7)

34

E 28F016SA

V

IH

t

AVEL

t

PHQV

ADDRESSES STABLE

t

AVGL

t

ELQV

t

GLQX

t

ELQX

t

AVQV

t

AVAV

t

EHQZ

t

GHQZ

t

GLQV

VALID OUTPUT

t

OH

HIGH ZHIGH Z

0489_11

ADDRESSES (A)

V

IL

V

IH

(1)

CEx# (E)

V

IL

V

IH

OE# (G)

V

IL

V

IH

WE# (W)

V

IL

V

OH

DATA (D/Q)

V

OL

5.0V

V

CC

GND

V

IH

RP# (P)

V

IL

NOTE:

1. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

Figure 12. Read Timing Waveforms

35

28F016SA E

V

IH

t

AVFL

t

AVGL

t

ELFL

ADDRESSES STABLE

= t

ELFL

t

ELQV

t

GLQX

t

ELQX

t

AVQV

t

GLQV

t

AVAV

t

DATA OUTPUT

t

FLQZ

DATA

OUTPUT

FLQV

= t

AVQV

HIGH Z

t

OH

DATA

OUTPUT

t

t

EHQZ

GHQZ

HIGH Z

ADDRESSES (A)

CEx #(E)

OE# (G)

BYTE# (F)

V

DATA (DQ0-DQ7)

V

V

DATA (DQ8-DQ15)

V

V

IL

V

IH

(1)

V

IL

V

IH

V

IL

V

IH

V

IL

OH

OL

OH

HIGH Z

t

AVEL

HIGH Z

OL

NOTE:

1. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

Figure 13. BYTE# Timing Waveforms

36

0489_12

E 28F016SA

5.7 Power-Up and Reset Timings: COMMERCIAL/EXTENDED TEMPERATURE

V Power-Up

CC

RP#

(P)

3/5#

(Y)

V

CC

(3V,5V)

CE #

X

Address

(A)

Data

(Q)

0V

t

YHPH

3.3V

t

PHQV

t

PHEL3

t

AVQV

Valid 3.3V Outputs

Valid

t

PLYL

t

PL5V

t

YLPH

4.5V

5.0V

t

PHQV

t

PHEL5

Valid

t

AVQV

Valid 5.0V Outputs

Figure 14. VCC Power-Up and RP# Reset Waveforms

Symbol Parameter Notes Min Max Unit

t

PLYL

t

PLYH

t

YLPH

t

YHPH

t

PL5V

t

PL3V

t

PHEL3

t

PHEL5

t

AVQV

t

PHQV

NOTES:

CE

#, CE1# and OE# are switched low after Power-Up.

0

1. The t

2. The power supply may start to switch concurrently with RP# going low.

3. The address access time and RP# high to data valid time are shown for 5V V

the AC Characteristics Read Only Operations for 3.3V V

RP# Low to 3/5# Low (High) 0 µs

3/5# Low (High) to RP# High 1 2 µs

RP# Low to VCC at 4.5V minimum
(to V

at 3.0V min or 3.6V max)

CC

20 µs

RP# High to CE# Low (3.3V VCC) 1 500 ns
RP# High to CE# Low (5V VCC) 1 330 ns
Address Valid to Data Valid for VCC = 5V ± 10% 3 80 ns
RP# High to Data Valid for VCC = 5V ± 10% 3 480 ns

YLPH/tYHPH

and t

PHEL3/tPHEL5

times must be strictly followed to guarantee all other read and program specifications.

operation of the 28F016SA-080. Refer to

and all other speed options.

CC

CC

0489_13

37

28F016SA E

5.8 AC Characteristics for WE#–Controlled Command Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE

= 3.3V ± 10%, TA = 0°C to +70°C, –40°C to +85°C

V

CC

Temp Commercial Comm/Extended

Sym Parameter Notes Min Typ Max Min Typ Max Units

t

AVAV

t

VPWH

t

PHEL

t

ELWL

t

AVWH

t

DVWH

t

WLWH

t

WHDX

t

WHAX

t

WHEH

t

WHWL

tGHWL Read Recovery before Write 0 0 ns
t

WHRL

t

RHPL

t

PHWL

t

WHGL

t

QVVL

t

WHQV1

t

WHQV2

Write Cycle Time 120 150 ns
VPP Setup to WE# Going High 3 100 100 ns
RP# Setup to CE# Going Low 480 480 ns
CE# Setup to WE# Going Low 10 10 ns
Address Setup to WE# Going

2,6 75 75 ns

High
Data Setup to WE# Going

2,6 75 75 ns

High
WE# Pulse Width 75 75 ns
Data Hold from WE# High 2 10 10 ns
Address Hold from WE# High 2 10 10 ns
CE# Hold from WE# High 10 10 ns
WE# Pulse Width High 45 75 ns

WE# High to RY/BY# Going
Low

RP# Hold from Valid Status

30 0 ns
Register (CSR, GSR, BSR)
Data and RY/BY# High

RP# High Recovery to WE#

11µs

Going Low
Write Recovery before Read 95 120 ns
VPP Hold from Valid Status

00µs
Register (CSR, GSR, BSR)
Data and RY/BY# High

Duration of Word/Byte

4,5 5 9 Note75 9 Note7µs

Program Operation
Duration of Block Erase

4 0.3 10 0.3 10 sec

Operation

(1)

100 100 ns

38

E 28F016SA

5.8 AC Characteristics for WE#–Controlled Command Write Operations:

(1)

COMMERCIAL AND EXTENDED TEMPERATURE

V

= 5.0V ±10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

CC

Temp Commercial Commercial Comm/Ext

Versions VCC ± 5% 28F016SA-070 Unit

VCC ± 10% 28F016SA-080 28F016SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

t

t

t

t

t

t

t

t

t

t

t

t

AVAV

VPWH

PHEL

ELWL

AVWH

DVWH

WLWH

WHDX

WHAX

WHEH

WHWL

GHWL

Write Cycle
Time

V

Setup to
WE# Going
High

RP# Setup to
CE# Going
Low

CE# Setup to
WE# Going
Low

Address Setup
to WE# Going
High

Data Setup to
WE# Going
High

WE# Pulse
Width

Data Hold
from WE#
High

Address Hold
from WE#
High

CE# Hold from
WE# High

WE# Pulse
Width High

Read
Recovery
before Write

70 80 100 ns

3 100 100 100 ns

480 480 480 ns

000ns

2,6 50 50 50 ns

2,6 50 50 50 ns

40 50 50 ns

20 0 0 ns

210 10 10 ns

10 10 10 ns

30 30 50 ns

000ns

(Continued)

39

28F016SA E

5.8 AC Characteristics for WE#–Controlled Command Write Operations:

(1)

COMMERCIAL AND EXTENDED TEMPERATURE

V

= 5.0V ±10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

CC

Temp Commercial Commercial Comm/Ext

Versions VCC ± 5% 28F016SA-070 Unit

VCC ± 10% 28F016SA-080 28F016SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

t

t

t

t

t

t

t

WHRL

RHPL

PHWL

WHGL

QVVL

1 Duration of

WHQV

2 Duration of

WHQV

WE# High to
RY/BY# Going
Low

RP# Hold from
Valid Status
Register
(CSR, GSR,
BSR) Data
and RY/BY#
High

RP# High
Recovery to
WE# Going
Low

Write
Recovery
before Read

V

Hold from
Valid Status
Register
(CSR, GSR,
BSR) Data
and RY/BY#
High

Word/Byte
Program
Operation

Block Erase
Operation

100 100 100 ns

30 0 0 ns

111µs

60 65 80 ns

000µs

4,5 4.5 6 Note74.5 6 Note74.5 6 Note7µs

4 0.3 10 0.3 10 0.3 10 sec

(Continued)

40

E 28F016SA

NOTES:

CE# is defined as the latter of CE

1. Read timings during data program and block erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested.

4. Data program/block erase durations are measured to valid Status Register data.

5. Word/byte program operations are typically performed with 1 programming pulse.

6. Address and data are latched on the rising edge of WE# for all command write operations.

7. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office

for more information.

# or CE1# going low or the first of CE0# or CE1# going high.

0

POWER-DOW N

ADDRESSES (A)

NOTE 1

ADDRESSES (A)

NOTE 2

CEx # (E)

NOTE 4

OE# (G)

WE# (W)

DATA (D/Q)

V

RY/BY# (R)

V

RP# (P)

V

V

(V)

PP

V

t

t

WLWH

t

IN

WRITE VALID ADDRESS

& DATA (DATA-W RITE) OR

ERASE CONFIRM COMM AND

A

t

AVWH

A

t

AVWH

WHEH

t

WHWL

WHDX

AUTOMATED DATA-WRITE

OR ERASE DEL AY

IN

t

WHAX

IN

t

WHAX

t

WHGL

t

WHQV1,2

IN

t

WHRL

t

VPWH

WRITE DATA-WRIT E OR

DEEP

IL

IH

IL

IH

IL

IH
IL

IH

IL

IH

IL

IH

IL

IL

ERASE SETUP COMMAND

t

ELWL

t

DVWH

HIGH Z

t

PHWL

t

AVAV

t

AVAV

DD

V

IH

V

V

V

V

V

V
V

V

V

V

V

OH

OL

V

V

V

PPH

PPL

IN

V

WRITE READ EXTENDED

REGISTER COMMAND

NOTE 3

D

IN

READ EXTENDED

STATUS REGISTER DATA

A=RA

READ COMPATIBLE

STATUS REGISTER DATA

D

OUT

t

RHPL

NOTE 5

t

GHWL

t

QVVL

NOTES:

1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.

2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during data program/block erase operations.

4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

5. RP# low transition is only to show t

; not valid for above read and program cycles.

RHPL

D

IN

0489_14

Figure 15. AC Waveforms for Command Write Operations

41

28F016SA E

5.9 AC Characteristics for CE#–Controlled Command Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE

= 3.3V ±10%, TA = 0°C to +70°C, -40°C to +85°C

V

CC

Temp Commercial Comm/Ext

Sym Parameter Speed -120 -150 Unit

Notes Min Typ Max Min Typ Max

t

AVAV

t

VPEH

t

PHWL

t

WLEL

t

AVEH

t

DVEH

t

ELEH

t

EHDX

t

EHAX

t

EHWH

t

EHEL

t

GHEL

t

EHRL

t

RHPL

t

PHEL

t

EHGL

t

QVVL

t

EHQV1

t

EHQV2

Write Cycle Time 120 150 ns
VPP Setup to CE# Going High 3 100 100 ns
RP# Setup to WE# Going Low 480 480 ns
WE# Setup to CE# Going Low 0 0 ns
Address Setup to CE# Going

2,6 75 75 ns

High
Data Setup to CE# Going High 2,6 75 75 ns
CE# Pulse Width 75 75 ns
Data Hold from CE# High 2 10 10 ns
Address Hold from CE# High 2 10 10 ns
WE Hold from CE# High 10 10 ns
CE# Pulse Width High 45 75 ns
Read Recovery before Write 0 0 ns
CE# High to RY/BY# Going Low 100 100 ns
RP# Hold from Valid Status

30 0 ns
Register (CSR, GSR, BSR)
Data and RY/BY# High

RP# High Recovery to CE#

11µs

Going Low
Write Recovery before Read 95 120 ns
VPP Hold from Valid Status

00µs
Register (CSR, GSR, BSR)
Data and RY/BY# High

Duration of Word/Byte Program

4,5 5 9 Note75 9 Note7µs

Operation
Duration of Block Erase

4 0.3 10 0.3 10 sec

Operation

(1)

42

E 28F016SA

5.9 AC Characteristics for CE#–Controlled Command Write Operations:

(1)

COMMERCIAL AND EXTENDED TEMPERATURE

V

= 5.0 to 10% , 5.0 ± 5%, TA = 0°C to +70°C, –40°C to +85°C

CC

Temp Commercial Commercial Comm/Ext

Versions VCC ± 5% 28F016SA-070 Unit

VCC ± 10% 28F016SA-080 28F016SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

t

Write Cycle

AVAV

Time

t

VPEHVPP

t

PHWL

t

WLEL

t

AVEH

t

DVEH

t

ELEH

t

EHDX

t

EHAX

t

EHWH

t

EHEL

t

GHEL

t

EHRL

Setup to
CE# Going
High

RP# Setup to
WE# Going
Low

WE# Setup to
CE# Going Low

Address Setup
to CE# Going
High

Data Setup to
CE# Going
High

CE# Pulse
Width

Data Hold from
CE# High

Address Hold
from CE# High

WE# Hold from
CE# High

CE# Pulse
Width High

Read Recovery
before Write

CE# High to
RY/BY# Going
Low

3 100 100 100 ns

3 480 480 480 ns

2,6 50 50 50 ns

2,6 50 50 50 ns

20 0 0 ns

210 10 10 ns

70 80 100 ns

000ns

40 50 50 ns

10 10 10 ns

30 30 50 ns

000ns

100 100 100 ns

(Continued)

43

28F016SA E

5.9 AC Characteristics for CE#–Controlled Command Write Operations:

(1)

COMMERCIAL AND EXTENDED TEMPERATURE

V

= 5.0 to 10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

CC

Temp Commercial Commercial Comm/Ext

Versions VCC ± 5% 28F016SA-070 Unit

VCC ± 10% 28F016SA-080 28F016SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

t

RP# Hold from

RHPL

Valid Status
Register (CSR,
GSR, BSR)
Data and
RY/BY# High

t

RP# High

PHEL

Recovery to
CE# Going Low

t

Write Recovery

EHGL

before Read

t

QVVLVPP

Hold from
Valid Status
Register (CSR,
GSR, BSR)
Data and
RY/BY# High

t

Duration of

EHQV1

Word/Byte
Program
Operation

t

Duration of

EHQV2

Block Erase
Operation

NOTES:

CE# is defined as the latter of CE

1. Read timings during data program and block erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested.

4. Data program/block erase durations are measured to valid Status Register data.

5. Word/byte program operations are typically performed with 1 programming pulse.

6. Address and data are latched on the rising edge of CE# for all command write operations.

7. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office

for more information.

30 0 0 ns

111µs

60 65 80 µs

000µs

4,5 4.5 6 Note74.5 6 Note74.5 6 Note7µs

4 0.3 10 0.3 10 0.3 10 sec

# or CE1# going low or the first of CE0# or CE1# going high.

0

(Continued)

44

E 28F016SA

POWER-DOWN

ADDRESSES (A)

NOTE 1

ADDRESSES (A)

NOTE 2

WE# (W)

OE# (G)

CEx#(E)

NOTE 4

DATA (D/Q)

V

RY/BY# (R)

V

RP# (P)

(V)

V

PP

t

ELEH

t

IN

WRITE VALID AD DRESS

& DATA (DATA-W RITE) OR

ERASE CONFIRM COMMAND

A

t

AVEH

A

t

t

EHWH

t

EHEL

EHDX

AUTOMATED DATA-WRITE

OR ERASE DELAY

IN

t

EHAX

IN

t

EHAXAVEH

t

EHQV1,2

D

IN

t

EHRL

t

VPEH

WRITE DATA-WRITE OR

DEEP

IH

IL

IH

IL

IH

IL

IH
IL

IH

IL

IH

IL

IH

IL

ERASE SETUP COMMAND

t

WLEL

t

DVEH

HIGH Z

t

PHEL

t

AVAV

t

AVAV

D

V

V

V

V

V

V

V
V

V

V

V

V

OH

OL

V

V

V

PPH

V

PPL

V

IH

V

IL

WRITE READ EXTENDED

REGISTER COMMAND

NOTE 3

D

IN

READ EXTENDED

STATUS REGISTER DATA

A=RA

READ COMPATIBLE

STATUS REGISTER DATA

t

EHGL

D

OUT

t

RHPL

NOTE 5

t

GHEL

t

QVVL

NOTES:

1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.

2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during data program/block erase operations.

4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

5. RP# low transition is only to show t

; not valid for above read and program cycles.

RHPL

D

IN

0489_15

Figure 16. Alternate AC Waveforms for Command Write Operations

45

28F016SA E

5.10 AC Characteristics for Page Buffer Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE

= 3.3V ± 10%, TA = 0°C to +70°C, –40°C to +85°C

V

CC

Temp Commercial Comm/Ext

Sym Parameter Speed –120 –150 Unit

Notes Min Typ Max Min Typ Max

t

AVAV

t

ELWL

t

AVWL

t

DVWH

t

WLWH

t

WHDX

t

WHAX

t

WHEH

t

WHWL

t

GHWL

t

WHGL

Write Cycle Time 120 150 ns
CE# Setup to WE# Going Low 10 10 ns
Address Setup to WE# Going Low 3 0 0 ns
Data Setup to WE# Going High 2 75 75 ns
WE# Pulse Width 75 75 ns
Data Hold from WE# High 2 10 10 ns
Address Hold from WE# High 2 10 10 ns
CE# Hold from WE# High 10 10 ns
WE# Pulse Width High 45 75 ns
Read Recovery before Write 0 0 ns
Write Recovery before Read 95 120 ns

(1)

46

E 28F016SA

5.10 AC Characteristics for Page Buffer Write Operations:

(1)

COMMERCIAL AND EXTENDED TEMPERATURE

V

= 5.0V ± 10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

CC

Temp Commercial Commercial Comm/Ext

Sym Parameter Speed –70 –80 –100 Unit

V

CC

Notes Min Typ Max Min Typ Max Min Typ Max

t

AVAV

t

ELWL

t

AVWL

t

DVWH

t

WLWH

t

WHDX

t

WHAX

t

WHEH

t

WHWL

t

GHWL

t

WHGL

NOTES:

CE# is defined as the latter of CE

1. These are WE#–controlled write timings, equivalent CE#–controlled write timings apply.

2. Sampled, but not 100% tested.

3. Address must be valid during the entire WE# low pulse or the entire CE# low pulse for CE#-controlled writes.

Write Cycle Time 70 80 100 ns
CE# Setup to

WE# Going Low
Address Setup to

WE# Going Low
Data Setup to

WE# Going High
WE# Pulse Width 40 50 50 ns
Data Hold from

WE# High
Address Hold

from WE# High
CE# Hold from

WE# High
WE# Pulse Width

High
Read Recovery

before Write
Write Recovery

before Read

3000ns

2505050ns

2000ns

2101010ns

# or CE1# going low or the first of CE0# or CE1# going high.

0

5.0V ± 5% 5.0V ± 10% 5.0V ± 10%

000ns

10 10 10 ns

30 30 50 ns

000ns

60 65 80 ns

(Continued)

47

28F016SA E

V

CEx#(E)

WE# (W)

ADDRESSES (A)

DATA (D/Q)

IH

V

IL

t

ELWL

V

IH

HIGH Z

t

AVWL

t

WLWH

VALID

t

DVWH

D

IN

V

IL

V

IH

V

IL

V

IH

V

IL

Figure 17. Page Buffer Write Timing Waveforms

(Loading Data to the Page Buffer)

t

WHEH

t

WHDX

t

WHAX

t

WHWL

0489_16

48

E 28F016SA

5.11 Erase and Word/Byte Write Performance, Cycling Performance and Suspend Latency

= 3.3V ± 10%, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C

V

CC

Sym Parameter Notes Min Typ

Page Buffer Byte Write Time 2,4 3.26 Note 6 µs
Page Buffer Word Write Time 2,4 6.53 Note 6 µs

t

1 Word/Byte Program Time 2 9 Note 6 µs

WHRH

t

2 Block Program Time 2 0.6 2.1 sec Byte Prog. Mode

WHRH

t

3 Block Program Time 2 0.3 1.0 sec Word Prog. Mode

WHRH

Block Erase Time 2 0.8 10 sec
Full Chip Erase Time 2 25.6 sec
Erase Suspend Latency Time

to Read
Auto Erase Suspend Latency

Time to Write
Erase Cycles 5 100,000 1,000,000 Cycles

= 5.0V ± 10%, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C

V

CC

Sym Parameter Notes Min Typ

Page Buffer Byte Write Time 2,4 2.76 Note 6 µs
Page Buffer Word Write Time 2,4 5.51 Note 6 µs

t

1 Word/Byte Program Time 2 6 Note 6 µs

WHRH

t

2 Block Program Time 2 0.4 2.1 sec Byte Prog. Mode

WHRH

t

3 Block Program Time 2 0.2 1.0 sec Word Prog. Mode

WHRH

Block Erase Time 2 0.6 10 sec
Full Chip Erase Time 2 19.2 sec
Erase Suspend Latency Time

to Read
Auto Erase Suspend Latency

Time to Write
Erase Cycles 5 100,000 1,000,000 Cycles

NOTES:

1. +25°C, V

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. This assumes using the full Page Buffer to data program to the flash memory (256 bytes or 128 words).

5. Typical 1,000,000 cycle performance assumes the application uses block retirement techniques.

6. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel Sales office

for more information.

= 3.3V or 5.0V nominal, VPP = 12.0V nominal, 10K cycles.

CC

(3)

(1)

Max Units Test Conditions

7.0 µs

10.0 µs

(1)

Max Units Test Conditions

5.0 µs

8.0 µs

49

28F016SA E

6.0 DERATING CURVES

290489-16.eps

Figure 18. ICC vs. Frequency (VCC = 5.5V) for x8

or x16 Operation

290489-18.eps

Figure 19. ICC during Block Erase

50

290489-19.eps

Figure 20. ICC vs. Frequency (VCC = 3.6V) for x8

or x16 Operation

290489-21.eps

Figure 21. IPP during Block Erase

E 28F016SA

Figure 22. Access Time (t

290489-25.eps

Figure 23. IPP during Word Write Operation

) vs. Output Loading

ACC

Figure 24. IPP during Page Buffer Write

Operation

290489-24.eps

290489-26

51

28F016SA E

7.0 MECHANICAL SPECIFICATIONS FOR TSOP

290489-28.eps

Figure 25. Mechanical Specifications of the 28F016SA 56-Lead TSOP Type 1 Package

Family: Thin Small Outline Package

Symbol Millimeters

Minimum Nominal Maximum Notes

A 1.20

52

A

1

A

2

b 0.100 0.150 0.200
c 0.115 0.125 0.135

D

1

E 13.80 14.00 14.20

e 0.50

D 19.80 20.00 20.20

L 0.500 0.600 0.700

N56

∅

Y 0.100

Z 0.150 0.250 0.350

0.05

0.965 0.995 1.025

18.20 18.40 18.60

0°3°5°

E 28F016SA

See Detail A

b

8.0 MECHANICAL SPECIFICATIONS FOR SSOP

a

He

E

A2

R1

R2

Detail A

D

e

B

Figure 26. Mechanical Specifications of the 56-Lead SSOP Package

Symbol Millimeters

A 1.80 1.90
A1 0.47 0.52 0.57
A2 1.18 1.28 1.38

B 0.25 0.30 0.40

C 0.13 0.15 0.20

D 23.40 23.70 24.00

E 13.10 13.30 13.50

e

1

He 15.70 16.00 16.30

N56

L

1

Y 0.10

a 2° 3° 4°

b3°3°5°
R1 0.15 0.20 0.25
R2 0.15 0.20 0.25

1

Minimum Nominal Maximum Notes

0.45 0.50 0.55

Y

Family: Shrink Small Outline Package

A

A1

C

0.80

L

1

0528_20

53

28F016SA E

= 5.0V ± 10%,

100 pF Load

APPENDIX A

DEVICE NOMENCLATURE AND ORDERING

INFORMATION

CC

-

7

ACCESS SPEED

70 ns
100 ns
100 ns

VCC = 5.0V ± 5%,

30 pF Load

A268F

D

DA = Commercial Temperature
56-Lead SSOP
E = Commercial Temperature
56-Lead TSOP
T = Extended Temperature
56-Lead SSOP

Option Order Code VCC = 3.3V ± 10%,

1 E28F016SA-070 E28F016SA-120 E28F016SA-080 E28F016SA-070
2 E28F016SA-100 E28F016SA-150 E28F016SA-100
3 DA28F016SA-070 DA28F016SA-120 DA28F016SA-080 DA28F016SA-070
4 DA28F016SA-100 DA28F016SA-150 DA28F016SA-100
5 DT28F016SA-100 DT28F016SA-150 DT28F016SA-150 DT28F016SA-150

000

1SA

Valid Combinations

50 pF Load

V

0489_18

54

E 28F016SA

APPENDIX B

ADDITIONAL INFORMATION

Order Number Document/Tool

297372
290490
290528
290429
292092
292123
292126

292144
292159
294016

297534

297508 FLASHBuilder Design Resource Tool

NOTES:

1. Please call the Intel Literature Center at [phone] to request Intel documentation. International customers should
contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.

16-Mbit Flash Product Family User’s Manual
DD28F032SA 32-Mbit FlashFile™ Memory Datasheet
28F016SV FlashFile™ Memory Datasheet
28F008SA 8-Mbit FlashFile™ Memory Datasheet
AP-357 Power Supply Solutions for Flash Memory
AP-374 Flash Memory Write Protection Techniques
AP-377 16-Mbit Flash Product Family Software Drivers 28F016SA, 28F016SV,

28F016XS, 28F016XD
AP-393 28F016SV Compatibility with 28F016SA
AP-607 Multi-Site Layout Planning with Intel’s Flash File™ Components
ER-33 ETOX™ Flash Memory Technology - Insight to Intel’s Fourth Generation

Process Innovation
Small and Low-Cost Power Supply solution for Intel’s Flash Memory Products

(Technical Paper)

(1,2)

55