Datasheet CY8C29466, CY8C29566, CY8C29666, CY8C29866 Datasheet (CYPRESS)

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PSoC™ Mixed-Signal Array Final Data Sheet

CY8C29466, CY8C29566, CY8C29666, and CY8C29866

Features

■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ Two 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0V to 5.25V Operating Voltage ❐ Operating Voltages Down to 1.0V Using On-

Chip Switch Mode Pump (SMP)

❐ Industrial Temperature Range: -40°C to +85°C

■ Advanced Peripherals (PSoC Blocks) ❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:

- Up to 14-Bit ADCs

- Up to 9-Bit DACs

- Programmable Gain Amplifiers

- Programmable Filters and Comparators

❐ 16 Digital PSoC Blocks Provide:

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Up to 4 Full-Duplex UARTs

- Multiple SPI™ Masters or Slaves

- Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks

Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

SYSTEM BUS

Global Digital Interconnect

SRAM

Interrupt

Controller

Multiple C lock Sources

(Includes IMO, ILO, PLL, and ECO)

DIGITAL SYSTEM

Digital

Block Array

SROM Flash 32K

CPU Core (M8C)

Global Analog Interconnect

ANALOG SYSTEM

Analog

Block Array

■ Precision, Programmable Clocking ❐ Internal ±2.5% 24/48 MHz Oscillator ❐ 24/48 MHz with Optional 32.768 kHz Crystal ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Oscillator for Watchdog and Sleep

■ Flexible On-Chip Memory ❐ 32K Bytes Flash Program Storage 50,000

Erase/Write Cycles

❐ 2K Bytes SRAM Data Stora ge ❐ In-System Serial Programming (ISSP™) ❐ Partial Flash Updates ❐ Flexible Protection Mode s ❐ EEPROM Emulation in Flash

■ Programmable Pin Configuration s ❐ 25 mA Sink on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open

Drain Drive Modes on all GPIO

❐ Up to 12 Analog Inputs on GPIO ❐ Four 40 mA Analog Outputs on GPIO ❐ Configurable Interrupt on all GPIO

Analog Drivers

PSoC™ Functional Overview

The PSoC™ family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture

PSoC CORE

Sleep and Watchdog

allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages.

The PSoC architecture, as illustrat ed on th e l ef t , is com pri se d of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all

Analog

Ref.

the device r esources to be c ombined into a compl ete custom system. The PSoC CY8C29x66 family can have up to eight IO ports that connec t to the gl obal di git al and a nalog i ntercon ne cts ,

Analog

Input

Mux ing

providing access to 16 digital blocks and 12 analog blocks.

The PSoC Core

■ Additional System Resources

❐ I

C™ Slave, Mast er, an d Multi-Mas ter to

400 kHz

❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference

■ Complete Developm en t Tools ❐ Free Development Software

(PSoC™ De signer)

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full S peed Emulation ❐ Complex Breakpoint Structure ❐ 128K Bytes Trace Memory ❐ Complex Events ❐ C Compilers, Assembler, and Linker

The PSoC Core is a powerful engine that supports a rich feature set. Th e co re in cl ud es a C PU , memo r y, clocks, and c on fig -

Digital

Clocks

Tw o

Multiply

Accums.

POR and LVD

Decimator

I C

System Resets

SYSTEM R ESOURCES

Internal Voltage

Ref .

Sw itch

Mode Pump

urable GPIO (General Purpose IO). The M8C C PU core is a powerfu l proce ssor wit h spee ds up t o

24 MHz, providing a four MI PS 8-bit Harvar d archit ecture m icroprocessor. The CPU utilizes an interrupt controller with 25 vec-

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CY8C29x66 Final Data Sheet PSoC™ Overview

tors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT).

Port 7

Port 6

Port 5

Port 4

Port 3

Port 2

Port 1

Port 0

Memory encompasses 32 KB of Flash for program storage, 2 KB of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utiliz es four pro tectio n lev-

T o Syste m Bu s

To Analog

System

els on blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Cloc k (RT C) and can opti onally genera te a crys tal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System

Row Input

DIGITAL SYSTEM

Digital PSoC Block Array

Row 0

DBB00 DBB01 DCB02 DCB03

Configuration

Row 1

DBB10 DBB11 DCB12 DCB13

Configuration

Row Outpu t

Configuration

Row O utput

Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.

Row 2

Configuration

Row Outpu t

PSoC GPIOs provide conne ct ion t o the CP U, di gital and analog resources of the devi ce. Each pin’ s dri ve mod e may b e selec te d from eight options, allowing great flexibility in external interfac-

DBB20 DBB21 DCB22 DCB23

Row Input

Configuration

ing. Every pin also has the c apa bility to gen erate a syste m inte rrupt on high level, low level, and change from last read.

Row 3

Configuration

Row Outpu t

The Digital System

The Digital System is composed of 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other bl oc ks to fo rm 8, 16 , 24, and 32-bit perip hera ls , which are called user mo dule ref eren ces. Dig ita l periph eral co nfigurations include those listed below.

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 32 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity (up to 4)

■ SPI master and slave (up to 4 each)

■ I2C slave and multi-master (1 available as a System

Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA (up to 4)

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This config urability frees your desi gns from the co nstraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled “PSoC Device Charac-

teristics” on page3.

DBB30 DBB31 DCB32 DCB33

Row Input

Configuration

GIE[7:0] GIO[7:0]

Global Digital Interconnect

GOE[7:0] GOO[7:0]

Digital System Block Diagram

The Analog System

The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requiremen ts. Some of the more comm on PSoC analog fun ctions (most available as user modules) are listed below.

■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolu-

tion, selectable as Incr emental, Delta Sigma, and SAR)

■ Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 4, with selectable gain to 48x)

■ Instrumentation amplifiers (up to 2, with selectable gain to

93x)

■ Comparators (up to 4, with 16 selectable thresholds)

■ DACs (up to 4, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)

■ High current output drivers (four with 40 mA drive as a Core

Resource)

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CY8C29x66 Final Data Sheet PSoC™ Overview

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak Detectors

■ Many other topologies possible

Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below.

P0[7]

P0[5]

P0[3] P0[1]

P2[3]

P2[1]

Array Input Configuration

P0[6]

P0[4]

P0[2] P0[0]

P2[6]

RefIn

P2[4]

AGNDIn

P2[2] P2[0]

Additional System Resources

System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below.

■ Digital clock dividers provide three customizable clock fre-

quencies for use in applic ations . The clo cks c an be route d to both the digital a nd analog systems. Additiona l clocks c an be generated using digital PSoC blocks as clock dividers.

■ Two multiply accumulates (MACs) provide fast 8-bit multipli-

ers with 32-bit accumulate to assist in both general math as well as dig ital filters.

■ The decimator provides a custom hardware filter for digital

signal, processi ng applicat ions includ ing the creat ion of Delt a Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication

over two wires. Slave, master, and multi-master modes are all supported.

■ Low Voltage Detection (LVD) interrupts can signal the appli-

cation of f alling voltage levels, w hile the adv anced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3 voltage reference provides an absolute refer-

ence for the analog system, including ADCs and DACs.

■ An integrated switch mode pump (S MP) gene rate s norm al

operating volt ages f rom a single 1.2V batt ery cel l, providin g a low cost boost converter.

ACI0[1:0] ACI3[1:0]

ACB00 ACB01

ASC10

Interface to

Digital System

M8C Interface (Address Bus, Data Bus, Etc.)

ACI1[1:0] ACI2[1:0]

B l oc k Arra y

ACB02 ACB03

ASD11

ASC21

RefLo AGND

RefHi

ASC12 ASD13

ASD22 ASC23ASD20

Analog Re fe re nce

Reference

Generators

Analog System Block Diagram

AGNDIn RefIn Bandgap

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted below.

PSoC Device Characteristics

PSoC Device

Group

Digital Rows

Digital Blocks

Digital IO (max)

CY8C29x66 44 4 16 12 4 4 12 2K 32K

CY8C27x43 CY8C24794 56 1 4 48 2 2 6 1K 16K CY8C24x23 24 1 4 12 2 2 6 256 Bytes 4K CY8C24x23A 24 1 4 12 2 2 6 256 Bytes 4K CY8C21x34 28 1 4 28 0 2

CY8C21x23

a. Limited analog functionality.

44 2 8 12 4 4 12 256 Bytes 16K

16 1 4 8 0 2

Analog Inputs

Analog Outputs

Analog Blocks

Analog Columns

Amount of SRAM

512 Bytes 8K 256 Bytes 4K

Amount of Flash

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CY8C29x66 Final Data Sheet PSoC™ Overview

Getting Started

The quickest path to understanding the PSoC silicon is by rea ding this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC™ Mixed-Signal Array Technical Reference Manual.

For up-to-date Ordering, Packag ing, an d Electri cal Specificatio n information, reference the latest PSoC device data sheets on the web at http://www.cypress.com/psoc.

Development Kits

Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at http://www.onfulfillment.com/cypressstore/ contains develop- ment kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view a current list of available items.

Tele-Training

Free PSoC "Tele-training" is available for beginners and taught by a marketing or application engineer over the phone. Five training cl asses are availabl e to accelerate th e learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the tele-training, see http://www.cypress.com/support/training.cfm.

Consultants

Certified PSoC Consultants offer everything from technical assistance to complete d PSoC d esign s. To contact or become a PSoC Consultant, go to the following Cypress support web site:

http://www.cypress.com/support/cypros.cfm.

Technical Support

PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.

Development Tools

The Cypress MicroSystems PSoC Designer is a Microsoft Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)

PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs.

PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.

PSoC

Designer

Importable

Design

Database

Dev ice

Database

Application

Database

Project

Database

User

Modules

Library

Graphical Designer

Interf ace

Results

Commands

PSoC

Designer

Core

Engin e

Context

Sensitive

Help

PSoC

Configuration

Sheet

Manufacturing

Information

File

Application Notes

A long list of application notes will assist you in every aspect of

Emulation

Pod

In-Circuit Emulator

Device

Programmer

your design effort. To locate the PSoC application notes, go to

http://www.cypress.com/design/results.cfm.

PSoC Designer Subsystems

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PSoC Designer Software Subsystems

Device Editor

The Device Edi tor su bsyst em al lows th e use r to se lect di ffere nt onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.

PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conj unc tion with the D evice Data S heet . Once the framework is generated, the user can add application-specific code to flesh out the fr am ew ork . It’s also possible to change the selected components and regenerate the framework.

Design Browser

The Design Browser allows users to select and import preconfigured desi g ns into th e u se r’s project. Use rs ca n ea s il y br ow se a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tool s i nclude a 300-baud modem , LI N Bus master and slave, fan controller, and magnetic card reader.

Application Editor

In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build.

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of the USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are availa ble separa tely. The emulation pod takes t he place o f the PSoC device in the ta rget board and perfo rms full speed (24 MHz) operation.

Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use abso lut e addre ssing or ca n be co mpil ed in relat ive mode, and linked with other software modules to get absolute addressing.

C Language Compiler. A C language compiler is available that supports Cypress MicroSystems’ PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices.

The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

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Designing with User Modules

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and d igital hard ware blocks give the PS oC archite cture a unique flexibility that p ays d ivide nds in mana gi ng specifi catio n change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its fu nction and connectivity to other blocks, multiplexers, buses, and to the IO pins. Iterative devel op men t cy cl es perm it y ou to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements.

To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular applicati on. For exam ple, a Pulse Width Modula tor User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run-time. The API als o provides o ptional inte rrupt servic e routines that you can adapt as needed.

The API functions are documented in user module data sheets that are viewed directly in the PSo C Desi gn er ID E. Th es e data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user mod ule p ara me ter a nd d oc um ent s the setting of each register controlled by the user module.

The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to develo ping co de for the proj ect, yo u perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specif ic atio n an d pro vi des the high -le vel us er module API functions.

Device Editor

User

M odule

Selection

Placement

and

Parameter

-ization

Source

Code

Generator

Generate Application

Application Editor

Project

M anager

Source

Code Editor

Build

M anager

B uild All

Debugger

Interface

to ICE

Storage

Inspector

Event &

Break p oint

M anager

User Module and Source Code Development Flows

The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming.

The last step in the devel opm en t proc es s t ak es pla ce insi de the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint event s tha t inc lu de m oni tori ng ad dres s and da t a bu s values, memory locations and external signals.

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CY8C29x66 Final Data Sheet PSoC™ Overview

Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this document.

Acronym Description

AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-to- analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory FSR full scale range GPIO general purpose IO GUI graphical user interface HBM human body model ICE in-circuit emul ato r ILO internal low speed oscillator IMO internal main oscillator IO input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoC™ Programmable System-on-Chip™ PWM pulse width modulator SC switched capacitor SLIMO slow IMO SMP switch mode pump SRAM static random access memory

Units of Measure

A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 17 lists all the abbreviations used to measure the PSoC devices.

Numeric Naming

Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexi d ec im al nu mber s ma y al so be re p res en t ed by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.

Table of Contents

For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed Signal Array Technical Refer- ence Manual. This document encompasses and is organized into the following chapters and sections.

1. Pin Information ............................................................. 8

1.1 Pinouts ................................................................... 8

1.1.1 28-Pin Part Pinout ...................................... 8

1.1.2 44-Pin Part Pinout ...................................... 9

1.1.3 48-Pin Part Pinouts ...................................10

1.1.4 100-Pin Part Pinout ..................................12

2. Register Reference ..................................................... 14

2.1 Register Conventions ........................................... 14

2.1.1 Abbreviations Used .................................. 14

2.2 Register Mapping Tables ..................................... 14

3. Electrical Specifications ............................................ 17

3.1 Absolute Maximum Ratings ................................. 18

3.2 Operating Temperature ........................................ 18

3.3 DC Electrical Characteristics ................................19

3.3.1 DC Chip-Level Specifications ................... 19

3.3.2 DC General Purpose IO Specifications .... 19

3.3.3 DC Operational Amplifier Specifications ... 20

3.3.4 DC Analog Output Buffer Specifications ... 22

3.3.5 DC Switch Mode Pump Specifications ..... 23

3.3.6 DC Analog Reference Specifications ....... 24

3.3.7 DC Analog PSoC Block Specifications ..... 25

3.3.8 DC POR, SMP, and LVD Specifications ... 25

3.3.9 DC Programming Specifications ............... 26

3.4 AC Electrical Characteristics ................................ 27

3.4.1 AC Chip-Level Specifications ................... 27

3.4.2 AC General Purpose IO Specifications .... 29

3.4.3 AC Operational Amplifier Specifications ... 30

3.4.4 AC Digital Block Specifications ................. 32

3.4.5 AC Analog Output Buffer Specifications ... 33

3.4.6 AC External Clock Specifications ............. 34

3.4.7 AC Programming Specifications ............... 34

3.4.8 AC I2C Specifications ...............................35

4. Packaging Information ...............................................36

4.1 Packaging Dimensions .........................................36

4.2 Thermal Impedances ........................................... 40

4.3 Capacitance on Crystal Pins ................................40

4.4 Solder Reflow Peak Temperature ........................ 40

5. Ordering Information .................................................. 41

5.1 Ordering Code Definitions .................................... 41

6. Sales and Service Information .................................. 42

6.1 Revision History ...................................................42

6.2 Copyrights and Code Protection .......................... 42

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1. Pin Information

This chapter describes, lists, and illustrates the CY8C29x66 PSoC device pins and pinout configurations.

1.1 Pinouts

The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capab le of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.

1.1.1 28-Pin Part Pinout

Table 1-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)

Pin No.

1 IO I P0[7] Analog column mux input. 2 IO IO P0[5] Analog column mux input and column output. 3 IO IO P0[3] Analog column mux input and column output. 4 IO I P0[1] Analog column mux input. 5 IO P2[7] 6 IO P2[5] 7 IO I P2[3] Direct switched capacitor block input. 8 IO I P2[1] Direct switched capacitor block input. 9 Power SMP Switch Mode Pump (SMP) connection to

10 IO P1[7] I2C Serial Clock (SCL). 11 IO P1[5] I2C Serial Data (SDA). 12 IO P1[3] 13 IO P1[1] Crystal (XTALin), I2C Serial Clock (SCL). 14 Power Vss Ground connection. 15 IO P1[0] Crystal (XTALout), I2C Serial Data (SDA). 16 IO P1[2] 17 IO P1[4] Optional External Clock Input (EXT CLK). 18 IO P1[6] 19 Input XRES Active high external reset with internal pull

20 IO I P2[0] Direct switched capacitor block input. 21 IO I P2[2] Direct switched capacitor block input. 22 IO P2[4] External Analog Ground (AGND). 23 IO P2[6] External Voltage Reference (VREF). 24 IO I P0[0] Analog column mux input. 25 IO IO P0[2] Analog column mux input and column output. 26 IO IO P0[4] Analog column mux input and column output. 27 IO I P0[6] Analog column mux input. 28 Power Vdd Supply voltage.

Type

Digital Analog

Name

external components required.

down.

Description

CY8C29466 28-Pin PSoC Device

A, I, P0[7] A, IO, P0[5] A, IO, P0[3]

A, I, P0[1]

A, I, P2[3]

A, I, P2[1]

I2C SCL, P1[7]

I2C SDA, P1[5]

I2C SCL, XTALin, P1[1]

P2[7] P2[5]

SMP

P1[3]

Vss

10 11 12 13 14

1 2 3 4 5 6 7 8 9

PDIP

SSOP

SOIC

Vdd

28 27

P0[6], A, I P0[4], A, IO

P0[2], A, IO

P0[0], A, I

24 23

P2[6], External VREF P2[4], External AGND

P2[2], A, I

21 20

P2[0], A, I XRES

P1[6]

P1[4], EXTCLK

17 16

P1[2] P1[0], XTALout, I2C SDA

LEGEND: A = Analog, I = Input, and O = Output.

November 12, 2004 Document No. 38-12013 Rev. *G 8

Page 9

CY8C29x66 Final Data Sheet 1. Pin Information

1.1.2 44-Pin Part Pinout

Table 1-2. 44-Pin Part Pinout (TQFP)

Pin No.

1 IO P2[5] 2 IO I P2[3] Direct switched capacitor block input. 3 IO I P2[1] Direct switched capacitor block input. 4 IO P4[7] 5 IO P4[5] 6 IO P4[3] 7 IO P4[1] 8 Power SMP Switch Mode Pump (SMP) connection to

9 IO P3[7] 10 IO P3[5] 11 IO P3 [3] 12 IO P3[1] 13 IO P1[7] I2C Serial Clock (SCL). 14 IO P1[5] I2C Serial Data (SDA). 15 IO P1[3] 16 IO P1[1] Crystal (XTALin), I2C Serial Clock (SCL). 17 Power Vss Ground connection. 18 IO P1[0] Crystal (XTALout), I2C Serial Data (SDA). 19 IO P1[2] 20 IO P1[4] Optional External Clock Input (EXTCLK). 21 IO P1[6] 22 IO P3[0] 23 IO P3[2] 24 IO P3[4] 25 IO P3[6] 26 Input XRES Active high external reset with internal pull

27 IO P4[0] 28 IO P4[2] 29 IO P4[4] 30 IO P4[6] 31 IO I P2[0] Direct switched capacitor block input. 32 IO I P2[2] Direct switched capacitor block input. 33 IO P2 [4] External Analog Ground (AGND). 34 IO P2[6] External Voltage Reference (VREF). 35 IO I P0[0] Analog column mux input. 36 IO IO P0[2] Analog column mux input and c olumn outpu t. 37 IO IO P0[4] Analog column mux input and c olumn outpu t. 38 IO I P0[6] Analog column mux input. 39 Power Vdd Supply voltage. 40 IO I P0[7] Analog column mux input. 41 IO IO P0[5] Analog column mux input and c olumn outpu t. 42 IO IO P0[3] Analog column mux input and c olumn outpu t. 43 IO I P0[1] Analog column mux input. 44 IO P2[7]

Type

Digital Analog

Name

external components required.

down.

Description

A, I, P2[3] P2[2], A, I A, I, P2[1]

CY8C29566 44-Pin PSoC Device

P0[2], A, IO

P0[0], A, I

P0[7], A, I

Vdd

P0[5], A, IO

TQFP

I2C SCL, XTALin, P1[1]

P0[6], A, I

Vss

I2C SDA, XTALout, P1[0]

P0[1], A, I

P0[3], A, IO

P2[7]

P2[5]

P4[7] P4[5] P4[4] P4[3] P4[1]

SMP XRES P3[7] P3[6] P3[5] P3[4]

P3[3] P3[2]

4443424140393837363534

1 2 3 4 5 6 7 8

9 10 11

131415161718192021

P1[3]

P3[1]

I2C SCL, P 1 [7 ]

I2C SDA, P1[5]

P2[6 ], Externa l VREF

P0[4], A, IO

P2 [4], Exte rna l AGND 32 31

P2 [0 ], A , I

P4[6]

30 29

P4[2]

P4[0]

27 26 25 24 23

P1[6]

P3[0]

P1[2]

EXTCLK, P1[4]

LEGEND: A = Analog, I = Input, and O = Output.

November 12, 2004 Document No. 38-12013 Rev. *G 9

Page 10

CY8C29x66 Final Data Sheet 1. Pin Information

1.1.3 48-Pin Part Pinouts

Table 1-3. 48-Pin Part Pinout (SSOP)

Pin No.

1 IO I P0[7] Analog column mux input. 2 IO IO P0[5] Analog co l umn mux input and column ou tput. 3 IO IO P0[3] Analog co l umn mux input and column ou tput. 4 IO I P0[1] Analog column mux input. 5 IO P2[7] 6 IO P2[5] 7 IO I P2[3] Direct switched capacitor block input. 8 IO I P2[1] Direct switched capacitor block input. 9 IO P4[7] 10 IO P4[5] 11 IO P4[3] 12 IO P4[1] 13 Power SMP Switch Mode Pump (SMP) conne ct ion to

14 IO P3[7] 15 IO P3[5] 16 IO P3[3] 17 IO P3[1] 18 IO P5[3] 19 IO P5[1] 20 IO P1[7] I2C Serial Clock (SCL). 21 IO P1[5] I2C Serial Data (SDA). 22 IO P1[3] 23 IO P1[1] Crystal (XTALin), I2C Serial Clock (SCL). 24 Power Vss Ground connection. 25 IO P1[0] Crystal (XTALout), I2C Serial Data (SDA). 26 IO P1[2] 27 IO P1[4] Optional External Clock Input (EXTCLK). 28 IO P1[6] 29 IO P5[0] 30 IO P5[2] 31 IO P3[0] 32 IO P3[2] 33 IO P3[4] 34 IO P3[6] 35 Input XRES Active high external reset with internal pul l

36 IO P4[0] 37 IO P4[2] 38 IO P4[4] 39 IO P4[6] 40 IO I P2[0] Direct switched capacitor block input. 41 IO I P2[2] Direct switched capacitor block input. 42 IO P2[4] External Analog Ground (AGND). 43 IO P2[6] External Voltage Reference (VREF). 44 IO I P0[0] Analog column mux input. 45 IO IO P0[2] Analog column mux input and c olumn outpu t. 46 IO IO P0[4] Analog column mux input and c olumn outpu t. 47 IO I P0[6] Analog column mux input. 48 Power Vdd Supply voltage.

Type

Digital Analog

Name

external components required.

down.

Description

I2C SCL, XTAL in, P1[1]

CY8C29666 48-Pin PSoC Device

A, I, P0[7] A, IO, P0[5] A, IO, P0[3]

P2[7]

P2[5] A, I, P2[3] A, I, P2[1]

P4 [7 ] P2[0 ], A, I

P4[5]

P4[3]

P4[1]

SMP P3[7] P3[5] P3[3] P3[4] P3[1] P5[3] P5[1]

I2C SCL, P1 [7]

I2C SDA, P1[5]

P1[3]

Vss

1 2 3 4

6 7

10 11 12

SSOP

13 14 15 16 17 18 19 20 21 22

Vdd

P0 [6 ], A , I

P0 [4 ], A , IO

P0 [2 ], A , IOA, I, P0[1]

P0 [0 ], A , I

P2 [6], Exte rna l VREF

43 42

P2 [4], Exte rna l AGND P2 [2 ], A , I

41 40 39

P4[6] P4[4]

P4[2]

37 36

P4[0] XRES

P3[6]

34 33

P3[2]

P3[0]

P5[2]

P5[0]

P1[6]

P1[4], EX TCLK

P1[2]

P1[0], XTALout, I2 C SDA

LEGEND: A = Analog, I = Input, and O = Output.

November 12, 2004 Document No. 38-12013 Rev. *G 10

Page 11

CY8C29x66 Final Data Sheet 1. Pin Information

Table 1-4. 48-Pin Part Pinout (MLF*)

Pin No.

1 IO I P2[3] Direct switched capacitor block input. 2 IO I P2[1] Direct switched capacitor block input. 3 IO P4[7] 4 IO P4[5] 5 IO P4[3] 6 IO P4[1] 7 Power SMP Switch Mode Pump (SMP) connection to

8 IO P3[7] 9 IO P3[5] 10 IO P3[3] 11 IO P3 [1] 12 IO P5[3] 13 IO P5[1] 14 IO P1[7] I2C Serial Clock (SCL). 15 IO P1[5] I2C Serial Data (SDA). 16 IO P1[3] 17 IO P1[1] Crystal (XTALin), I2C Serial Clock (SCL). 18 Power Vss Ground connection. 19 IO P1[0] Crystal (XTALout), I2C Serial Data (SDA). 20 IO P1[2] 21 IO P1[4] Optional External Clock Input (EXTCLK). 22 IO P1[6] 23 IO P5[0] 24 IO P5[2] 25 IO P3[0] 26 IO P3[2] 27 IO P3[4] 28 IO P3[6] 29 Input XRES Active high external reset with internal pull

30 IO P4[0] 31 IO P4[2] 32 IO P4[4] 33 IO P4[6] 34 IO I P2[0] Direct switched capacitor block input. 35 IO I P2[2] Direct switched capacitor block input. 36 IO P2 [4] External Analog Ground (AGND). 37 IO P2[6] External Voltage Reference (VREF). 38 IO I P0[0] Analog column mux input. 39 IO IO P0[2] Analog column mux input and c olumn outpu t. 40 IO IO P0[4] Analog column mux input and c olumn outpu t. 41 IO I P0[6] Analog column mux input. 42 Power Vdd Supply voltage. 43 IO I P0[7] Analog column mux input. 44 IO IO P0[5] Analog column mux input and c olumn outpu t. 45 IO IO P0[3] Analog column mux input and c olumn outpu t. 46 IO I P0[1] Analog column mux input. 47 IO P2[7] 48 IO P2[5]

Type

Digital Analog

Name

external components required.

down.

Description

A, I, P2[3] A, I, P2[1]

CY8C29666 48-Pin PSoC Device

P2[5]

P2[7]

P0[1], A, I

P0[3], A, IO

P0[5], A, IO

P0[7], A, I

Vdd

4847464544434241403938

1 2

P4[7]

P4[5]

P4[3]

5 6

P4[1]

SMP P3[7] P3[5] P3[3] P3[1] P5[3]

7 8

9 10 11 12

1314151617181920212223

P5[1]

I2C SC L, P1 [7]

MLF

(Top View )

P1[3]

I2C S DA, P1[ 5]

I2C SC L, XTALin, P1[1]

Vss

I2C SD A, XTALout, P1[0 ]

P0[6], A, I

P0[4], A, IO

P0[2], A, IO

P0[0], A, I

P2[6], Exte rnal VREF

P2 [4], Exte rna l AGN

P2 [2 ], A , I

P2 [0 ], A , I

P4[6]

P4[4]

P4[2]

P4[0]

XRES

P3[6]

P3[4]

P3[2]

P3[0]

P1[2]

P1[6]

P5[0]

P5[2]

EXTCLK, P1[4]

LEGEND: A = Analog, I = Input, and O = Output.

* The MLF package has a center pad that must be connected to ground (Vss).

November 12, 2004 Document No. 38-12013 Rev. *G 11

Page 12

CY8C29x66 Final Data Sheet 1. Pin Information

1.1.4 100-Pin Part Pinout

Table 1-5. 100-Pin Part Pinout (TQFP)

Pin No.

1 NC No connection. 51 NC No connection. 2 NC No connection. 52 IO P5[0] 3 IO I P0[1] Analog column mux input. 53 IO P5[2] 4 IO P2[7] 54 IO P5[4] 5 IO P2[5] 55 IO P5[6] 6 IO I P2[3] Direct switched capacitor block input. 56 IO P3[0] 7 IO I P2[1] Direct switched capacitor block input. 57 IO P3[2] 8 IO P4[7] 58 IO P3[4] 9 IO P4[5] 59 IO P3[6] 10 IO P4[3] 60 NC No connection. 11 IO P4[1] 61 NC No connection. 12 NC No connection. 62 Input XRES Active high external reset with internal pull

13 NC No connection. 63 IO P4[0] 14 Power SMP Switch Mode Pump (SMP) connection to

15 Power Vss Ground connection. 65 Power V ss Ground connection. 16 IO P3[7] 66 IO P4[4] 17 IO P3[5] 67 IO P4[6] 18 IO P3[3] 68 IO I P2[0] Direct switched capacitor block input. 19 IO P3[1] 69 IO I P2[2] Direct switched capacitor block input. 20 IO P5[7] 70 IO P2[4] External Analog Ground (AGND). 21 IO P5[5] 71 NC No connection. 22 IO P5[3] 72 IO P2[6] External Voltage Reference (VREF). 23 IO P5[1] 73 NC No connection. 24 IO P1[7] I2C Serial Clock (SCL). 74 IO I P0[0] Analog column mux input. 25 NC No connection. 75 NC No connection. 26 NC No connection. 76 NC No connection. 27 NC No connection. 77 IO IO P0[2] Analog column mux input and column output. 28 IO P1[5] I2C Serial Data (SDA). 78 NC No connection. 29 IO P1[3] 79 IO IO P0[4] Analog column mux input and column output. 30 IO P1[1] Crystal (XTALin), I2C Serial Clock (SCL). 80 NC No connection. 31 NC No connection. 81 IO I P0[6] Analog column mux input. 32 Power Vdd Supply voltage. 82 Power Vdd Supply voltage. 33 NC No connection. 83 Power Vdd Supply voltage. 34 Power Vss Ground connection. 84 Power Vss Ground connection. 35 NC No connection. 85 Power Vss Ground connection. 36 IO P7[7] 86 IO P6[0] 37 IO P7[6] 87 IO P6[1] 38 IO P7[5] 88 IO P6[2] 39 IO P7[4] 89 IO P6[3] 40 IO P7[3] 90 IO P6[4] 41 IO P7[2] 91 IO P6[5] 42 IO P7[1] 92 IO P6[6] 43 IO P7[0] 93 IO P6[7] 44 IO P1[0] Crystal (XTALout), I2C Serial Data (SDA). 94 NC No connection. 45 IO P1[2] 95 IO I P0[7] Analog column mux input. 46 IO P1[4] Optional External Clock Input (EXTCLK). 96 NC No connection. 47 IO P1[6] 97 IO IO P0[5] Analog column mux input and column output. 48 NC No connection. 98 NC No connection. 49 NC No connection. 99 IO IO P0[3] Analog column mux input and column output. 50 NC No connection. 100 NC No connection.

Type

Digital Analog Digital Analog

Name Description

external componen ts requ i red.

Pin No.

64 IO P4[2]

Type

Name Description

down.

LEGEND: A = Analog, I = Input, and O = Output.

November 12, 2004 Document No. 38-12013 Rev. *G 12

Page 13

CY8C29x66 Final Data Sheet 1. Pin Information

CY8C29866 100-Pin PSoC Device

P0 [3 ], A , IONCP0 [5 ], A , IONCP0 [7 ], A , INCP6[7]

P6[6]

P6[5]

P6[4]

P6[3]

P6[2]

P6[1]

P6[0]

Vss

Vdd

P0 [6 ], A , INCP0 [4 ], A , IONCP0 [2 ], A , IO

NC NC

A, I, P0[1 ]

P2[7] P2[5]

A, I, P2[3 ] A, I, P2[1 ]

P4[7] P4[5] P4[3]

P4[1]

NC NC

SMP

Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1]

I2C SCL , P1[7]

9998979695949392919089888786858483828180797877

100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

20 21 22 23 24 25

26272829303132333435363738394041424344454647485049

Vdd

P1[3]

TQFP

Vss

P7[7]

P7[3]

P7[6]

P7[5]

P7[4]

P7[2]

P7[1]

P7[0]

P1[2]

NCNCNC

P1[6]

75 74

P0[0], A, I NC

P2[6], External VREF

72 71

P2[4], External AGND P2[2], A, I

P2[0], A, I

P4[6]

P4[4]

Vss

P4[2]

P4[0]

63 62

XRES

NC NC

P3[6]

P3[4]

P3[2]

P3[0]

P5[6]

P5[4]

P5[2]

P5[0]

52 51

I2C SDA, P1[5]

XTALin, I2C SCL , P1[1]

EXTCLK, P1[4]

XTALout, I2C SDA , P1[0]

November 12, 2004 Document No. 38-12013 Rev. *G 13

Page 14

2. Register Reference

This chapter lists the registers of the CY8C29x66 PSoC device. For detailed register information, reference the PSoC™ Mixed-Signal Array Technical Reference Manual.

2.1 Register Conventions

2.1.1 Abbreviations Used

The register conventions specific to this section are listed in the following table.

Convention Description

R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific

2.2 Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag regist er (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are reserved and should not be accessed.

November 12, 2004 Document No. 38-12013 Rev. *G 14

Page 15

CY8C29x66 Final Data Sheet 2. Register Reference

Access

Name

PRT0DR 00 RW DBB20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW PRT0IE 01 RW DBB20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW PRT0GS 02 RW DBB20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW PRT0DM2 03 RW DBB20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW PRT1DR 04 RW DBB21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW PRT1IE 05 RW DBB21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW PRT1GS 06 RW DBB21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW PRT1DM2 07 RW DBB21CR0 47 # ASD11CR3 87 RW C7 PRT2DR 08 RW DCB22DR0 48 # ASC12CR0 88 RW RDI3RI C8 RW PRT2IE 09 RW DCB22DR1 49 W ASC12CR1 89 RW RDI3SYN C9 RW PRT2GS 0A RW DCB22DR2 4A RW ASC12CR2 8A RW RDI3IS CA RW PRT2DM2 0B RW DCB22CR0 4B # ASC12CR3 8B RW RDI3LT0 CB RW PRT3DR 0C RW DCB23DR0 4C # ASD13CR0 8C RW RDI3LT1 CC RW PRT3IE 0D RW DCB23DR1 4D W ASD13CR1 8D RW RDI3RO0 CD RW PRT3GS 0E RW DCB23DR2 4E RW ASD13CR2 8E RW RDI3RO1 CE RW PRT3DM2 0F RW DCB23CR0 4F # ASD13CR3 8F RW CF PRT4DR 10 RW DBB30DR0 50 # ASD20CR0 90 RW CUR_PP D0 RW PRT4IE 11 RW DBB30DR1 51 W ASD20CR1 91 RW STK_PP D1 RW PRT4GS 12 RW DBB30DR2 52 RW ASD20CR2 92 RW D2 PRT4DM2 13 RW DBB30CR0 53 # ASD20CR3 93 RW IDX_PP D3 RW PRT5DR 14 RW DBB31DR0 54 # ASC21CR0 94 RW MVR_PP D4 RW PRT5IE 15 RW DBB31DR1 55 W ASC21CR1 95 RW MVW_PP D5 RW PRT5GS 16 RW DBB31DR2 56 RW ASC21CR2 96 RW I2C_CFG D6 RW PRT5DM2 17 RW DBB31CR0 57 # ASC21CR3 97 RW I2C_SCR D7 # PRT6DR 18 RW DCB32DR0 58 # ASD22CR0 98 RW I2C_DR D8 RW PRT6IE 19 RW DCB32DR1 59 W ASD22CR1 99 RW I2C_MSCR D9 # PRT6GS 1A RW DCB32DR2 5A RW ASD22CR2 9A RW INT_CLR0 DA RW PRT6DM2 1B RW DCB32CR0 5B # ASD22CR3 9B RW INT_CLR1 DB RW PRT7DR 1C RW DCB33DR0 5C # ASC23CR0 9C RW INT_CLR2 DC RW PRT7IE 1D RW DCB33DR1 5D W ASC23CR1 9D RW INT_CLR3 DD RW PRT7GS 1E RW DCB33DR2 5E RW ASC23CR2 9E RW INT_MSK3 DE RW PRT7DM2 1F RW DCB33CR0 5F # ASC23CR3 9F RW INT_MSK2 DF RW DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCB02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCB02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R DCB02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R DCB03DR0 2C # TMP0_DR 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCB03DR1 2D W TMP1_DR 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCB03DR2 2E RW TMP2_DR 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCB03CR0 2F # TMP3_DR 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW DBB10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0 DBB10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1 DBB10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2 DBB10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3 DBB11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4 DBB11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBB11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6 DBB11CR0 37 # ACB01CR2 77 RW B7 CPU_F F7 RL DCB12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8 DCB12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9 DCB12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA DCB12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB DCB13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FC DCB13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW FD DCB13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE # DCB13CR0 3F # ACB03CR2 7F RW BF CPU_SCR0 FF # Blank fields are Reserved and should not be accessed. # Access is bit specific.

(0,Hex)

Addr

Name

Access

(0,Hex)

Addr

Name

Access

(0,Hex)

Addr

Name

Access

(0,Hex)

Addr

November 12, 2004 Document No. 38-12013 Rev. *G 15

Page 16

CY8C29x66 Final Data Sheet 2. Register Reference

Access

Name

PRT0DM0 00 RW DBB20FN 40 RW ASC10CR0 80 RW RDI2RI C0 RW PRT0DM1 01 RW DBB20IN 41 RW ASC10CR1 81 RW RDI2SYN C1 RW PRT0IC0 02 RW DBB20OU 42 RW ASC10CR2 82 RW RDI2IS C2 RW PRT0IC1 03 RW 43 ASC10CR3 83 RW RDI2LT0 C3 RW PRT1DM0 04 RW DBB21FN 44 RW ASD11CR0 84 RW RDI2LT1 C4 RW PRT1DM1 05 RW DBB21IN 45 RW ASD11CR1 85 RW RDI2RO0 C5 RW PRT1IC0 06 RW DBB21OU 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 PRT2DM0 08 RW DCB22FN 48 RW ASC12CR0 88 RW RDI3RI C8 RW PRT2DM1 09 RW DCB22IN 49 RW ASC12CR1 89 RW RDI3SYN C9 RW PRT2IC0 0A RW DCB22OU 4A RW ASC12CR2 8A RW RDI3IS CA RW PRT2IC1 0B RW 4B ASC12CR3 8B RW RDI3LT0 CB RW PRT3DM0 0C RW DCB23FN 4C RW ASD13CR0 8C RW RDI3LT1 CC RW PRT3DM1 0D RW DCB23IN 4D RW ASD13CR1 8D RW RDI3RO0 CD RW PRT3IC0 0E RW DCB23OU 4E RW ASD13CR2 8E RW RDI3RO1 CE RW PRT3IC1 0F RW 4F ASD13CR3 8F RW CF PRT4DM0 10 RW DBB30FN 50 RW ASD20CR0 90 RW GDI_O_IN D0 RW PRT4DM1 11 RW DBB30IN 51 RW ASD20CR1 91 RW GDI_E_IN D1 RW PRT4IC0 12 RW DBB30OU 52 RW ASD20CR2 92 RW GDI_O_OU D2 RW PRT4IC1 13 RW 53 ASD20CR3 93 RW GDI_E_OU D3 RW PRT5DM0 14 RW DBB31FN 54 RW ASC21CR0 94 RW D4 PRT5DM1 15 RW DBB31IN 55 RW ASC21CR1 95 RW D5 PRT5IC0 16 RW DBB31OU 56 RW ASC21CR2 96 RW D6 PRT5IC1 17 RW 57 ASC21CR3 97 RW D7 PRT6DM0 18 RW DCB32FN 58 RW ASD22CR0 98 RW D8 PRT6DM1 19 RW DCB32IN 59 RW ASD22CR1 99 RW D9 PRT6IC0 1A RW DCB32OU 5A RW ASD22CR2 9A RW DA PRT6IC1 1B RW 5B ASD22CR3 9B RW DB PRT7DM0 1C RW DCB33FN 5C RW ASC23CR0 9C RW DC PRT7DM1 1D RW DCB33IN 5D RW ASC23CR1 9D RW OSC_GO_EN DD RW PRT7IC0 1E RW DCB33OU 5E RW ASC23CR2 9E RW OSC_CR4 DE RW PRT7IC1 1F RW 5F ASC23CR3 9F RW OSC_CR3 DF RW DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

DBB01FN 24 RW 64 A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6

DCB02FN 28 RW ALT_CR1 68 RW A8 IMO_TR E8 W DCB02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_T R EA RW

DCB03FN 2C RW TMP0_DR 6C RW AC EC DCB03IN 2D RW TMP1_DR 6D RW AD ED DCB03OU 2E RW TMP2_DR 6E RW AE EE

DBB10FN 30 RW ACB00CR3 70 RW RDI0RI B0 RW F0 DBB10IN 31 RW ACB00CR0 71 RW RDI0SYN B1 RW F1 DBB10OU 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2

DBB11FN 34 RW ACB01CR3 74 RW RDI0LT1 B4 RW F4 DBB11IN 35 RW ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBB11OU 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6

DCB12FN 38 RW ACB02CR3 78 RW RDI1RI B8 RW F8 DCB12IN 39 RW ACB02CR0 79 RW RDI1SYN B9 RW F9 DCB12OU 3A RW ACB02CR1 7A RW RDI1IS BA RW FLS_PR1 FA RW

DCB13FN 3C RW ACB03CR3 7C RW RDI1LT1 BC RW FC DCB13IN 3D RW ACB03CR0 7D RW RDI1RO0 BD RW FD DCB13OU 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #

Blank fields are Reserved and should not be accessed. # Access is bit specific.

(1,Hex)

Addr

23 AMD_CR0 63 RW A3 VLT_CR E3 RW

27 ALT_CR0 67 RW A7 DEC_CR2 E7 RW

2B 6B AB ECO_TR EB W

2F TMP3_DR 6F RW AF EF

33 ACB00CR2 73 RW RDI0LT0 B3 RW F3

37 ACB01CR2 77 RW B7 CPU_F F7 RL

3B ACB02CR2 7B RW RDI1LT0 BB RW FB

3F ACB03CR2 7F RW BF CPU_SCR0 FF #

Name

Access

(1,Hex)

Addr

Name

Access

(1,Hex)

Addr

Name

(1,Hex)

Addr

Access

November 12, 2004 Document No. 38-12013 Rev. *G 16

Page 17

3. Electrical S pecifications

This chapter presents the DC and AC electrical specifications of the CY8C29x66 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifi cations are valid for -40 Refer to Table 3-16 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.

C ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted.

5.25

4.75

Vdd Voltage

3.00

93 kHz 12 MHz 24 MHz

CPU Frequency

5.25

SLIMO

Mode=1

4.75

Vdd Voltage

SLIMO

Mode=0

SLIMO Mode = 0

3.60

3.00

93 kHz

SLIMO

Mode=1

6 MHz

IMO Frequency

SLIMO

Mode=0

12 MHz 24 MHz

Figure 3-1a. Voltage versus CPU Frequency Figure 3-1b. IMO Frequency Trim Options

The following table lists the units of measure that are used in this chapter.

Table 3-1: Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

dB decibels mA milli-ampere

fF femto farad ms milli-second Hz hertz mV milli-volts KB 1024 bytes nA nanoampere

Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts

kΩ kilohm Ω ohm

MHz megahertz pA picoampere

MΩ megaohm pF picofarad

µA microampere pp peak-to-peak µF microfarad ppm parts per million µH microhenry ps picosecond

µs microsecond sps samples per second µV microvolts σ sigma: one standard deviation

µVrms microvolts root-mean-square V volts

degree Cels i us µW microwatts

November 12, 2004 Document No. 38-12013 Rev. *G 17

Page 18

CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.1 Absolute Maximum Ratings

Table 3-2: Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

STG

Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V V

IOZ

MIO

MAIO

ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD. LU Latch-up C urrent – – 200 mA

Storage Tempera ture -55 – +100

Ambient Temperature with Power Applied -40 – +85

DC Input Voltage Vss - 0.5 – Vdd + 0.5 V DC Voltage App lie d to Tri-state Vss - 0.5 – Vdd + 0.5 V Maximum Current into any Port P in -25 – +50 mA Maximum Cu rrent into any Port Pin Conf igured as Analog

Driver

-50 – +50 mA

Higher storage temperature s w ill re duce data retention time.

3.2 Operating Temperature

Table 3-3: Operating Temperature

Symbol Description Min Typ Max Units Notes

Ambient Temperature -40 – +85 Junction Temperature -40 – +100

The temper ature rise from ambie nt to junc tion i s package specific. See “Thermal Impedances”

on page 40. The user must limit the power con-

sumption to comply with this requirement.

November 12, 2004 Document No. 38-12013 Rev. *G 18

Page 19

CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.3 DC Electrical Characteristics

3.3.1 DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-4: DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 3.00 – 5.25 V See DC POR and LVD specifications, Table 3-

DD3

DDP

SBH

SBXTL

SBXTLH

REF

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

14 on page 25.

Supply Current – 8 14 mA

Supply Current – 5 9 mA

Supply current when IMO = 6 MHz using SLIMO mode. – 2 3 mA

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator, and 32 kHz crystal oscillator active.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and 32 kHz crystal oscillator active.

Reference Voltage (Bandgap) 1.28 1.3 1.32 V Trimmed for appropriate Vdd.

– 3 10 µA Conditions are wit h internal slow speed oscilla-

– 4 25 µA Conditions are wit h internal slow speed oscilla-

– 4 12 µA Conditions are with properly load ed, 1 µW max,

– 5 27 µA Conditions are with properly load ed, 1 µW max,

Conditions are 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2

= 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3

MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz.

Conditions are Vdd = 3.3V, TA = 25 oC, CPU =

0.75 MHz, SYSCLK doubler disabled, VC1 =

0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz.

tor, Vdd = 3.3V, -40

tor, Vdd = 3.3V, 55

32.768 kHz crystal. Vdd = 3.3V , -40

32.768 kHz crystal. Vdd = 3.3V, 55

C ≤ TA ≤ 55 oC.

C < TA ≤ 85 oC.

C ≤ TA ≤ 55

C < TA ≤ 85

3.3.2 DC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-5: DC GPIO Specifications

Symbol Description Min Typ Max Units Notes

OUT

November 12, 2004 Document No. 38-12013 Rev. *G 19

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Pull up Resistor 4 5. 6 8 kΩ Pull down Resistor 4 5.6 8 kΩ High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

Low Output Level – – 0.75 V IOL = 25 mA, Vd d = 4.75 to 5.25 V (8 to tal load s,

Input Low Level – – 0.8 V Vdd = 3.0 to 5.25. Input High Level 2.1 – V Vdd = 3.0 to 5.25. Input Hysterisis – 60 – mV Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 µA. Capacitive Load on Pins as Input – 3.5 10 pF Capacitive Load on Pins as Output – 3.5 10 pF

4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1 [5])). 80 mA maximum combined IOH budget.

4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1 [5])). 150 mA maximum combined IOL budget.

Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC.

Page 20

CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.3.3 DC Operational Ampli fier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only. The Operatio nal Amplifier is a component of bo th the Analog Con tinuous Time PSoC bloc ks and the Analog Sw itched Capacitor

PSoC blocks. The guarant eed spe ci fic ati ons are mea sur ed i n the Anal og Continuous T i me PSoC block. Ty pic al p ara me ters app ly to 5V at 25°C and are for design guidance only.

Table 3-6: 5V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV

OSOA

EBOA

INOA

CMOA

CMRR

OLOA

OHIGHOA

OLOWOA

SOA

PSRR

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Average Input Offset Voltage Drift – 7.0 35.0

Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 µA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Common Mo de Voltage Range. A l l Cases, exce pt highest.

Power = High, Opamp Bias = High Common Mode Rejection Ratio 60 – – dB

Open Loop Gain 80 – – dB High Output Voltage Swing (internal signals) Vdd - .01 – – V Low Output Voltage Swing (internal signals) – – 0.1 V Supply Current (including associate d A GND buffer)

Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Volta g e Rejection Ratio 67 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤

–1.6 – –

0.0 – Vdd

– – – – – –

1.3

1.2

150 300 600 1200 2400 4600

10 8

7.5

Vdd - 0.5VV0.5 –

200 400 800 1600 3200 6400

mV mV mV

µV/

µA µA µA µA µA µA

Package and pin dependent. Temp = 25

VIN ≤ Vdd.

November 12, 2004 Document No. 38-12013 Rev. *G 20

Page 21

CY8C29x66 Final Data Sheet 3. Electrical Specifications

Table 3-7: 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV

OSOA

EBOA

INOA

CMOA

CMRR G

OLOA

OHIGHOA

OLOWOA

SOA

PSRR

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High

– –

1.65

1.32

10 8

mV High Power is 5 Volts Only Average Input Offset Voltage Drift – 7.0 35.0

µV/

Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 µA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF

Package and pin dependent. Temp = 25

Common Mode Voltage Range 0 – Vdd V Common Mode Rejection Ratio 60 – – dB

Open Loop Gain 80 – – dB High Output Voltage Swing (internal signals) Vdd - .01 – – V Low Output Voltage Swing (internal signals) – – .01 V Supply Current (including associate d A GND buffer)

Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High

Supply Volta ge R ejection Ratio 54 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) o r (Vdd - 1.25V ) ≤

– – – – – –

150 300 600 1200 2400 –

200 400 800 1600 3200 –

µA

Not Allowed

VIN ≤ Vdd

November 12, 2004 Document No. 38-12013 Rev. *G 21

Page 22

CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.3.4 DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-8: 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Input Offset Vo ltage (Absol ute Value) – 3 12 mV Average I nput Offset Voltage Drift – +6 – µV/°C Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V Output Resistance

Power = Low Power = High High Output Voltage Swing (Load = 32 ohms to Vdd/2)

Power = Low Power = High

– –

0.5 x Vdd + 1.3

0.5 x Vdd

+ 1.3

– –

1 1

– –

Ω

V V

Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High

– –

0.5 x Vdd - 1.3

0.5 x Vdd

- 1.3

V V

Supply Current Including Bias Cell (No Load) Power = Low Power = High

– –

1.1

2.6

2 5

mA mA

Supply Voltage Rejection Ratio 40 64 – dB

Table 3-9: 3.3V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV Average Input Offset Voltage Drift – +6 – µV/°C Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V Output Resistance

Power = Low Power = High

– –

10 High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High

0.5 x Vdd + 1.0

0.5 x Vdd

+ 1.0

– –

–

– Low Output Voltage Swing (Load = 1k ohms to Vdd/2)

Power = Low Power = High

– –

0.5 x Vdd - 1.0

0.5 x Vdd

Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Volta ge R ej ect io n R a tio 60 64 – dB

–

0.8

2.0

- 1.0

Ω

V V

mA mA

November 12, 2004 Document No. 38-12013 Rev. *G 22

Page 23

CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.3.5 DC Switch Mode Pump Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-10: DC Switch Mode Pump (SMP) Specifications

Symbol Description Min Typ Max Units Notes

5V 5V Output Voltage at Vdd from Pump 4.75 5.0 5.25 V

PUMP

3V 3V Output Voltage at Vdd from Pump 3.00 3.25 3.60 V

PUMP

5V Input Voltage Range from Battery 1.8 – 5.0 V

BAT

3V Input Voltage Range from Battery 1.0 – 3.3 V

BAT

BATSTART

∆V

PUMP_Line

∆V

PUMP_Load

∆V

PUMP_Ripple

PUMP

a. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure3-2.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Configuration of footnote.

Average, neglecting ripple. SMP

trip voltage is set to 5.0V.

Configuration of footnote.

Average, neglecting ripple. SMP

trip voltage is set to 3.25V.

Available Output Current

= 1.5V, V

BAT

= 1.8V, V

BAT

Minimum Input Voltage from Battery to Start Pump

Line Regulation (over V

PUMP PUMP

= 3.25V = 5.0V

range) – 5 – %V

BAT

8 5

– –

1.2 – – V

mA mA

Configuration of footnote. SMP trip voltage is set to 3.25V. SMP trip voltage is set to 5.0V.

Configuration of footnote. Configuration of footnote. Configuration of footnote.

Configuration of footnote.a VO is the “Vdd Value for PUMP

SMP trip voltage is set to 5.0V.

SMP trip voltage is set to 3.25V.

a 0o

C ≤ TA ≤ 100. 1.25V at TA = -

Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-14 on page 25.

Load Regulation – 5 – %V

Output Voltage Ripple (depends on capaci-

– 100 – mVpp

tor/load) Efficiency 35 50 – %

Configuration of footnote.a VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and

LVD Specification, Table 3-14 on page 25. Configuration of footnote.

Configuration of footnote. is set to 3.25V.

Load is 5 mA.

Load is 5 mA. SMP trip voltage

Switching Frequency – 1.4 – MHz Switching Duty Cycle – 50 – %

Vdd

BAT

Battery

SMP

Vss

PSoC

PUMP

Figure 3-2. Basic Switch Mode Pump Circuit

November 12, 2004 Document No. 38-12013 Rev. *G 23

Page 24

CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.3.6 DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only. The guaranteed specific ations are measure d throug h the Anal og Con tinuou s T im e PSoC block s. The powe r level s for AGND refer to

the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high.

Table 3-11: 5V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG5

– – – – – – – RefHi = Vdd/2 + BandGap – RefHi = 3 x BandGap 3.75 3.9 4.05 V

– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.058 P2[4] + P2[6] P2[4] + P2[6] + 0.058 V – RefHi = 2 x BandGap 2.50 2.60 2.70 V – RefHi = 3.2 x BandGap 4.02 4.16 4.29 V – RefLo = Vdd/2 – BandGap

– RefLo = BandGap 1.20 1.30 1.40 V – RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2.489 - P2[6] 2.6 - P2[6] 2.711 - P2[6] V – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - 1.368 P2[4] - 1.30 P2[4] - 1.232 V – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.042 P2[4] - P2[6] P2[4] - P2[6] + 0.042 V

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Bandgap Voltage Reference 5V 1.28 1.30 1.32 V AGND = Vdd/2

AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Block to Block Variation (AGND = Vdd/2)

Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V

2.52 2.60 2.72 V P2[4] - 0.013 P2[4] P2[4] + 0.013 V

1.27 1.3 1.34 V

2.03 2.08 2.13 V

-0.034 0.000 0.034 V

Vdd/2 + 1.21 Vdd/2 + 1.3 Vdd/2 + 1.382

Vdd/2 - 1.369 Vdd/2 - 1.30 Vdd/2 - 1.231

Table 3-12: 3.3V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG33

– – – AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.009 P2[4] P2[4] + 0.009 V

– – – – RefHi = Vdd/2 + BandGap Not Allowed

– RefHi = 3 x BandGap Not Allowed – RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.042 P2[4] + P2[6] P2[4] + P2[6] + 0.042 V – RefHi = 2 x BandGap 2.50 2.60 2.70 V – RefHi = 3.2 x BandGap Not Allowed – RefLo = Vdd/2 - BandGap Not Allowed – RefLo = BandGap Not Allowed – RefLo = 2 x BandGap - P2 [6] (P2[6] = 0.5V) Not Allowed – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.036 P2[4] - P2[6] P2[4] - P2[6] + 0.036 V

Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 V AGND = Vdd/2

AGND = 2 x BandGap

AGND = BandGap AGND = 1.6 x BandGap AGND Block to Block Variation (AGND = Vdd/2)

Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V Not Allowed

1.27 1.30 1.34 V

2.03 2.08 2.13 V

-0.034 0.000 0.034 mV

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

November 12, 2004 Document No. 38-12013 Rev. *G 24

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.3.7 DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-13: DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units Notes

Resistor Unit Value (Continuous Time) – 12.2 – kΩ Capacitor Unit Value (Switch Cap) – 80 – fF

3.3.8 DC POR, SMP, and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-14: DC POR, SMP, and LVD Specifications

Symbol Description Min Typ Max Units Notes

PPOR0R

PPOR1R

PPOR2R

PPOR0

PPOR1

PPOR2

PH0

PH1

PH2

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

PUMP0

PUMP1

PUMP2

PUMP3

PUMP4

PUMP5

PUMP6

PUMP7

a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

–

2.91

4.39

4.55

–

V V

Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

–

2.82

4.39

4.55

–

V V

PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

– – –

92 0 0

– – –

mV mV mV

Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

2.98

3.08

3.20

4.08

4.57

4.74

4.82

4.91

V V

V V V V

V V

V Vdd Value for SMP Trip VM[2:0] = 000b VM[2:0] = 001b

VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

2.96

3.03

3.18

4.11

4.55

4.63

4.72

4.90

3.02

3.10

3.25

4.19

4.64

4.73

4.82

5.00

3.08

3.16

3.32

4.28

4.74

4.82

4.91

5.10

November 12, 2004 Document No. 38-12013 Rev. *G 25

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.3.9 DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-15: DC Programming Specifications

Symbol Description Min Typ Max Units Notes

DDP

ILP

IHP

ILP

IHP

OLV

OHV

Flash

ENPB

Flash

ENT

Flash

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Supply Current During Programming or Verify – 10 30 mA Input Low Voltage During Programming or Verify – – 0.8 V Input High Voltage During Programming or Verify 2.2 – – V Input Current when Applying Vilp to P1[0] or P1[1] During

Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During

Programming or Verify Output Low Voltage During Programming or Ve rify – – Vss + 0.75 V

Output High Voltage During Programming or Verify Vdd - 1.0 – Vdd V Flash Endurance (per block) 50,000 – – – Erase/write cycles per block. Flash Endurance (total)

Flash Data Retention 10 – – Years

– – 0.2 mA Driving internal pull-down resistor.

– – 1.5 mA Driving internal pull-down resistor.

1,800,000 – – – Erase/write cycles.

November 12, 2004 Document No. 38-12013 Rev. *G 26

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.4 AC Electrical Characteristics

3.4.1 AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Note See the individual user module data sheets for information on maximum frequencies for user modules. Table 3-16: AC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

IMO24

IMO6

CPU1

CPU2

48M

24M

32K1

32K2

PLL

Jitter24M2 24 MHz Period Jitter (PLL) – – 600 ps T

PLLSLEW

PLLSLEWLOW

OSACC

Jitter32k 32 kHz Period Jit te r – 100 ns T

XRST

DC24M 24 MHz Duty Cycle 40 50 60 % Step24M 24 MHz Trim Step Size – 50 – kHz Fout48M 48 MHz Output Frequency 46.8 48.0

Jitter24M1 24 MHz Period Jitter (IMO) – 600 ps F

MAX

RAMP

a. 4.75V < Vdd < 5.25V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on tr im mi n g fo r op er a t i on at 3.3 V. d. See the individual user module data sheets for information on maximum frequencies for user modules.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Internal Main Oscillator Frequency for 24 MHz 23.4 24

Internal Main Oscillator Frequency for 6 MHz 5.75 6

CPU Frequency (5V Nominal) 0.93 24 CPU Frequency (3.3V Nominal) 0.93 12 Digital PSoC Block Frequency 0 48

Digital PSoC Block Frequency 0 24

24.6

6.35

24.6

12.3

49.2

24.6

a,b,c

MHz Trimmed for 5V or 3.3 V operation us i ng

a,b,c

MHz Trimmed for 5V or 3.3 V operation us i ng

a,b

MHz

b,c

MHz

a,b,d

MHz Refer to the AC Digital Block Specifica-

b, d

MHz

factory trim values. See Figure 3-1b on

page 17. SLI MO Mo de = 0.

factory trim values. See Figure 3-1b on

page 17. SLI MO Mo de = 1.

tions below.

Internal Low Sp ee d Oscillator Frequency 15 32 64 kHz External Crystal Oscillator – 32.768 – kHz

Accuracy is capacitor and crystal dependent. 50% duty cycle.

PLL Frequency – 23.986 – MHz

PLL Lock Time 0.5 – 10 ms PLL Lock Time for Low Gain Setting 0.5 – 50 ms External Crystal Oscillator Startup to 1% – 250 500 ms External Crystal Oscillator Startup to 100 ppm – 300 600 ms The crystal oscillator frequency is within 100 ppm

External Reset Pulse Width 10 – – µs

a,c

49.2

MHz Trimmed. Utilizing f act ory trim values.

Maximum frequency of signal on row input or row output. – – 12.3 MHz Supply Ramp Time 0 – – µs

A multiple (x732) of crystal frequency.

of its final val ue by the end of the T Correct operat ion assu mes a pr operl y loade d 1 uW

maximum drive level 32.768 kHz crystal . 3.0V ≤ Vdd ≤ 5.5V, -40

C ≤ TA ≤ 85 oC.

osacc

period.

November 12, 2004 Document No. 38-12013 Rev. *G 27

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

PLL

Enable

PLLSLEW

PLL

24 MHz

PLL

Gain

Figure 3-3. PLL Lock Timing Diagram

PLL

Enable

PLLSLEWLOW

PLL

Gain

Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram

32K

Select

32K2

24 MHz

32 kHz

Figure 3-5. External Crystal Oscillator Startup Timing Diagram

Jitter24M1

24M

Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter32k

32K2

Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram

November 12, 2004 Document No. 38-12013 Rev. *G 28

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.4.2 AC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-17: AC GPIO Specifications

Symbol Description Min Typ Max Units Notes

GPIO

TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.75 to 5.25V, 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.75 to 5.25V, 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%

90%

GPIO

Output

Voltage

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

GPIO Operating Frequency 0 – 12.3 MHz Normal Strong Mode

10%

TRiseF TRiseS

Figure 3-8. GPIO Timing Diagram

TFallF

TFallS

November 12, 2004 Document No. 38-12013 Rev. *G 29

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.4.3 AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only. Settling times, slew rates, and gain bandw idth are based on the Analog Continuous Time PSoC block.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Power = High and Opamp Bias = High is not supported at 3.3V.

Table 3-18: 5V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

ROA

SOA

ROA

FOA

NOA

Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time to 0.1% for a 1V Step (10 pF loa d ,

Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load,

Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load,

Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Med i um, Opamp Bias = High) – 100 – nV/rt-Hz

– – –

0.15

1.7

6.5

0.01

0.5

4.0

0.75

3.1

5.4

– – –

3.9

0.72

0.62

5.9

0.92

0.72

– – –

µs

MHz

µs µs µs

Table 3-19: 3.3V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

ROA

SOA

ROA

FOA

NOA

Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Settling Time to 0.1% of a 1V Step (10 pF lo ad ,

Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load,

Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load,

Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Med i um, Opamp Bias = High) – 100 – nV/rt-Hz

– –

0.31

2.7

0.24

1.8

0.67

2.8

– –

3.92

0.72

5.41

0.72

– –

µs

MHz

µs µs

November 12, 2004 Document No. 38-12013 Rev. *G 30

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

dBV/rtHz 10000

0.01

0.1

1.0 10

1000

100

0.001 0.01 0.1 1 10 100Freq (kHz)

Figure 3-9. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proporti ona l to 1/f, p ower in de pen dent, and determined by de vic e g eometry. At high frequencies, increased power level reduces the noise spectrum level.

nV/rtHz 10000

PH_BH PH_BL PM_BL PL_BL

1000

100

0.001 0.01 0.1 1 10 100

Freq (kHz)

Figure 3-10. Typical Opamp Noise

November 12, 2004 Document No. 38-12013 Rev. *G 31

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.4.4 AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-20: AC Digital Block Specifications

Function Description Min Typ Max Units Notes

All Functions

Timer Captu re Pu l se Width

Counter Enable Pulse Width

Dead Band Kill Pulse Width:

CRCPRS (PRS Mode)

CRCPRS (CRC Mode)

SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2 x over

SPIS Maximum Input Clock Frequency – – 4.1 ns

Transmitter Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over

Receiver Maximum Input Clock Fr eq uency – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Maximum Block Clocking Frequency (> 4.75V) 49.2 4.75V < Vdd < 5.25V. Maximum Block Clocking Frequency (< 4.75V) 24.6 3.0V < Vdd < 4.75V.

50 Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V . Maximum Frequency, With Capture – – 24.6 MHz

50 Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V. Maximum Frequency, Enable Input – – 24.6 MHz

Asynchronous Restart Mode 20 – – ns Synchronous Restart Mode

Disable Mode

Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V. Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.

Maximum Input Clock Frequency – – 24.6 MHz

Width of SS_ Negated Between Transmissions

– – ns

clocking.

November 12, 2004 Document No. 38-12013 Rev. *G 32

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.4.5 AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-21: 5V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

ROB

SOB

ROB

FOB

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

Power = Low Power = High

–

0.5

0.55

0.8

300

– –

4 4

3.4

– –

µs µs

V/µs V/

MHz MHz

kHz kHz

µs

Table 3-22: 3.3V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

ROB

SOB

ROB

Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

FOB

Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

Power = Low Power = High

–

.36

0.7

200

– –

4.7

4 4

– –

µs µs

V/µs V/

MHz MHz

kHz kHz

µs

November 12, 2004 Document No. 38-12013 Rev. *G 33

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.4.6 AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-23: 5V AC External Clo ck Specific ations

Symbol Description Min Typ Max Units Notes

OSCEXT

– High Period 20.6 – Low Period 20.6 – Power Up IMO to Switch 150

Table 3-24: 3.3V AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

OSCEXT

– High Period with CPU Clock divide by 1 41.7 – Low Period with CPU Clock divide by 1 4 1. 7 – Power Up IMO to Switch 150

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Frequency 0.093 –24.6MHz

– 5300 ns – –ns – – µs

Frequency with CPU Clock divide by 1 0.093 – 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3V.

Frequency with CPU Clock divide by 2 or greater 0.186 – 24.6 MHz If the frequency of the external clock is

– 5300 ns – –ns – – µs

With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure tha t th e fifty percent duty cycle requirement is met.

3.4.7 AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-25: AC Programming Specifications

Symbol Description Min Typ Max Units Notes

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

ERASEB

WRITE

DSCLK

DSCLK3

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Rise Time of SCLK 1 – 20 ns Fall Time of SCLK 1 – 20 ns Data Set up Time to Falling Edge of SCLK 40 – – ns Data Hold T ime fro m Falling Edge of SCLK 40 – – ns Frequency of SCLK 0 – 8 MHz Flash Erase Time (Block) – 10 – ms Flash Block Write Time – 10 – ms Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6

November 12, 2004 Document No. 38-12013 Rev. *G 34

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CY8C29x66 Final Data Sheet 3. Electrical Specifications

3.4.8 AC I2C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-26: AC Characteristics of the I

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

SPI2C

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

C SDA and SCL Pins

Standard Mode Fast Mode

Units NotesMin Max Min Max

SCL Clock Frequency 0 100 0 400 kHz Hold Time (repeated) START Condition. After this

period, the first clock pulse is gene rated. LOW Period of the SCL Clock 4.7 –1.3– µs

HIGH Period of the SCL Clock 4.0 –0.6– µs Set-up Time for a Repeated START Condition 4.7 –0.6– µs Data Hold Time 0 –0– µs Data Set-up Time 250 – Set-up Time for STOP Condition 4.0 –0.6– µs Bus Free Time Between a STOP and START Condition 4.7 –1.3– µs Pulse Width of spikes are suppressed by the input fil-

ter.

+ t

rmax

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SU;DAT

4.0 –0.6– µs

100

– – 0 50 ns

–ns

≥ 250 ns must then be met. This will automatically be

SU;DAT

SD A

LOWI2C

SUDATI2C

HDSTAI2C

SPI2C

BUFI2C

SCL

HDSTAI2C

HDDATI2C

HIGHI2C

SUSTAI2C

Sr SP

Figure 3-11. Definition for Timing for Fast/Standard Mode on the I

SUSTOI2C

C Bus

November 12, 2004 Document No. 38-12013 Rev. *G 35

Page 36

4. Packaging Information

This chapter illustrates the packaging specifications for the CY8C29x66 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emul ator Pod Dime ns ion s at

http://www.cypress.com/support/link.cfm?mr=poddim.

4.1 P ackaging Dimensi ons

51-85014 - *D

Figure 4-1. 28-Lead (300-Mil) Molded DIP

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CY8C29x66 Final Data Sheet 4. Packaging Information

51-85079 - *C

Figure 4-2. 28-Lead (210-Mil) SSOP

51-85026 - *C

Figure 4-3. 28-Lead (300-Mil) SOIC

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CY8C29x66 Final Data Sheet 4. Packaging Information

Figure 4-4. 44-Lead TQFP

51-85064 - *B

51-85061 - *C

51-85061-

Figure 4-5. 48-Lead (300-Mil) SSOP

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CY8C29x66 Final Data Sheet 4. Packaging Information

Figure 4-6. 48-Lead (7x7 mm) MLF

51-85152-*B

51-85161 - **

Figure 4-7. 100-Lead TQFP

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CY8C29x66 Final Data Sheet 4. Packaging Information

4.2 Thermal Impedances

Table 4-1. Thermal Impedances per Package

Package Typical θ

28 PDIP

28 SSOP

28 SOIC 44 TQFP 48 SSOP

48 MLF

100 TQFP

* TJ = TA + POWER x θ

69 oC/W 94 oC/W 67 oC/W 60 oC/W 69 oC/W 28 oC/W 50 oC/W

4.3 Capacitance on Cryst al Pins

Table 4-2: Typical Package Capacitance on Crystal Pins

Package Package Capacitance

28 PDIP 3.5 pF 28 SSOP 2.8 pF

28 SOIC 2.7 pF 44 TQFP 2.6 pF 48 SSOP 3.3 pF

48 MLF 1.8 pF

100 TQFP 3.1 pF

4.4 Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 4-3. Solder Reflow Peak Temperature

Package Minimum Peak Temperature* Maximum Peak Temperature

28 PDIP 28 SSOP

28 SOIC 44 TQFP 48 SSOP

48 MLF

100 TQFP

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC with Sn-Pb or 245+/-5

C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

220oC 260oC 240oC 260oC 220oC 260oC 220oC 260oC 220oC 260oC 220oC 260oC 220oC 260oC

November 12, 2004 Document No. 38-12013 Rev. *G 40

Page 41

5. Ordering Information

The following table lists the CY8C29x66 PSoC device’s key package features and ordering codes.

Table 5-1. CY8C29x66 PSoC Device Key Features and Ordering Information

Package

28 Pin (300 Mil) DIP CY8C29466-24PXI 32K 2K Yes -40C to +85C 16 12 24 12 4 Yes 28 Pin (210 Mil) SSOP CY8C29466-24PV XI 32K 2K Yes -40C to +85C 16 12 24 12 4 Yes 28 Pin (210 Mil) SSOP (T ape and Reel) 28 Pin (300 Mil) SOIC CY8C29466-24SXI 32K 2K Yes -40C to +85C 16 12 24 12 4 Yes 28 Pin (300 Mil) SOIC (T ape and Reel) 44 Pin TQFP CY8C29566-24AXI 32K 2K Yes -40C to +85C 16 12 40 12 4 Yes 44 Pin TQFP (T ape and Reel) 48 Pin (300 Mil) SSOP CY8C29666-24PV XI 32K 2K Yes -40C to +85C 16 12 44 12 4 Yes 48 Pin (300 Mil) SSOP (T ape and Reel) 48 Pin MLF CY8C29666-24LFXI 32K 2K Yes -40C to +85C 16 12 44 12 4 Yes 100 Pin TQFP CY8C29866-24AXI 32K 2K Yes -40C to +85C 16 12 64 12 4 Yes

CY8C29466-24PVXIT 32K 2K Yes -40C to +85C 16 12 24 12 4 Yes

CY8C29466-24SXIT 32K 2K Yes -40C to +85C 16 12 24 12 4 Yes

CY8C29566-24AXIT 32K 2K Yes -40C to +85C 16 12 40 12 4 Yes

CY8C29666-24PVXIT 32K 2K Yes -40C to +85C 16 12 44 12 4 Yes

Ordering

Code

Flash

(Bytes)

RAM

(Bytes)

Switch Mode

Pump

Range

Temperature

Blocks

Digital PSoC

Blocks

Analog PSoC

Digital IO

Pins

Inputs

Analog

Outputs

5.1 Ordering Code Definitions

Y 8 C 29 xxx-SPxx

Package Type: Thermal Rating:

PX = PDIP Pb-Fre e C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX = MLF Pb-Free

AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress

XRES Pin

November 12, 2004 Document No. 38-12013 Rev. *G 41

Page 42

6. Sales and Service Information

To obtain informa tion ab out Cypress Micro System s or PSoC sa les an d techn ical supp ort, reference the fol lowing i nforma tion or go to the section titled “Getting Started” on page 4 in this document.

Cypress Mi croSystem s

2700 162nd Street SW Building D Lynnwood, WA 98037 Phone: 800.669.0557 Facsimile: 425.787.4641

Web Sites: Company Information – http://www.cypress.com

Sales – http://www.cypress.com/aboutus/sales_locations.cfm

Technical Support – http://www.cypress.com/support/login.cfm

6.1 Revision History

Table 6-1. CY8C29X66 Data Sheet Revision History

Document Title: CY8C29466, CY8C29566, CY8C29666, and CY8C29866 PSoC Mixed-Signal Array Final Data Sheet Document Number: 38-120 13

Revision ECN # Issue Date Origin of Change Description of Change

** 131151 11/13/2003 New Silicon New document (Revision **). *A 132848 01/21/2004 NWJ New information. First edition of preliminary data sheet. *B 133205 01/27/2004 NWJ Changed part numbers, increased SRAM data storage to 2K bytes. *C 133656 02/09/2004 SFV Changed part numbers and removed a 28-pin SOIC. *D 227240 06/01/2004 SFV Changes to Overview section, 48-pin MLF pinout, and significant changes to the Electrical Specs. *E 240108 See ECN SFV Added a 28-lead (300 mil) SOIC part. *F 247492 See ECN SFV New information added to the Elec tri c a l Specifications chapter. *G 288849 See ECN HMT Add DS standards, update device table, fine-tune pinouts, add Reflow Peak Temp. table. Finalize.

Distribution: Extern al/Publ ic Posting: None

6.2 Co pyri ghts and Code Protection

Copyrights

© Cypress MicroSystems, Inc. 2003 – 2004. All rights reserved. PSoC™, PSoC Designer™, and Programmable System-on-Chip™ are trademarks of Cypress Micr oSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than cir cuitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does n o t au tho riz e it s prod u ct s for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems products in life- support systems application impl ies that the manufacturer assumes all ri sk of such use and in doing so indemnifies Cypress MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pu rsuant to an e xpress writte n agreement with Cypress M icroSystems.

Flash Code Protection

Note the following details of the Flash code protection features on Cypress MicroSystems devices. Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of

products is one of the most secure families of it s kind on the market today, regardless of how they are used. There may be met hods, unknown to Cypress MicroSystems, that can breach the c ode protect ion feat ures. An y of these meth ods, to ou r knowled ge, would b e dishone st and possi bly ill egal. Nei ther Cypress Micr oSystems nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress MicroSystems are committed to continuously improving the code protection features of our products.

Page 43

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

Datasheet CY8C29466, CY8C29566, CY8C29666, CY8C29866 Datasheet (CYPRESS)

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

PSoC™ Functional Overview

Getting Started

Development Tools

Designing with User Modules

Document Conventions

1. Pin Information

1.1 Pinouts

1.1.1 28-Pin Part Pinout

1.1.2 44-Pin Part Pinout

1.1.3 48-Pin Part Pinouts

1.1.4 100-Pin Part Pinout

2. Register Reference

2.1 Register Conventions

2.1.1 Abbreviations Used

2.2 Register Mapping Tables

3. Electrical S pecifications

3.1 Absolute Maximum Ratings

3.2 Operating Temperature

3.3 DC Electrical Characteristics

3.3.1 DC Chip-Level Specifications

3.3.2 DC General Purpose IO Specifications

3.3.3 DC Operational Ampli fier Specifications

3.3.4 DC Analog Output Buffer Specifications

3.3.5 DC Switch Mode Pump Specifications

3.3.6 DC Analog Reference Specifications

3.3.7 DC Analog PSoC Block Specifications

3.3.8 DC POR, SMP, and LVD Specifications

3.3.9 DC Programming Specifications

3.4 AC Electrical Characteristics

3.4.1 AC Chip-Level Specifications

3.4.2 AC General Purpose IO Specifications

3.4.3 AC Operational Amplifier Specifications

3.4.4 AC Digital Block Specifications

3.4.5 AC Analog Output Buffer Specifications

3.4.6 AC External Clock Specifications

3.4.7 AC Programming Specifications

3.4.8 AC I2C Specifications

4. Packaging Information

4.1 P ackaging Dimensi ons

4.2 Thermal Impedances

4.3 Capacitance on Cryst al Pins

4.4 Solder Reflow Peak Temperature

5. Ordering Information

5.1 Ordering Code Definitions

6. Sales and Service Information

6.1 Revision History

6.2 Co pyri ghts and Code Protection