Datasheet CY8C24794 Datasheet (CYPRESS)

Download

Page 1

PSoC® Mixed-Signal Array Final Data Sheet

CY8C24094, CY8C24794, CY8C24894, and CY8C24994

Features

■ CY8C24894 includes an XRES pin to support In-System Serial Programming (ISSP) and external reset control

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds to 24 MHz ❐ Two 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0 to 5.25V Operating Voltage ❐ Industrial Temperature Range: -40°C to +85°C ❐ USB Temperature Range: -10°C to +85°C

■ Advanced Peripherals (PSoC Blocks)

❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:

- Up to 14-Bit ADCs

- Up to 9-Bit DACs

- Programmable Gain Amplifiers

- Programmable Filters and Comparators

❐ 4 Digital PSoC Blocks Provide:

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Full-Duplex UART

- Multiple SPI™ Masters or Slaves

- Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks ❐ Capacitive Sensing Application Capability

■ Full-Speed USB (12 Mbps)

❐ Four Uni-Directional Endpoints ❐ One Bi-Directional Control Endpoint ❐ USB 2.0 Compliant ❐ Dedicated 256 Byte Buffer ❐ No External Crystal Required

■ Flexible On-Chip Memory

❐ 16K Flash Program Storage 50,000 Erase/

Write Cycles

❐ 1K SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations

❐ 25 mA Sink on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open

Drain Drive Modes on all GPIO

❐ Up to 48 Analog Inputs on GPIO ❐ Two 33 mA Analog Outputs on GPIO ❐ Configurable Interrupt on all GPIO

■ Precision, Programmable Clocking

❐ Internal ±4% 24/48 MHz Oscillator ❐ Internal Oscillator for Watchdog and Sleep ❐ .25% Accuracy for USB with no External

Components

■ Additional System Resources

❐ I

C™ Slave, Master, and Multi-Master to

400 kHz

❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference

■ Complete Development Tools

❐ Free Development Software

(PSoC Designer™)

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Bytes Trace Memory

Port 7

s u B

m e

Global Digital Interconnect

SRAM

Interrupt

Controller

DIGITAL SYSTEM

Digital

Block

Array

Digital

MACs

Decimator

Type 2

Clocks

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

Global Analog Interconnect

PSoC CORE

SROM Flash 16K

CPU Core (M8C)

Clock Sources

(Includes IMO and ILO)

Sleep and Watchdog

ANALOG SYSTEM

Analog

Block

Array

POR and LVD

I2C USB

System Resets

Internal Voltage

Ref.

SYSTEM RESOURCES

Ref.

Analog Drivers

Analog

Input

Muxing

PSoC® Functional Overview

The PSoC® family consists of many Mixed-Signal Array with On-Chip Controller devices. All PSoC family devices are

designed to replace traditional MCUs, system ICs, and the numerous discrete components that surround them. The PSoC CY8C24x94 devices are unique members of the PSoC family because it includes a full-featured, full-speed (12 Mbps) USB port. Configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of industrial, consumer, and communication applications.

This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages.

The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources including a full-speed USB port. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x94 devices can have up to seven IO ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks.

February 15, 2007 © Cypress Semiconductor 2004-2007 — Document No. 38-12018 Rev. *J 1

Page 2

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet PSoC® Overview

The PSoC Core

The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO).

The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with up to 20 vectors, to simplify programming of real time embedded events. Program execution is timed and protected usin g the included Sleep and Watch Dog Timers (WDT).

Memory encompasses 16K of Flash for program storage, 1K of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 8% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. In USB systems, the IMO will self-tune to ± 0.25% accuracy for USB communication.

PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.

The Digital System

The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.

Digital System Block Diagram

Port 2

Port 1

To Analog

System

Port 0

Configuration

Row Output

Port 7

Port 5

i F

Port 3

Port 4

To S ys te m Bu s

DIGITAL SYSTEM

Digital PSoC Block Array

DBB00 DBB01 DCB02 DCB03

Row Input

Configuration

Row 0

Digital peripheral configurations include those listed below.

■ Full-Speed USB (12 Mbps)

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 24 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity

■ SPI master and slave

■ I2C slave and multi-master

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled PSoC Device Characteristics.

The Analog System

The Analog System is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below.

■ Analog-to-digital converters (up to 2, with 6- to 14-bit resolu-

tion, selectable as Incremental, Delta Sigma, and SAR)

■ Filters (2 and 4 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 2, with selectable gain to 48x)

■ Instrumentation amplifiers (1 with selectable gain to 93x)

■ Comparators (up to 2, with 16 selectable thresholds)

■ DACs (up to 2, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)

■ High current output drivers (two with 30 mA drive as a PSoC

Core Resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak Detectors

■ Many other topologi e s po ssi bl e

GIE[7:0]

GIO[7:0]

Global Digital Interconnect

GOE[7:0]

GOO[7:0]

February 15, 2007 Document No. 38-12018 Rev. *J 2

Page 3

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet PSoC® Overview

Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below.

Analog System Block Diagram

All IO

(Except Port 7)

P0[7]

P0[5]

P0[3] P0[1]

P2[3]

P2[1]

Array Input

Configuration

ACI0[1:0]

Analog

Mux Bus

ACI1[1:0]

P0[6]

P0[4]

P0[2] P0[0]

P2[6]

RefIn

P2[4]

AGNDIn

P2[2] P2[0]

The Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin in ports 0-

5. Pins can be connected to the bus individually o r in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. It can be split into two sections for simultaneous dual-channel processing. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array.

Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

■ Track pad, finger sensing.

■ Chip-wide mux that allows analog input from up to 48 IO

pins.

■ Crosspoint connection between any IO pin combinations.

When designing capacitive sensing applications, refer to the latest signal-to-noise signal level re quirements Application Note s, which can be found under http://www.cypress.com >> DESIGN RESOURCES >> Application Notes. In general, and unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) for CapSense applications is 5:1.

Additional System Resources

Block

ACB00 ACB01

Array

RefHi RefLo AGND

ASD11

ASC21

Analog Reference

Reference

Generators

ASC10

ASD20

Interface to

Digital System

M8C Inte rface (Addre ss Bus, Data Bus, Etc.)

AGNDIn RefIn Bandgap

System Resources, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow.

■ Full-S peed USB (12 Mbps) with 5 configurable endpoints and

256 bytes of RAM. No external components required except two series resistors. Wider than commercial temperature USB operation (-10°C to +85°C).

■ Digital clock dividers provide three customizable clock fre-

quencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers.

■ Two multiply accumulates (MACs) provide fast 8-bit multipli-

ers with 32-bit accumulate, to assist in both general math as well as digital filters.

■ Decimator provides a custom hardware filter for digital signal

processing apps. including creation of Delta Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication

over two wires. Slave, master, multi-master are supported.

■ Low V oltage Detection (L VD) interrupt s signal the application

of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ Versatile analog multiplexer system.

February 15, 2007 Document No. 38-12018 Rev. *J 3

Page 4

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet PSoC® Overview

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this data sheet is shown in the highlighted row of the table

PSoC Device Characteristics

PSoC Part

Number

CY8C29x66

CY8C27x43

CY8C24x94 56 1 4 48 2 2 6 1K 16K

CY8C24x23A

CY8C21x34

CY8C21x23

CY8C20x34

a. Limited analog functionality. b. Two analog blocks and one CapSense.

Digital IODigital

up to

28 16 1 4 8 0 2

up to

Rows

4 16 12 4 4 12 2K 32K

28124412

1412226

142802

0 0 28 0 0

Inputs

Digital

Blocks

Analog

Columns

Analog

Outputs

Size

Flash

SRAM

Blocks

256

16K

Bytes

256

Bytes

512

Bytes

256

Bytes

512

Bytes

Getting Started

The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual.

For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on

Size

the web at http://www.cypress.com/psoc. To determine which PSoC device meets your requirements,

navigate through the PSoC Decision Tree in the Application Note AN2209 at http://www.cypress.com and select Application Notes under the Design Resources.

Development Kits

Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at

http://www.cypress.com, click the Online Store shopping cart

icon at the bottom of the web page, and click PSoC (Program- mable System-on-Chip) to view a current list of available items.

Technical Training Modules

Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http://

www.cypress.com/techtrain.

Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. T o contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants.

Technical Support

PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.

Application Notes

A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are listed by date as default.

February 15, 2007 Document No. 38-12018 Rev. *J 4

Page 5

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet PSoC® Overview

Development Tools

PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)

PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides de sign database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs.

PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.

PSoC Designer Subsystems

PSoC

Designer

Importable

Design

Database

Device

Database

Application

Database

Project

Database

User

Modules

Library

Emulation

Pod

Graphical Designer

Interface

Results

Commands

PSoC

Designer

Core

Engine

In-Circuit Emulator

Context

Sensitive

Help

PSoC

Configuration

Sheet

Manufacturing

Information

File

Device

Programmer

February 15, 2007 Document No. 38-12018 Rev. *J 5

Page 6

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet PSoC® Overview

PSoC Designer Software Subsystems

Device Editor

The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.

PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can pri nt out a con figuration sh eet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It’s also possible to change the selected components and regenerate the framework.

Design Browser

The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader.

Application Editor

In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build.

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compiler. A C language compiler is available that supports the PSoC family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices.

The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

February 15, 2007 Document No. 38-12018 Rev. *J 6

Page 7

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet PSoC® Overview

Designing with User Modules

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements.

To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed.

The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module.

The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.

User Module/Source Code Development Flows

Device Editor

User

Module

Selection

Placement

and

Parameter

-ization

Source

Code

Generator

Generate Application

Appli cati on Editor

Project

Manager

Source

Code

Editor

Build

Manager

Build All

Debugger

Interface

to IC E

Storage

Inspector

Event &

Breakpoint

Manager

The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and as sembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming.

The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger d ownloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.

February 15, 2007 Document No. 38-12018 Rev. *J 7

Page 8

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet PSoC® Overview

Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this document.

Acronym Description

AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-to-analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory FSR full scale range GPIO general purpose IO GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoC® Programmable Syste m-on-Chip™ PWM pulse width modulator SC switched capacitor SRAM static random access memory

Units of Measure

A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 22 lists all the abbreviations used to measure the PSoC devices.

Numeric Naming

Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.

Table of Contents

For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Refer- ence Manual. This document encompasses and is organized into the following chapters and sections.

Pin Information ........................................................................................ 9

1.1 56-Pin Part Pinout ......................................................................... 9

1.2 56-Pin Part Pinout (with XRES) .................................................. 10

1.3 68-Pin Part Pinout ........................................................................ 11

1.4 68-Pin Part Pinout (On-Chip Debug) ...........................................12

1.5 100-Ball VFBGA Part Pinout ........................................................ 13

1.6 100-Ball VFBGA Part Pinout (On-Chip Debug) ...........................15

1.7 100-Pin Part Pinout (On-Chip Debug) ..........................................17

2. Register Refe r ence ............................... ... ... ............................... ... .. ... .... 19

2.1 Register Conventions ................................................................... 19

2.1.1 Abbreviations Used ....................................................... 19

2.2 Register Mapping Tables .............................................................19

3. Electrical Specifications ............ ........................................................... 22

3.1 Absolute Maximum Ratings ......................................................... 23

3.2 Operating Temperature ................................................................ 23

3.3 DC Electrical Characteristics ........................................................ 23

3.3.1 DC Chip-Level Specifications ........................................ 23

3.3.2 DC General Purpose IO Specifications ......................... 24

3.3.3 DC Full-Speed USB Specifications ............................... 24

3.3.4 DC Operational Amplifier Specifications ....................... 25

3.3.5 DC Low Power Comparator Specifications ................... 26

3.3.6 DC Analog Output Buffer Specifications ....................... 27

3.3.7 DC Analog Reference Specifications ............................ 28

3.3.8 DC Analog PSoC Block Specifications .......................... 29

3.3.9 DC POR and LVD Specifications .................................. 29

3.3.10 DC Programming Specifications ................................... 30

3.4 AC Electrical Characteristics ............................................ ... ......... 31

3.4.1 AC Chip-Level Specifications .. .. ... ................................. 31

3.4.2 AC General Purpose IO Specifications ......................... 32

3.4.3 AC Full-Speed USB Specifications ............................... 32

3.4.4 AC Operational Amplifier Specifications ........................ 33

3.4.5 AC Low Power Comparator Specifications .... ... ............ 35

3.4.6 AC Digital Block Specifications ..................................... 35

3.4.7 AC External Clock Specifications .................................. 35

3.4.8 AC Analog Output Buffer Specification s ........................ 36

3.4.9 AC Programming Specifications .............. .. .................... 37

3.4.10 AC I2 C Specifications ................... ... .. ... ......................... 38

4. Packaging Information .......................................................................... 39

4.1 Packaging Dimensions ... ... .................................. ... .. .................... 39

4.2 Thermal Impedance ................................................................... ..42

4.3 Solder Reflow Peak Temperatu r e .................... ... ......................... 42

5. Development Tool Selection ................................................................ 43

5.1 Software ............ ....................................... .................................... 43

5.1.1 PSoC Designer .............................................................. 43

5.1.2 PSoC Express ............................................................... 43

5.1.3 PSoC Programmer ........................................................ 43

5.1.4 CY3202-C iMAGEcraft C Compiler .............. .. ... ............ 43

5.2 Development Kits ......................................................................... 43

5.2.1 CY3215-DK Basic Development Kit .............................. 43

5.2.2 CY3210-ExpressDK Development Kit ........................... 44

5.3 Evaluation Tools ..... ... ... .................................. .. ............................ 4 4

5.3.1 CY3210-MiniProg1 ............... ........................................ . 44

5.3.2 CY3210-PSoCEval1 ........... ..................... ...................... 44

5.3.3 CY3214-PSoCEvalUSB ................................................ 44

5.4 Device Programmers .................. ... ... ........................................... 44

5.4.1 CY3216 Modular Programmer ...................................... 44

5.4.2 CY3207ISSP In-System Serial Programmer (ISSP) ..... 44

5.5 Accessories (Emulation and Progra mming) ........ ......................... 45

5.6 3rd-Party Tools ..... .. .................................. ... ... .............................. 45

5.7 Build a PSoC Emulator into Your Board ...................................... 45

6. Ordering Infor ma t ion ........................... ... .................................. ... .. ....... 46

6.1 Ordering Code Definitions ............................................................ 46

7. Sales and Compan y Inf o r ma t ion ........................ ................................. 47

7.1 Revision History ........................................................................... 47

7.2 Copyrights and Code Protection ..................................................48

February 15, 2007 Document No. 38-12018 Rev. *J 8

Page 9

1. Pin Information

This chapter describes, lists, and illustrates the CY8C24x94 PSoC device family pin s and pinout configuration. The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin

(labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.

1.1 56-Pin Part Pinout

Table 1-1. 56-Pin Part Pinout (QFN**) See LEGEND details and footnotes in Table 1-2 on page 10.

Pin No.

1 IO I, M P2[3] Direct switched capacitor block input. 2 IO I, M P2[1] Direct switched capacitor block input. 3 IO M P4[7] 4 IO M P4[5] 5 IO M P4[3] 6 IO M P4[1] 7 IO M P3[7] 8 IO M P3[5]

9 IO M P3[3] 10 IO M P3[1] 11 IO M P5[7] 12 IO M P5[5] 13 IO M P5[3] 14 IO M P5[1] 15 IO M P1[7] I2C Serial Clock (SCL). 16 IO M P1[5] I2C Serial Data (SDA). 17 IO M P1[3] 18 IO M P1[1] I2C Serial Clock (SCL), ISSP SCLK*. 19 Power Vss Ground connection. 20 USB D+ 21 USB D22 Power Vdd Supply voltage. 23 IO P7[7] 24 IO P7[0] 25 IO M P1[0] I2C Serial Data (SDA), ISSP SDATA*. 26 IO M P1[2] 27 IO M P1[4] 28 IO M P1[6] 29 IO M P5[0] 30 IO M P5[2] Digital Analog 31 IO M P5[4] 44 IO M P2[6] External Voltage Reference (VREF) input. 32 IO M P5[6] 45 IO I, M P0[0] Analog column mux input. 33 IO M P3[0] 46 IO I, M P0[2] Analog column mux input. 34 IO M P3[2] 47 IO I, M P0[4] Analog column mux input VREF. 35 IO M P3[4] 48 IO I, M P0[6] Analog column mux input. 36 IO M P3[6] 49 Power Vdd Supply voltage. 37 IO M P4[0] 50 Power Vss Ground connection. 38 IO M P4[2] 51 IO I, M P0[7] Analog column mux input,. 39 IO M P4[4] 52 IO IO , M P0[5] Analog column mux input and column output. 40 IO M P4[6] 53 IO IO , M P0[3] Analog column mux input and column output. 41 IO I, M P2[0] Direct switched capacitor block input. 54 IO I, M P0[1] Analog column mux input. 42 IO I, M P2[2] Direct switched capacitor block input. 55 IO M P2[7] 43 IO M P2[4] External Analog Ground (AGND) input. 56 IO M P2[5]

Type

Digital Analog

Name Description

Pin No.

A, I, M, P2[3] A, I, M, P2[1]

M, P4[7] M, P4[5] M, P4[3] M, P4[1] M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, P5[3] M, P5[1]

Type

CY8C24794 56-Pin PSoC Device

P2[6], M

P0[0], A, I, M

P0[2], A, I, M

P0[4], A, I, M

P0[6], A, I, M

Vdd

Vss

P0[7], A, I, M

P0[5], A, IO, M

P0[3], A, IO, M

P0[1], A, I, M

P2[7], M

P2[5], M

1 2 3 4 5 6 7 8 9 10 11 12 13 14

15161718192021

M, P1[3]

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, I2C SCL, P1[1]

QFN

(Top View )

D-

D+

Vdd

Vss

Name Description

2324252627

P7[7]

P7[0]

M, P1[2]

M, I2C SDA, P1[0]

M, P1[4]

P2[4], M

41 40

39 38 37 36

34 33 32 31 30 29

M, P1[6]

P2[2], A, I, M P2[0], A, I, M P4[6], M P4[4], M P4[2], M P4[0], M P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M

February 15, 2007 Document No. 38-12018 Rev. *J 9

Page 10

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 1. Pin Information

1.2 56-Pin Part Pinout (with XRES)

Table 1-2. 56-Pin Part Pinout (QFN**)

Pin No.

1 IO I, M P2[3] Direct switched capacitor block input.

2 IO I, M P2[1] Direct switched capacitor block input.

3 IO M P4[7]

4 IO M P4[5]

5 IO M P4[3]

6 IO M P4[1]

7 IO M P3[7]

8 IO M P3[5]

Type

Digital Analog

Name Description

A, I, M, P2[3] A, I, M, P2[1]

M, P 4[7 ] M, P 4[5 ] M, P 4[3 ] M, P 4[1 ] M, P 3[7 ]

M, P 3[5 ] M, P 3[3 ] M, P 3[1 ]

M, P 5[7 ] M, P 5[5 ] M, P 5[3 ] M, P 5[1 ]

CY8C24894 56-Pin PSoC Device

P0[0 ], A, I, M

P0[2 ], A, I, M

P0[4 ], A, I, M

P0[6 ], A, I, M

Vdd

Vss

P0[7 ], A, I, M

P0[5 ], A, IO, M

P0[3 ], A, IO, M

P0[1 ], A, I, M

P2[7 ], M

P2[5 ], M

1 2 3 4 5 6 7 8 9 10 11 12 13 14

15161718192021

M, P1[3]

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

QFN

(Top View)

D+

Vss

M, I2C SCL, P1[1]

D-

Vdd

2324252627

P7[7]

P7[0]

M, P1[2]

M, I2C SDA, P1[0]

M, P1[4]

P2[6 ], M

P2[4 ], M

M, P1[6]

42 41

40 39 38 37

36 35

32 31 30 29

P2[2 ], A, I, M P2[0 ], A, I, M P4[6 ], M P4[4 ], M P4[2 ], M P4[0 ], M XRES P3[4 ], M P3[2 ], M P3[0 ], M P5[6 ], M P5[4 ], M P5[2 ], M P5[0 ], M

29 IO M P5[0] 30 IO M P5[2] Digital Analog

Pin No.

Type

Name Description

31 IO M P5[4] 44 IO M P2[6] External Voltage Reference (VREF) input. 32 IO M P5[6] 45 IO I, M P0[0] Analog column mux input. 33 IO M P3[0] 46 IO I, M P0[2] Analog column mux input. 34 IO M P3[2] 47 IO I, M P0[4] Analog column mux input VREF. 35 IO M P3[4] 48 IO I, M P0[6] Analog column mux input. 36 Input XRES Active high external reset with in ternal

pull down.

49 Power Vdd Supply voltage.

37 IO M P4[0] 50 Power Vss Ground connection. 38 IO M P4[2] 51 IO I, M P0[7] Analog column mux input,. 39 IO M P4[4] 52 IO IO , M P0[5] Analog column mux input and column output. 40 IO M P4[6] 53 IO IO , M P0[3] Analog column mux input and column output. 41 IO I, M P2[0] Direct switched capacitor block input. 54 IO I, M P0[1] Analog column mux input. 42 IO I, M P2[2] Direct switched capacitor block input. 55 IO M P2[7] 43 IO M P2[4] External Analog Ground (AGND) input. 56 IO M P2[5]

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

* These are the ISSP pins, which are not High Z at POR. See the ** The center pad on the QFN package should be connected to groun d (Vss) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

PSoC Mixed-Signal Array Technical Reference Manual for details.

February 15, 2007 Document No. 38-12018 Rev. *J 10

Page 11

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 1. Pin Information

1.3 68-Pin Part Pinout

The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device.

Table 1-3. 68-Pin Part Pinout (QFN**)

Pin No.

1 IO M P4[7]

2 IO M P4[5]

3 IO M P4[3]

4 IO M P4[1]

5 NC No connection.

6 NC No connection.

7 Power Vss Ground connection.

8 IO M P3[7]

9 IO M P3[5] 10 IO M P3[3] 11 IO M P3[1] 12 IO M P5[7] 13 IO M P5[5] 14 IO M P5[3] 15 IO M P5[1] 16 IO M P1[7] I2C Serial Clock (SCL). 17 IO M P1[5] I2C Serial Data (SDA). 18 IO M P1[3] 19 IO M P1[1] I2C Serial Clock (SCL) ISSP SCLK*. 20 Power Vss Ground connection. 21 USB D+ 22 USB D23 Power Vdd Supply voltage. 24 IO P7[7] 25 IO P7[6] 26 IO P7[5] 27 IO P7[4] 28 IO P7[3] 29 IO P7[2] 30 IO P7[1] Digital Analog

31 IO P7[0] 50 IO M P4[6] 32 IO M P1[0] I2C Serial Data (SDA), ISSP SDATA*. 51 IO I,M P2[0] Direct switched capacitor block input. 33 IO M P1[2] 52 IO I,M P2[2] Direct switched capacitor block input. 34 IO M P1[4] Optional External Clock Input (EXT-

35 IO M P1[6] 54 IO M P2[6] External Voltage Reference (VREF) input. 36 IO M P5[0] 55 IO I,M P0[0] Analog column mux input. 37 IO M P5[2] 56 IO I,M P0[2] Analog column mux input and column output. 38 IO M P5[4] 57 IO I,M P0[4] Analog column mux input and column output. 39 IO M P5[6] 58 IO I,M P0[6] Analog column mux input. 40 IO M P3[0] 59 Power Vdd Supply voltage. 41 IO M P3[2] 60 Power Vss Ground connection. 42 IO M P3[4] 61 IO I,M P0[7] Analog column mux input, integration input #1 43 IO M P3[6] 62 IO IO,M P0[5] Analog column mux input and column output, integra-

44 45 46

47 IO M P4[0] 66 IO M P2[5] 48 IO M P4[2] 67 IO I,M P2[3] Direct switched capacitor block input. 49

LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.

* These are the ISSP pins, which are not High Z at POR. See the ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

Type

Digital Analog

Name Description

CLK).

I2C SCL, M, P1[7]

I2C SDA, M, P1[5]

Pin No.

53 IO M P2[4] External Analog Ground (AGND) input.

CY8C24994 68-Pin PSoC Device

P2[1 ], M, AI

P2[3 ], M, AI

P2[5 ], M

P2[7 ], M

P0[1 ], M, AI

P0[3 ], M, AIO

P0[5 ], M, AIO

M, P 4[ 7 ] M, P 4[ 5 ] M, P 4[ 3 ] M, P 4[ 1 ]

M, P 3[ 7 ] M, P 3[ 5 ] M, P 3[ 3 ] M, P 3[ 1 ] M, P 5[ 7 ] M, P 5[ 5 ] M, P 5[ 3 ] M, P 5[ 1 ]

Type

Vss

6867666564636261605958575655545352

1 2 3 4

6 7 8

9 10 11 12 13 14 15 16 17

1819202122232425262728293031323334

M, P1[3]

I2C S CL, M, P1 [1]

Vss

D +

D -

(Top View)

Vdd

P7[7]

Name Description

P0[7 ], M, AI

QFN

P7[6]

P7[5]

Vss

Vdd

P0[6 ], M, AI

P0[4 ], M, AI

P0[2 ], M, AI

P0[0 ], M, AI

P2[6], M, Ext. VREF

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

I2C SDA, M, P1[0]

tion input #2. NC No connection. 63 IO IO,M P0[3] Analog column mux input and column output. NC No connection. 64 IO I,M P0[1] Analog column mux input.

Input XRES Active high pin reset with internal pull

down.

65 IO M P2[7]

IO M P4[4] 68 IO I,M P2[1] Direct switched capacitor block input.

PSoC Mixed-Signal Array Technical Reference Manual for details.

P2[4], M, Ext. AGND

P2[2 ], M, AI

P2[0], M, AI

51 50

P4[6], M P4[4], M

49 48

P4[2], M

P4[0], M

XRES

NC NC

P3[6], M

P3[4], M

P3[2], M

P3[0], M

40 39

P5[6], M

P5[4], M

P5[2], M

P5[0], M

P1[6], M

M, P1[2]

M, P1[4]

February 15, 2007 Document No. 38-12018 Rev. *J 11

Page 12

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 1. Pin Information

1.4 68-Pin Part Pinout (On-Chip Debug)

The 68-pin QFN part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Table 1-4. 68-Pin Part Pinout (QFN**)

Pin No.

1 IO M P4[7] 2 IO M P4[5] 3 IO M P4[3] 4 IO M P4[1] 5 OCDE OCD even data IO. 6 OCDO OCD odd data output. 7 Power Vss Ground connection. 8 IO M P3[7]

9 IO M P3[5] 10 IO M P3[3] 11 IO M P3[1] 12 IO M P5[7] 13 IO M P5[5] 14 IO M P5[3] 15 IO M P5[1] 16 IO M P1[7] I2C Serial Clock (SCL). 17 IO M P1[5] I2C Serial Data (SDA). 18 IO M P1[3] 19 IO M P1[1] I2C Serial Clock (SCL), ISSP SCLK*. 20 Power Vss Ground connection. 21 USB D+ 22 USB D23 Power Vdd Supply voltage. 24 IO P7[7] 25 IO P7[6] 26 IO P7[5] 27 IO P7[4] 28 IO P7[3] 29 IO P7[2] 30 IO P7[1] Digital Analog

44 45 46

47 IO M P4[0] 66 IO M P2[5] 48 IO M P4[2] 67 IO I,M P2[3] Direct switched capacitor block input. 49

LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.

* These are the ISSP pins, which are not High Z at POR. See the ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

Type

Digital Analog

Name Description

I2C SCL, M, P1[7]

I2C SDA, M, P1[5]

Pin No.

CY8C24094 68-Pin OCD PSoC Device

P2[1], M, AI

P2[3], M, AI

P2[5], M

P2[7], M

P0[1], M, AI

P0[3], M, AIO

P0[5], M, AIO

P0[7], M, AI

Vss

Vdd

M, P4[7] M, P4[5] M, P4[3]

M, P4[1]

OCDE

OCDO

Vss

M, P3[7] M, P3[5] M, P3[3]

M, P3[1] M, P5[7] M, P5[5]

M, P5[3] M, P5[1]

Type

6867666564636261605958575655545352

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17

1819202122232425262728293031323334

D +

Vss

M, P1[3]

I2C SCL, M, P1[1]

D -

Vdd

QFN

(Top View)

P7[5]

P7[7]

P7[6]

P7[4]

P7[3]

Name Description

P0[6], M, AI

P0[4], M, AI

P0[2], M, AI

P0[0], M, AI

P2[6], M, Ext. VREF

P7[2]

P7[1]

P7[0]

I2C SDA, M, P1[0]

53 IO M P2[4] External Analog Ground (AGND) input.

CLK).

tion input #2. HCLK OCD high-speed clock outp ut. 63 IO IO,M P0[3] Analog column mux input and column output. CCLK OCD CPU clock output. 64 IO I,M P0[1] Analog column mux input.

Input XRES Active high pin reset with internal pull

down.

65 IO M P2[7]

IO M P4[4] 68 IO I,M P2[1] Direct switched capacitor block input.

PSoC Mixed-Signal Array Technical Reference Manual for details.

P2[4], M, Ext. AGND

P2[2], M, AI

P2[0], M, AI

51 50

P4[6], M P4[4], M

49 48

P4[2], M

P4[0], M

XRES

CCLK HCLK

P3[6], M

P3[4], M

P3[2], M

P3[0], M

40 39

P5[6], M

P5[4], M

P5[2], M P5[0], M

P1[6], M

M, P1[2]

M, P1[4]

February 15, 2007 Document No. 38-12018 Rev. *J 12

Page 13

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 1. Pin Information

1.5 100-Ball VFBGA Part Pinout

The 100-ball VFBGA part is for the CY8C24994 PSoC device.

Table 1-5. 100-Ball Part Pinout (VFBGA)

Pin No.

Digital

A1 Power Vss Ground connection. F1 NC No connection. A2 Power Vss Ground connection. F2 IO M P5[7] A3 NC No connection. F3 IO MP3[5] A4 NC No connection. F4 IO MP5[1] A5 NC No connection. F5 Power Vss Ground connection. A6 Power Vdd Supply voltage. F6 Power Vss Ground connection. A7 NC No connection. F7 IO MP5[0] A8 NC No connection. F8 IO MP3[0] A9 Power Vss Ground connection. F9 XRES Active high pin reset with internal pull down.

A10 Power Vss Ground connection. F10 IO P7[1]

B1 Power Vss Ground connection. G1 NC No connection. B2 Power Vss Ground connection. G2 IO M P5[5] B3 IO I,M P2[1] Direct switched capacitor block input. G3 IO MP3[3] B4 IO I,M P0[1] Analog column mux input. G4 IO M P1[7] I2C Serial Clock (SCL). B5 IO I,M P0[7] Analog column mux input. G5 IO M P1[1] I2C Serial Clock (SCL), ISSP SCLK*. B6 Power Vdd Supply voltage. G6 IO M P1[0] I2C Serial Data (SDA), ISSP SDATA*. B7 IO I,M P0[2] Analog column mux input. G7 IO MP1[6] B8 IO I,M P2[2] Direct switched capacitor block inpu t. G8 IO M P3[4] B9 Power Vss Ground connection. G9 IO M P5[6]

B10 Power Vss Ground connection. G10 IO P7[2]

C1 NC No connection. H1 NC No connection. C2 IO M P4[1] H2 IO MP5[3] C3 IO M P4[7] H3 IO MP3[1] C4 IO M P2[7] H4 IO M P1[5] I2C Serial Data (SDA). C5 IO IO,M P0[5] Analog column mux input and column output. H5 IO M P1[3] C6 IO I,M P0[6] Analog column mux input. H6 IO M P1[2] C7 IO I,M P0[0] Analog column mux input. H7 IO MP1[4] C8 IO I,M P2[0] Direct switched capacitor block input. H8 IO MP3[2] C9 IO M P4[2] H9 IO M P5[4]

C10 NC No connection. H10 IO P7[3]

D1 NC No connection. J1 Power Vss Ground connection. D2 IO M P3[7] J2 Power Vss Ground connection. D3 IO M P4[5] J3 USB D+ D4 IO M P2[5] J4 USB DD5 IO IO,M P0[3] Analog column mux input and column output. J5 Power Vdd Supply voltage. D6 IO I,M P0[4] Analog column mux input. J6 IO P7[7] D7 IO M P2[6] External V oltage Reference (VREF) input. J7 IO P7[0] D8 IO M P4[6] J8 IO MP5[2] D9 IO M P4[0] J9 Power Vss Ground connection.

D10 NC No connection. J10 Power Vss Ground connection.

E1 NC No connection. K1 Power Vss Ground connection. E2 NC No connection. K2 Power Vss Ground connection. E3 IO M P4[3] K3 NC No connection. E4 IO I,M P2[3] Direct switched capacitor block input. K4 NC No connection. E5 Power Vss Ground connection. K5 Power Vdd Supply voltage. E6 Power Vss Ground connection. K6 IO P7[6] E7 IO M P2[4] External Analog Ground (AGND) input. K7 IO P7[5] E8 IO M P4[4] K8 IO P7[4] E9 IO M P3[6] K9 Power Vss Ground connection.

E10 NC No connection. K10 Power Vss Ground connection.

Name Description

Analog

Pin No.

Name Description

Digital

Analog

LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection.

* This is the ISSP pin, which is not High Z at POR. See the

PSoC Mixed-Signal Array Technical Reference Manual for details.

February 15, 2007 Document No. 38-12018 Rev. *J 13

Page 14

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 1. Pin Information

CY8C24994

12345678910

Vss

Vdd

Vss

P4[2]

P4[0]

P3[6]

XRES

P5[6]

P5[4]

Vss

P7[1]

P7[2]

P7[3]

Vss

P2[1]

P0[1]

P0[7]

Vdd

P0[2]

P0[0]

P2[6]

P2[4]

P5[0]

P1[6]

P1[4]

P7[0]

P7[5]

P2[2]

P2[0]

P4[6]

P4[4]

P3[0]

P3[4]

P3[2]

P5[2]

P7[4]

P4[1]

P4[7]

P2[7]

P0[5]

P0[3]

Vss

P1[1]

P1[3]

Vdd

P0[6]

P0[4]

Vss

P1[0]

P1[2]

P7[7]

P7[6]

P3[7]

P4[5]

P4[3]

P3[5]

P3[3]

P3[1]

D +

P2[5]

P2[3]

P5[1]

P1[7]

P1[5]

D -

Vss

P5[7]

P5[5]

P5[3]

Vss

F G H

J K

BGA (Top View)

February 15, 2007 Document No. 38-12018 Rev. *J 14

Page 15

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 1. Pin Information

1.6 100-Ball VFBGA Part Pinout (On-Chip Debug)

The 100-pin VFBGA part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production. Table 1-6. 100-Ball Part Pinout (VFBGA)

Pin No.

Digital

A1 Power Vss Ground connection. F1 OCDE OCD even data IO. A2 Power Vss Ground connection. F2 IO M P5[7] A3 NC No connection. F3 IO M P3[5] A4 NC No connection. F4 IO M P5[1] A5 NC No connection. F5 Power Vss Ground connection. A6 Power Vdd Supply voltage. F6 Power Vss Ground connection. A7 NC No connection. F7 IO M P5[0] A8 NC No connection. F8 IO M P3[0] A9 Power Vss Ground connection. F9 XRES Active high pin reset with internal pull down.

A10 Power Vss Ground connection. F10 IO P7[1]

B1 Power Vss Ground connection. G1 OCDO OCD odd data output. B2 Power Vss Ground connection. G2 IO M P5[5] B3 IO I,M P2[1] Direct switched capacitor block input. G3 IO M P3[3] B4 IO I,M P0[1] Analog column mux input. G4 IO M P1[7] I2C Serial Clock (SCL). B5 IO I,M P0[7] Analog column mux input. G5 IO M P1[1] I2C Serial Clock (SCL), ISSP SCLK*. B6 Power Vdd Supply voltage. G6 IO M P1[0] I2C Serial Data (SDA), ISSP SDATA*. B7 IO I,M P0[2] Analog column mux input. G7 IO M P1[6] B8 IO I,M P2[2] Direct swit ched capacitor block input. G8 IO M P3[4] B9 Power Vss Ground connection. G9 IO M P5[6]

B10 Power Vss Ground connection. G10 IO P7[2]

C1 NC No connection. H1 NC No connection. C2 IO M P4[1] H2 IO M P5[3] C3 IO M P4[7] H3 IO M P3[1] C4 IO M P2[7] H4 IO M P1[5] I2C Serial Data (SDA). C5 IO IO,M P0[5] Analog column mux input and column output. H5 IO M P1[3] C6 IO I,M P0[6] Analog column mux input. H6 IO M P1[2] C7 IO I,M P0[0] Analog column mux input. H7 IO M P1[4] C8 IO I,M P2[0] Direct switched capacitor block input. H8 IO M P3[2] C9 IO M P4[2] H9 IO M P5[4]

C10 NC No connection. H10 IO P7[3]

D1 NC No connection. J1 Power Vss Ground connection. D2 IO M P3[7] J2 Power Vss Ground connection. D3 IO M P4[5] J3 USB D+ D4 IO M P2[5] J4 USB DD5 IO IO,M P0[3] Analog column mux input and column output. J5 Power Vdd Supply voltage. D6 IO I,M P0[4] Analog column mux input. J6 IO P7[7] D7 IO M P2[6] External Voltage Reference (VREF) input. J7 IO P7[0] D8 IO M P4[6] J8 IO M P5[2] D9 IO M P4[0] J9 Power Vss Ground connection.

D10 CCLK OCD CPU clock output. J10 Power Vss Ground connection.

E10 HCLK OCD high-speed clock output. K10 Power Vss Ground connection.

Name Description

Analog

No.

Name Description

Digital

Analog

LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.

* This is the ISSP pin, which is not High Z at POR. See the

PSoC Mixed-Signal Array Technical Reference Manual for details.

February 15, 2007 Document No. 38-12018 Rev. *J 15

Page 16

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 1. Pin Information

CY8C24094 OCD

12345678910

Vss

Vdd

Vss

P4[2]

P4[0]

P3[6]

XRES

P5[6]

P5[4]

Vss

CClk

HClk

P7[1]

P7[2]

P7[3]

Vss

P2[1]

P0[1]

P0[7]

Vdd

P0[2]

P0[0]

P2[6]

P2[4]

P5[0]

P1[6]

P1[4]

P7[0]

P7[5]

P2[2]

P2[0]

P4[6]

P4[4]

P3[0]

P3[4]

P3[2]

P5[2]

P7[4]

P4[1]

P4[7]

P2[7]

P0[5]

P0[3]

Vss

P1[1]

P1[3]

Vdd

P0[6]

P0[4]

Vss

P1[0]

P1[2]

P7[7]

P7[6]

P3[7]

P4[5]

P4[3]

P3[5]

P3[3]

P3[1]

D +

P2[5]

P2[3]

P5[1]

P1[7]

P1[5]

D -

ocde

ocdo

Vss

P5[7]

P5[5]

P5[3]

Vss

E F G H

BGA (Top View)

Not for Production

February 15, 2007 Document No. 38-12018 Rev. *J 16

Page 17

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 1. Pin Information

1.7 100-Pin Part Pinout (On-Chip Debug)

The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production. T able 1-7. 100-Pin Part Pinout (TQFP)

Pin No.

1 NC No connection. 51 IO MP1[6] 2 NC No connection. 52 IO MP5[0] 3 IO I, M P0[1] Analog column mux input. 53 IO MP5[2] 4 IO M P2[7] 54 IO M P5[4] 5 IO M P2[5] 55 IO M P5[6] 6 IO I, M P2[3] Direct switched capacitor block input. 56 IO MP3[0] 7 IO I, M P2[1] Direct switched capacitor block input. 57 IO MP3[2] 8 IO M P4[7] 58 IO M P3[4]

9 IO M P4[5] 59 IO M P3[6] 10 IO MP4[3] 60 HCLK OCD high-speed clock output. 11 IO MP4[1] 61 CCLK OCD CPU clock output. 12 OCDE OCD even data IO. 62 Input XRES Active high pin reset with internal pull down. 13 OCDO OCD odd data output. 63 IO M P4[0] 14 NC No connection. 64 IO MP4[2] 15 Power Vss Ground connection. 65 Power Vss Ground connection. 16 IO M P3[7] 66 IO M P4[4] 17 IO M P3[5] 67 IO M P4[6] 18 IO MP3[3] 68 IO I, M P2[0] Direct switched capacitor block input. 19 IO MP3[1] 69 IO I, M P2[2] Direct switched capacitor block input. 20 IO M P5[7] 70 IO P2[4] External Analog Ground (AGND) input. 21 IO M P5[5] 71 NC No connection. 22 IO MP5[3] 72 IO P2[6] External Voltage Reference (VREF) input. 23 IO MP5[1] 73 NC No connection. 24 IO M P1[7] I2C Serial Clock (SCL). 74 IO I P0[0] Analog column mux input. 25 NC No connection. 75 NC No connection. 26 NC No connection. 76 NC No connection. 27 NC No connection. 77 IO I, M P0[2] Analog column mux input and column output. 28 IO P1[5] I2C Serial Data (SDA) 78 NC No connection. 29 IO P1[3] 79 IO I, M P0[4] Analog column mux input and column output. 30 IO P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

31 NC No connection. 81 IO I, M P0[6] Analog column mux input . 32 Power Vss Ground connection. 82 Power Vdd Supply voltage. 33 USB D+ 83 NC No connection. 34 USB D- 84 Power Vss Ground connection. 35 Power Vdd Supply voltage. 85 NC No connection. 36 IO P7[7] 86 NC No connection. 37 IO P7[6] 87 NC No connection. 38 IO P7[5] 88 NC No connection. 39 IO P7[4] 89 NC No connection. 40 IO P7[3] 90 NC No connection. 41 IO P7[2] 91 NC No connection. 42 IO P7[1] 92 NC No connection. 43 IO P7[0] 93 NC No connection. 44 NC No connection. 94 NC No connection. 45 NC No connection. 95 IO I, M P0[7] Analog column mux input. 46 NC No connection. 96 NC No connection. 47 NC No connection. 97 IO IO, M P0[5] Analog column mux input and column output. 48 IO P1[0] Crystal (XTALout), I2C Serial Data (SDA),

49 IO P1[2] 99 IO IO, M P0[3] Analog column mux input and column output. 50 IO P1[4] Optional External Clock Input (EXTCLK). 100 NC No connection.

Name Description

Digital

Analog

ISSP SCLK*.

ISSP SDATA*.

Pin No.

Digital

80 NC No connection.

98 NC No connection.

Name Description

Analog

LEGEND A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.

* These are the ISSP pins, which are not High Z at POR. See the

PSoC Mixed-Signal Array Technical Reference Manual for details.

February 15, 2007 Document No. 38-12018 Rev. *J 17

Page 18

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 1. Pin Information

CY8C24094 OCD

P0[3], M, AINCP0[5], M, AINCP0[7], M, AINCNCNCNCNCNCNCNCNCNC

VssNCVdd

P0[6], M, AINCP0[4], M, AINCP0[2], M, AI

NC NC

AI, M, P0[1]

M, P2[7]

M, P2[5] AI, M, P2[3] AI, M, P2[1]

M, P4[7]

M, P4[5]

M, P4[3]

M, P4[1]

OCDE OCDO

Vss M, P3[7] M, P3[5]

M, P3[3] M, P3[1]

M, P5[7] M, P5[5] M, P5[3]

M, P5[1]

I2C SC L, P1[ 7]

9998979695949392919089888786858483828180797877

100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647485049

D+

Vss

M, P1[3]

TQFP

D-

Vdd

P7[7]

P7[6]

P7[5]

P7[4]

P7[2]

P7[3]

P7[1]

NCNCNC

P7[0]

75 74

P0[0], M, AI NC

73 72

P2[6], M, Ex ternal VREF

P2[4], M, Ex ternal AGN D

P2[2], M, AI P2[0], M, AI

P4[6], M

P4[4], M

Vss

P4[2], M

64 63

P4[0], M XRES

62 61

CCLK

HCLK P3[6], M

P3[4], M

P3[2], M

P3[0], M

P5[6], M

P5[4], M

P5[2], M

P5[0], M

52 51

P1[6], M

M, P1[2]

M, P1[4]

I2C SCL, M, P1[1]

I2C SD A, M , P1[5]

I2C SD A, M , P1[0]

Not for Production

February 15, 2007 Document No. 38-12018 Rev. *J 18

Page 19

2. Register Reference

This chapter lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the PSoC Mixed-Signal Array Technical Reference Manual.

2.1 Register Conventions

2.1.1 Abbreviations Used

The register conventions specific to this section are listed in the following table.

Convention Description

R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific

2.2 Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are Reserved and should not be accessed.

February 15, 2007 Document No. 38-12018 Rev. *J 19

Page 20

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 2. Register Reference

Access

Name

(0,Hex)

Addr

Name

(0,Hex)

Addr

Access

Name

(0,Hex)

Addr

Access

Name

(0,Hex)

Addr

Access

PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2

PRT7DR PRT7IE PRT7GS PRT7DM2 DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0

Blank fields are Reserved and should not be accessed. # Access is bit specific.

00 RW PMA0_DR 40 RW 01 RW PMA1_DR 41 RW 02 RW PMA2_DR 42 RW 03 RW PMA3_DR 43 RW 04 RW PMA4_DR 44 RW 05 RW PMA5_DR 45 RW 06 RW PMA6_DR 46 RW 07 RW PMA7_DR 47 RW 08 RW USB_SOF0 48 R 88 C8 09 RW USB_SOF1 49 R 89 C9 0A RW USB_CR0 4A RW 8A CA 0B RW USBIO_CR0 4B # 8B CB 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 EP0_DR0 58 RW 98 19 EP0_DR1 59 RW 99 1A EP0_DR2 5A RW 9A 1B EP0_DR3 5B RW 9B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F

USBIO_CR1 4C RW 8C CC

RW RW

EP1_CNT1 4E # 8E CE

EP1_CNT 4F RW 8F CF

EP2_CNT1 50 #

EP2_CNT 51 RW

EP3_CNT1 52 #

EP3_CNT 53 RW

EP4_CNT1 54 #

EP4_CNT 55 RW

EP0_CR 56 #

EP0_CNT 57 #

EP0_DR4 5C RW 9C

EP0_DR5 5D RW 9D

EP0_DR6 5E RW 9E

EP0_DR7 5F RW 9F

RW # AMX_IN W AMUXCFG RW # ARF_CR # CMP_CR0 W ASY_CR RW CMP_CR1 # # W RW # # TMP_DR0 W TMP_DR1 RW TMP_DR2 # TMP_DR3

ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2

4D 8D CD

60 61 62 A2 63 64 65 66 67 A7 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 B8 F8 79 B9 F9 7A BA FA 7B BB FB 7C BC FC 7D BD 7E BE 7F BF

RW RW

RW # # RW

RW RW RW RW RW RW RW RW RW RW RW RW

ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3

ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3

MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1

80 81 82 83 84 85 86 87

90 91 92 93 94 95 96 97

A0 A1

A3 A4 A5 A6

A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7

RW RW RW RW RW RW RW RW

RW CUR_PP RW STK_PP RW RW IDX_PP RW MVR_PP RW MVW_PP RW I2C_CFG RW I2C_SCR

I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1

MUL0_X

MUL0_Y

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2 RW RW RW RW RW RW RW

CPU_F

DAC_D

CPU_SCR1

CPU_SCR0

C0 C1 C2 C3 C4 C5 C6 C7

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7

FD FE FF

RW RW

RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW

RW # #

February 15, 2007 Document No. 38-12018 Rev. *J 20

Page 21

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 2. Register Reference

Access

Name

(1,Hex)

Addr

Name

(1,Hex)

Access

Addr

Name

(1,Hex)

Access

Addr

Name

(1,Hex)

Access

Addr

PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1

PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN DBB00IN DBB00OU

DBB01FN DBB01IN DBB01OU

DCB02FN DCB02IN DCB02OU

DCB03FN DCB03IN DCB03OU

Blank fields are Reserved and should not be accessed. # Access is bit specific.

RW PMA0_WA

RW PMA1_WA

RW PMA2_WA

RW PMA3_WA

RW PMA4_WA

RW PMA5_WA

RW PMA6_WA

RW PMA7_WA

RW PMA0_RA

RW PMA1_RA

RW PMA2_RA

RW PMA3_RA

RW PMA4_RA

RW PMA5_RA

RW 17 18 58 98 19 59 99 1A 5A 9A 1B 5B 9B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 6B AB 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 7B BB FB 3C 3D 3E 3F 7F BF CPU_SCR0 FF #

PMA6_RA

PMA7_RA

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0 RW CMP_GO_EN RW CMP_GO_EN1 RW AMD_CR1

ALT_CR0 RW RW RW

RW TMP_DR0 RW TMP_DR1 RW TMP_DR2

TMP_DR3

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

RW RW RW RW RW RW RW RW

RW RW RW RW RW RW RW RW RW RW RW RW

ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3

ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3

RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1

41 42 43 44 45 46 47 48 88 C8 49 89 C9 4A 8A CA 4B 8B CB 4C 8C CC 4D 8D CD 4E 8E CE 4F 8F CF 50 51 52 53 54 55 56 57

5C 9C DC 5D 9D 5E 9E 5F 9F 60 61 62 63 64 65 66 67 68 A8 69 A9 6A AA

6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 B8 F8 79 B9 F9 7A BA FA

7C BC FC 7D BD 7E BE

80 81 82 83 84 85 86 87

90 91 92 93 94 95 96 97

A0 A1 A2 A3 A4 A5 E5 A6 E6 A7 E7

AC AD AE EE AF EF B0 B1 B2 B3 B4 B5 B6 B7

USBIO_CR2 C0 RW

USB_CR1 C1 #

RW RW RW

EP1_CR0 C4 #

EP2_CR0 C5 #

EP3_CR0 C6 #

EP4_CR0 C7 #

GDI_O_IN RW GDI_E_IN RW GDI_O_OU RW GDI_E_OU RW RW RW RW

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

VLT_CMP

IMO_TR

ILO_TR

BDG_TR

ECO_TR

MUX_CR4

MUX_CR5

RW RW RW RW RW RW RW

CPU_F

DAC_CR

CPU_SCR1

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB

DD DE DF E0 E1 E2 E3 E4

E8 E9 EA EB EC ED

F0 F1 F2 F3 F4 F5 F6 F7

FD FE

RW RW RW RW

RW RW RW RW RW RW RW R

W W RW W RW RW

RW #

February 15, 2007 Document No. 38-12018 Rev. *J 21

Page 22

3. Electrical S pecifications

This chapter presents the DC and AC electrical specifications of the CY8C24x9 4 PSoC device family. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40 than 12 MHz are valid for -40

Figure 3-1. Voltage versus CPU Frequency

5.25

C ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater

C ≤ TA ≤ 70oC and TJ ≤ 82oC.

4.75

Vdd Voltage

3.00

93 kHz 12 MHz 24 MHz

CPU Frequency

The following table lists the units of measure that are used in this chapter.

Table 3-1: Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

dB decibels mA milli-ampere

fF femto farad ms milli-second Hz hertz mV milli-volts KB 1024 bytes nA nanoampere

Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts

kΩ kilohm Ω ohm

MHz megahertz pA picoampere

MΩ megaohm pF picofarad

µA microampere pp peak-to-peak

µF microfarad ppm parts per million

µH microhenry ps picosecond

µs microsecond sps samples per second

µV microvolts σ sigma: one standard deviation

µVrms microvolts root-mean-square V volts

degree Celsius µW microwatts

February 15, 2007 Document No. 38-12018 Rev. *J 22

Page 23

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.1 Absolute Maximum Ratings

T able 3-2. Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

STG

Vdd Supply Voltage on Vdd Relat i ve to Vss -0.5 – +6.0 V V

IO2

MIO

MAIO

ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD. LU Latch-up Current – – 200 mA

Storage Temperature -55 25 +100

Ambient Temperature with Power Applied -40 – +85

DC Input Voltage Vss - 0.5 – Vdd + 0.5 V DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 V Maximum Current into any Port Pin -25 – +50 mA Maximum Current into any Port Pin Configured as Analog

Driver

-50 – +50 mA

Higher storage temperatures will reduce data retention time. Recommended storage temper-

ature is +25 age temperatures above 65

reliability.

C ± 25oC. Extended duration stor-

C will degrade

3.2 Operating Temperature

T able 3-3. Operating Temperature

Symbol Description Min Typ Max Units Notes

T T T

A AUSB J

Ambient Temperature -40 – +85 Ambient Temperature using USB -10 – +85 Junction Temperature -40 – +100

The temperature rise from ambient to junction is package specific. See “Thermal Impedance” on

page 42. The user must limit the power con-

sumption to comply with this requirement.

3.3 DC Electrical Characteristics

3.3.1 DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-4. DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 3.0 – 5.25 V See DC POR and LVD specifications, Table 3-

DD5

DD3

SBH

a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable sys te m opera tion. This s hould be compa red with devic es that have similar functions

enabled.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

15 on page 29.

Supply Current, IMO = 24 MHz (5V) – 14 27 mA

Supply Current, IMO = 24 MHz (3.3V) – 8 14 mA

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

WDT.

Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.

– 3 6.5 µA Conditions are with internal slow speed oscilla-

– 4 25 µA Conditions are with internal slow speed oscilla-

Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5

MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off.

Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5

MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off.

tor, Vdd = 3.3V, -40 power = off.

tor, Vdd = 3.3V, 55 power = off.

C ≤ TA ≤ 55 oC, analog

C < TA ≤ 85 oC, analog

February 15, 2007 Document No. 38-12018 Rev. *J 23

Page 24

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.3.2 DC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-5. DC GPIO Specifications

Symbol Description Min Typ Max Units Notes

OUT

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Pull-Up Resistor 4 5.6 8 kΩ Pull-Down Resistor 4 5.6 8 kΩ High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,

Input Low Level – – 0.8 V Vdd = 3.0 to 5.25. Input High Level 2.1 – V Vdd = 3.0 to 5.25. Input Hysterisis – 60 – mV Input Leakage (Absolute V alue) – 1 – nA Gross tested to 1 µA. Capacitive Load on Pins as Input – 3.5 10 pF Capacitive Load on Pins as Output – 3.5 10 pF

4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget.

4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 200 mA maximum combined IOL budget.

Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC.

3.3.3 DC Full-Speed USB Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -10°C ≤ T

are for design guidance only.

Table 3-6. DC Full-Speed (12 Mbps) USB Specification s

Symbol Description Min Typ Max Units Notes

USB Interface

EXT

UOH

UOHI

UOL

CRS

≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Differential Input Sensitivity 0.2 – – V | (D+) - (D-) | Differential Input Common Mode Range 0.8 – 2.5 V Single Ended Receiver Threshold 0.8 – 2.0 V Transceiver Capacitance – – 20 pF High-Z State Data Line Leakage -10 – 10 µA0V < V External USB Series Resistor 23 – 25 Ω In series with each USB pin. Static Output High, Driven 2.8 – 3.6 V 15 kΩ ± 5% to Ground. Internal pull-up enabled. Static Output High, Idle 2.7 – 3.6 V 15 kΩ ± 5% to Ground. Internal pull-up enabled. Static Output Low – – 0.3 V 15 kΩ ± 5% to Ground. Internal pull-up enabled. USB Driver Output Impedance 28 – 44 Ω Including R D+/D- Crossover Voltage 1.3 – 2.0 V

< 3.3V.

Resistor.

EXT

February 15, 2007 Document No. 38-12018 Rev. *J 24

Page 25

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.3.4 DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor

PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.

Table 3-7. 5V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV

OSOA

EBOA

INOA

CMOA

OLOA

OHIGHOA

OLOWOA

SOA

PSRR

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Average Input Offset Voltage Drift – 7.0 35.0

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Common Mode Voltage Range

Common Mode Voltage Range (high power or high opamp bias)

Open Loop Gain Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio 65 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN

–1.6 – –

0.0 – Vdd

0.5 –

60 60 80

Vdd - 0.2 Vdd - 0.2 Vdd - 0.5

– – –

– – – – – –

1.3

1.2

––dB

– – –

400 500 800 1200 2400 4600

10 8

7.5

Vdd - 0.5

– – –

0.2

0.5

800 900 1000 1600 3200 6400

mV mV mV

µV/

Package and pin dependent. Temp = 25

V The common-mode input voltage range is mea-

V V V

µA µA µA µA µA µA

sured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.

≤ Vdd.

February 15, 2007 Document No. 38-12018 Rev. *J 25

Page 26

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

T able 3-8. 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV

OSOA

EBOA

INOA

CMOA

OLOA

OHIGHOA

OLOWOA

SOA

PSRR

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only Average Input Offset Voltage Drift – 7.0 35.0

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage range is

Open Loop Gain Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High is 5V only Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio 65 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤

– –

60 60 80

Vdd - 0.2 Vdd - 0.2 Vdd - 0.2

– – –

– – – – – –

1.65

1.32

––dB

– – –

400 500 800 1200 2400 4600

10 8

– – –

0.2

800 900 1000 1600 3200 6400

mV mV

µV/

V V V

µA µA µA µA µA µA

Package and pin dependent. Temp = 25

measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.

VIN

≤ Vdd.

3.3.5 DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

apply to 5V at 25°C and are for design guidance only.

T able 3-9. DC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

REFLPC

SLPC

OSLPC

February 15, 2007 Document No. 38-12018 Rev. *J 26

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. T ypical parameters

Low power comparator (LPC) reference voltage range 0.2 – Vdd - 1 V LPC supply current – 10 40 µA LPC voltage offset – 2.5 30 mV

Page 27

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.3.6 DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-10. 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Input Offset Voltage (Absolute Value) – 3 12 mV Average Input Offset Voltage Drift – +6 – µV/°C Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V Output Resistance

Power = Low Power = High High Output Voltage Swing (Load = 32 ohms to Vdd/2)

Power = Low Power = High

Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High

Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ra tio 53 64 – dB (0.5 x Vdd - 1.3) ≤ V

– –

0.5 x Vdd + 1.1

0.5 x Vdd

– –

+ 1.1

0.6

– –

1.1

2.6

– –

0.5 x Vdd - 1.3

0.5 x Vdd

5.1

8.8

- 1.3

Ω

V V

mA mA

2.3).

OUT

≤ (Vdd -

T a ble 3-11. 3.3V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV Average Input Offset Voltage Drift – +6 – µV/°C Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V Output Resistance

Power = Low Power = High High Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High

Low Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High

Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio 34 64 – dB (0.5 x Vdd - 1.0) ≤ V

– –

0.5 x Vdd + 1.0

0.5 x Vdd

– –

–

+ 1.0

1 1

– –

0.8

2.0

– –

0.5 x Vdd - 1.0

0.5 x Vdd

2.0

4.3

- 1.0

Ω

V V

mA mA

Vdd + 0.9).

OUT

≤ (0.5 x

February 15, 2007 Document No. 38-12018 Rev. *J 27

Page 28

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.3.7 DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to

the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high.

T able 3-12. 5V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.28 1.30 1.32 V –

– – – – – – RefHi = Vdd/2 + BandGap – RefHi = 3 x BandGap 3 x BG - 0.06 3 x BG 3 x BG + 0.06 V

– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077 V – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 V – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100 V – RefHi = 3.2 x BandGap 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 V – RefLo = Vdd/2 – BandGap – RefLo = BandGap BG - 0.06 BG BG + 0.06 V – RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 V – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 V

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

AGND = Vdd/2 AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Block to Block Variation (A GND = Vdd/2 )

Vdd/2 - 0.04 Vdd/2 - 0.01 Vdd/2 + 0.007 V 2 x BG - 0.048 2 x BG - 0.030 2 x BG + 0.024 V P2[4] - 0.011 P2[4] P2[4] + 0.011 V BG - 0.009 BG + 0.008 BG + 0.016 V

1.6 x BG - 0.022 1.6 x BG - 0.010 1.6 x BG + 0.018 V

-0.034 0.000 0.034 V

Vdd/2 + BG - 0.10 Vdd/2 + BG Vdd/2 + BG + 0.10

Vdd/2 - BG - 0.04 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04

T able 3-13. 3.3V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.28 1.30 1.32 V –

– – AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] + 0.001 P2[4] + 0.009 V

– – – – RefHi = Vdd/2 + BandGap Not Allowed

– RefHi = 3 x BandGap Not Allowed – RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V – RefHi = 3.2 x BandGap Not Allowed – RefLo = Vdd/2 - BandGap Not Allowed – RefLo = BandGap Not Allowed – RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed – RefLo = P2[4]-P2 [6 ] (P 2[4 ] = Vdd/ 2 , P2[6 ] = 0.5V ) P2[4] - P2[6] - 0.048 P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092 V

AGND = Vdd/2 AGND = 2 x BandGap

AGND = BandGap AGND = 1.6 x BandGap AGND Column to Column Variation (AGND = Vdd/2)

Vdd/2 - 0.03 Vdd/2 - 0.01 Vdd/2 + 0.005 V Not Allowed

BG - 0.009 BG + 0.005 BG + 0.015 V

1.6 x BG - 0.027 1.6 x BG - 0.010 1.6 x BG + 0.018 V

-0.034 0.000 0.034 V

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

February 15, 2007 Document No. 38-12018 Rev. *J 28

Page 29

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.3.8 DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-14. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units Notes

Resistor Unit Value (Continuous Time) – 12.2 – kΩ Capacitor Unit Value (Switched Capacitor) – 80 – fF

3.3.9 DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

for design guidance only.

Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical Reference Manual for more information on the VLT_CR register.

Table 3-15. DC POR and LVD Specifications

Symbol Description Min Typ Max Units Notes

PPOR0R

PPOR1R

PPOR2R

PPOR0

PPOR1

PPOR2

PH0

PH1

PH2

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters apply to 5V or 3.3V at 25°C and are

Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

–

– – –

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

2.91

4.39

4.55

2.82

4.39

4.55

92 0 0

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

–

– – –

2.98

3.08

3.20

4.08

4.57

4.74

4.82

4.91

V V V

mV mV mV

V V

V V V V

V V V

February 15, 2007 Document No. 38-12018 Rev. *J 29

Page 30

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.3.10 DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

T able 3-16. DC Programming Specifications

Symbol Description Min Typ Max Units Notes

DDP

ILP

IHP

ILP

IHP

OLV

OHV

Flash

ENPB

Flash

ENT

Flash

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanc ed between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

25,000 maximum cycles each, or 36x4 blocks of 1 2,5 00 maximum c ycles each (t o limit t he total n umber of c ycles t o 3 6x50,00 0 and t hat no sing le block ev er see s more th an 50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Supply Current During Programming or Verif y – 15 30 mA Input Low Voltage During Programming or Verify – – 0.8 V Input High Voltage During Programming or Verify 2.1 – – V Input Current when Applying Vilp to P1[0] or P1[1] During

Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During

Programming or Verify Output Low Voltage During Pro gramming or Verify – – Vss + 0.75 V

Output High Voltage During Programming or Verify Vdd - 1.0 – Vdd V Flash Endurance (per block) 50,000 – – – Erase/write cycles per block. Flash Endurance (total)

Flash Data Retention 10 – – Years

– – 0.2 mA Driving internal pull-down resistor.

– – 1.5 mA Driving internal pull-down resistor.

1,800,000 – – – Erase/write cycles.

February 15, 2007 Document No. 38-12018 Rev. *J 30

Page 31

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.4 AC Electrical Characteristics

3.4.1 AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

T able 3-17. AC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

IMO245V

IMO243V

IMOUSB5V

IMOUSB3V

CPU1

CPU2

BLK5

BLK3

32K1

Jitter32k 32 kHz Period Jitter – 100 ns Step24M 24 MHz Trim Step Size – 50 – kHz Fout48M 48 MHz Output Frequency 46.08 48.0

Jitter24M1 24 MHz Period Jitter (IMO) Peak-to-Peak – 300 ps F

MAX

RAMP

a. 4.75V < Vdd < 5.25V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V. d. See the individual user module data sheets for information on maximum frequencies for user modules.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Internal Main Oscillator Frequency for 24 MHz (5V) 23.04 24

Internal Main Oscillator Frequency for 24 MHz (3.3V) 22.08 24

Internal Main Oscillator Frequency with USB (5V) Frequency locking enabled and USB traffic present.

Internal Main Oscillator Frequency with USB (3.3V) Frequency locking enabled and USB traffic present.

CPU Frequency (5V Nominal) 0.93 24 CPU Frequency (3.3V Nominal) 0.93 12 Digital PSoC Block Frequency (5V Nominal) 0 48 Digital PSoC Block Frequency (3.3V Nominal) 0 24 Internal Low Speed Oscillator Frequency 15 32 64 kHz

Maximum frequency of signal on row input or row output. – – 12.96 MHz Supply Ramp Time 0 – – µs

23.94 24

24.96

25.92

24.06

24.96

12.96

49.92

25.92

49.92

a,b

MHz Trimmed for 5V operation using factory trim

b,c

MHz Trimmed for 3.3V operation using factory

MHz -10°C ≤ TA ≤ 85°C

MHz -0°C ≤ TA ≤ 70°C

a,b

MHz

b,c

MHz

a,b,d

MHz Refer to the AC Digital Block Specifications.

b, d

MHz

a,c

MHz Trimmed. Utilizing factory trim values.

values.

trim values.

4.35

≤ Vdd ≤ 5.15

≤ Vdd ≤ 3.45

3.15

Figure 3-2. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

24M

February 15, 2007 Document No. 38-12018 Rev. *J 31

Page 32

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.4.2 AC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

T able 3-18. AC GPIO Specifications

Symbol Description Min Typ Max Units Notes

GPIO

TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%

Figure 3-3. GPIO Timing Diagram

90%

GPIO

Output

Voltage

10%

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

GPIO Operating Frequency 0 – 12 MHz Normal Strong Mode

TRise F TRise S

TFallF TF allS

3.4.3 AC Full-Speed USB Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -10°C ≤ T

are for design guidance only.

T able 3-19. AC Full-Speed (12 Mbp s) USB S pecifications

Symbol Description Min Typ Max Units Notes

RFS

FSS

RFMFS

DRATEFS

≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Transition Rise Time 4 – 20 ns For 50 pF load. Transition Fall Time 4 – 20 ns For 50 pF load. Rise/Fall Time Matching: (TR/TF)90– 111 % For 50 pF load. Full-Speed Data Rate 12 - 0.25% 12 12 + 0.25% Mbps

February 15, 2007 Document No. 38-12018 Rev. *J 32

Page 33

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.4.4 AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Power = High and Opamp Bias = High is not supported at 3.3V

T able 3-20. 5V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

ROA

SOA

ROA

FOA

NOA

Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

– – –

0.15

1.7

6.5

0.01

0.5

4.0

0.75

3.1

5.4

– – –

3.9

0.72

0.62

5.9

0.92

0.72

– – –

µs µs µs

V/ V/ V/

MHz MHz MHz

µs µs µs

T able 3-21. 3.3V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

ROA

SOA

ROA

FOA

NOA

Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

– –

0.31

2.7

0.24

1.8

0.67

2.8

– –

3.92

0.72

5.41

0.72

– –

µs µs

V/ V/

MHz MHz

µs µs

February 15, 2007 Document No. 38-12018 Rev. *J 33

Page 34

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 3-4. Typical AGND Noise with P2[4] Bypass

dBV/rtHz 10000

0.01

0.1

1.0 10

1000

100

0.001 0.01 0.1 1 10 100Freq (kHz)

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level.

Figure 3-5. Typical Opamp Noise

nV/rtHz 10000

PH_BH PH_BL PM_BL PL_BL

1000

100

0.001 0.01 0.1 1 10 100

Freq (kHz)

February 15, 2007 Document No. 38-12018 Rev. *J 34

Page 35

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.4.5 AC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

apply to 5V at 25°C and are for design guidance only.

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. T ypical parameters

Table 3-22. AC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

RLPC

LPC response time – – 50 µs ≥ 50 mV overdrive comparator reference set

within V

REFLPC

3.4.6 AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

T able 3-23. AC Digita l Block Specifications

Function Description Min Typ Max Units Notes

Timer Capture Pulse Width

Counter Enable Pulse Width

Dead Band Kill Pulse Width:

CRCPRS (PRS Mode)

CRCPRS (CRC Mode)

SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2 x ov er

SPIS Maximum Input Clock Frequency – – 4.1 MHz

Transmitter Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over

Receiver Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

50 Maximum Frequency, No Capture – – 49.92 MHz 4.75V < Vdd < 5.25V. Maximum Frequency, With Capture – – 25.92 MHz

50 Maximum Frequency, No Enable Input – – 49.92 MHz 4.75V < Vdd < 5.25V. Maximum Frequency, Enable Input – – 25.92 MHz

Asynchronous Restart Mode 20 – – ns Synchronous Restart Mode

Disable Mode

Maximum Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V. Maximum Input Clock Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.

Maximum Input Clock Frequency – – 24.6 MHz

Width of SS_ Negated Between Transmissions

– – ns

clocking.

3.4.7 AC External Clock Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

T able 3-24. AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

OSCEXT

– Duty Cycle 47 – Power up to IMO Switch 150

February 15, 2007 Document No. 38-12018 Rev. *J 35

Frequency for USB Applications 23.94 24 24.06 MHz

50 53 % – – µs

Page 36

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.4.8 AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

Table 3-25. 5V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

ROB

SOB

ROB

FOB

OBSS

OBLS

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

Power = Low Power = High

–

0.65

0.8

300

– –

2.5

2.2

– –

µs µs

V/µs V/

MHz MHz

kHz kHz

µs

Table 3-26. 3.3V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

ROB

SOB

ROB

Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

FOB

Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

OBSS

Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

OBLS

Power = Low Power = High

–

0.5

0.7

200

– –

3.8

2.6

– –

µs µs

V/µs V/

MHz MHz

kHz kHz

µs

February 15, 2007 Document No. 38-12018 Rev. *J 36

Page 37

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.4.9 AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

T able 3-27. AC Programming Specifications

Symbol Description Min Typ Max Units Notes

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

ERASEB

WRITE

DSCLK

DSCLK3

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Rise Time of SCLK 1 – 20 ns Fall Time of SCLK 1 – 20 ns Data Set up Time to Falling Edge of SCLK 40 – – ns Data Hold Time from Falling Edge of SCLK 40 – – ns Frequency of SCLK 0 – 8 MHz Flash Erase Time (Block) – 10 – ms Flash Block Write Time – 30 – ms Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6

February 15, 2007 Document No. 38-12018 Rev. *J 37

Page 38

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 3. Electrical Specifications

3.4.10 AC I2C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T

are for design guidance only.

T able 3-28. AC Characteristics of the I

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

SPI2C

a. A Fast-Mode I2C-bus device can be used in a Standard-Mo de I2C-b us s ystem, but the requireme nt t

the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t

rmax

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

C SDA and SCL Pins for Vdd

Standard Mode Fast Mode

Units NotesMin Max Min Max

SCL Clock Frequency 0 100 0 400 kHz Hold Time (repeated) START Condition. After this period,

the first clock pulse is generated. LOW Period of the SCL Clock 4.7 –1.3– µs

HIGH Period of the SCL Clock 4.0 –0.6– µs Set-up Time for a Repeated START Condition 4.7 –0.6– µs Data Hold Time 0 –0– µs Data Set-up Time 250 – Set-up Time for STOP Condition 4.0 –0.6– µs Bus Free Time Between a STOP and START Condition 4.7 –1.3– µs Pulse Width of spikes are suppressed by the input filter. – –050ns

+ t

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SU;DAT

4.0 –0.6– µs

100

SU;DAT

–ns

≥ 250 ns must then be met. This will automatically be the cas e if

SDA

SCL

LOWI2C

HDSTAI2C

Figure 3-6. Definition for Timing for Fast/Standard Mode on the I

SPI2C

SUSTOI2C

HDDATI2C

SUDATI2C

HIGHI2C

SUSTAI2C

HDSTAI2C

C Bus

BUFI2C

February 15, 2007 Document No. 38-12018 Rev. *J 38

Page 39

4. Packaging Information

This chapter illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package and solder reflow peak temperatures.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

4.1 Packaging Dimensions

Figure 4-1. 56-Lead (8x8 mm) QFN

001-12921 **

February 15, 2007 Document No. 38-12018 Rev. *J 39

Page 40

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 4. Packaging Information

Figure 4-2. 68-Lead (8x8 mm x 0.89 mm ) QF N

51-85214 *C

Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.

February 15, 2007 Document No. 38-12018 Rev. *J 40

Page 41

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 4. Packaging Information

Figure 4-3. 100-Ball (6x6 mm) VFBGA

Figure 4-4. 100-Lead (14x14 x 1.4 mm) TQFP

51-85209 *B

51-85048 *C

February 15, 2007 Document No. 38-12018 Rev. *J 41

Page 42

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 4. Packaging Information

4.2 Thermal Impedance

Table 4-1. Thermal Impedance for the Package

Package Typical θ

56 QFN** 68 QFN**

100 VFBGA

* TJ = TA + POWER x θ ** To achieve the thermal impedance specified for the QFN package, the center

thermal pad should be soldered to the PCB ground plane.

12.93 oC/W

13.05 oC/W 65 oC/W

4.3 Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 4-2. Solder Reflow Peak Temperature

Package Minimum Peak Temperature* Maximum Peak Temperature

56 QFN 68 QFN

100 VFBGA

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5

C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

240oC 260oC 240oC 260oC 240oC 260oC

February 15, 2007 Document No. 38-12018 Rev. *J 42

Page 43

5. Development Tool Selection

This chapter presents the development tools available for all current PSoC device families includ ing the CY8C24x94 family.

5.1 Software

5.1.1 PSoC Designer™

At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://

www.cypress.com under DESIGN RESOURCES >> Software

and Drivers.

5.1.2 PSoC Express™

As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocex-

press.

5.1.3 PSoC Programmer

Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube InCircuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocpro-

grammer.

5.2 Development Kits

All development kits can be purchased from the Cypress Online Store.

5.2.1 CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

5.1.4 CY3202-C iMAGEcraft C Compiler

CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items..

February 15, 2007 Document No. 38-12018 Rev. *J 43

Page 44

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 5. Development Tool Selection

5.2.2 CY3210-ExpressDK PSoC Express Development Kit

The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Cir-

cuit Emulator). It provides access to I

C buses, voltage reference, switches, upgradeable modules and more. The kit includes:

■ PSoC Express Software CD

■ Express Development Board

■ 4 Fan Modules

■ 2 Proto Modules

■ MiniProg In-System Serial Programmer

■ MiniEval PCB Evaluation Board

■ Jum per Wire Kit

■ USB 2.0 Cable

■ Serial Cable (DB9)

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples

■ 2 CY8C27443-24PXI 28-PDIP Chip Samples

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

5.3 Evaluation Tools

All evaluation tools can be purchased from the Cypress Online Store.

5.3.1 CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval So cket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

5.3.2 CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■ Evaluati on Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

5.3.3 CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

■ PSoCEvalUSB Board

■ L CD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

5.4 Device Programmers

All device programmers can be purchased from the Cypress Online Store.

5.4.1 CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

■ Modular Programmer Base

■ 3 Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

5.4.2 CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust th an the MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

February 15, 2007 Document No. 38-12018 Rev. *J 44

Page 45

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 5. Development Tool Selection

5.5 Accessories (Emulation and Programming)

Table 5-1. Emulation and Programming Accessories

Part # Pin

CY8C24794

-24LFXI CY8C24894

-24LFXI

a. Flex-Pod kit includes a practice flex-pod a nd a practice PCB, in addition to two b. Foot kit includes surface mount feet that can be soldered to the target PCB.

c. Programming adapter converts non-DIP package to DIP footprint. Specific

Package

56 QFN CY3250-

flex-pods.

details and ordering information for each of the adapters can be found at

http://www.emulation.com.

Flex-Pod Kit

24X94QFN

CY325056QFN-FK

Foot Kit

Adapter

AS-56-28

AS-28-28-02SS6ENG-GANG

5.6 3rd-Party Tools

Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards.

5.7 Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/

an2323.

February 15, 2007 Document No. 38-12018 Rev. *J 45

Page 46

6. Ordering Information

The following table lists the CY8C24x94 PSoC device’s key package features and ordering codes.

T able 6-1. CY8C24x94 PSoC Device’s Key Features and Ordering Information

Package

56 Pin (8x8 mm) QFN CY8C24794-24LFXI 16K 1K -40C to +85C 4 6 50 48 2 No 56 Pin (8x8 mm) QFN

(Tape and Reel) 56 Pin (8x8 mm) QFN CY8C24894-24LFXI 16K 1K -40C to +85C 4 6 49 47 2 Yes 56 Pin (8x8 mm) QFN

(Tape and Reel) 68 Pin OCD (8x8 mm) QFN 68 Pin (8x8 mm) QFN 68 Pin (8x8 mm) QFN

(Tape and Reel) 100 Ball OCD (6x6 mm) VFBGA

100 Ball (6x6 mm) VFBGA CY8C24994-24BVXI 16K 1K -40C to +85C 4 6 56 48 2 Yes 100 Pin OCD TQFP

a. This part may be used for in-circuit debugging. It is NOT available for production.

CY8C24794-24LFXIT 16K 1K -40C to +85C 4 6 50 48 2 No

CY8C24894-24LFXIT 16K 1K -40C to +85C 4 6 49 47 2 Yes CY8C24094-24LFXI 16K 1K -40C to +85C 4 6 56 48 2 Yes

CY8C24994-24LFXI 16K 1K -40C to +85C 4 6 56 48 2 Yes CY8C24994-24LFXIT 16K 1K -40C to +85C 4 6 56 48 2 Yes

CY8C24094-24BVXI 16K 1K -40C to +85C 4 6 56 48 2 Yes

CY8C24094-24AXI 16K 1K -40C to +85C 4 6 56 48 2 Yes

Code

Ordering

Flash

(Bytes)

SRAM

(Bytes)

Range

Temperature

Digital Blocks

Analog Blocks

Analog Inputs

Digital IO Pins

Analog Outputs

6.1 Ordering Code Definitions

CY 8 C 24 xxx-SPxx

Package Type: Thermal Rating:

PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free

BVX = VFBGA Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress

XRES Pin

February 15, 2007 Document No. 38-12018 Rev. *J 46

Page 47

7. Sales and Company Information

To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information.

Cypress Semiconductor

198 Champion Court San Jose, CA 95134

408.943.2600

Web Sites: Co mpany Information – http://www.cypress.com

Sales – http://www.cypress.com/aboutus/sales_locations.cfm

Technical Support – http://www.cypress.com/support/login.cfm

7.1 Revision History

T able 6-1. CY8C24x94 Data Sheet Revision History

Document Title: CY8C24094, CY8C24794, CY8C24894 and CY8C24994 PSoC® Mixed-Signal Array Final Data Sheet Document Number: 38-12018

Revision ECN # Issue Date Origin of Change Description of Change

** 133189 01.27.2004 NWJ New silicon and new document – Advance Data Sheet. *A 251672 See ECN SFV First Preliminary Data Sheet. Changed title to encompass only the CY8C24794 because the CY8C24494 and

*B 289742 See ECN HMT Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2 MACs. Change 512 bytes of

*C 335236 See ECN HMT Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP programming pinout notation.

*D 344318 See ECN HMT Add new color and logo. Expand analog arch. diagram. Fix IO #. Update Electrical Specifications. *E 346774 See ECN HMT Add USB temperature specifications. Make data sheet Final. *F 349566 See ECN HMT Remove USB logo. Add URL to preferred dimensions for mounting MLF packages. *G 393164 See ECN HMT Add new device, CY8C24894 56-pin MLF with XRES pi n. Add Fimousb3v char. to specs. Upgrade to CY Per-

*H 469243 See ECN HMT Add ISSP note to pinout tables. Update typical and recommended Storage Temperature per industrial specs.

*I 561158 See ECN HMT Add Low Power Comparator (LP C) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC Device Character-

*J 728238 See ECN HMT Add CapSense SNR requirement reference . Updat e figure standards. Update Technical Training paragraphs.

Distribution: External/Public Posting: None

CY8C24694 are not being offered by Cypress MicroSystems.

SRAM to 1K. Add dimension key to package. Remove HAPI. Update diagrams, registers and specs.

Add Reflow Temp. table. Update features (MAC, Oscillator, and voltage range), registers (INT_CLR2/MSK2, second MAC), and specs. (Rext, IMO, analog output buffer...).

form logo and update corporate address and copyright.

Update Low Output Level maximum IOL budget. Add FLS_PR1 to Register Map Bank 1 for users to specify which Flash bank should be used for SROM operations. Add two new devices for a 68-pin QFN and 100-ball VFBGA under RPNs: CY8C24094 and CY8C24994. Add two packages for 68-pin QFN. Add OCD non-production pinouts and package diagrams. Update CY branding and QFN convention. Add new Dev. Tool section. Update copyright and trademarks.

istics table. Add detailed dimensions to 56-pin QFN package diagram and updat e revision. Secure one packa ge diagram/manufacturing per QFN. Update emulation pod/feet kit part numbers. Fix pinout type-o per TestTrack.

Add QFN package clarifications and dimensions. Update ECN-ed Amkor dimensioned QFN package diagram revisions. Reword SNR reference. Add new 56-pin QFN spec.

Page 48

CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet 7. Sales and Company Information

7.2 Copyrights and Code Protection

© Cypress Semiconductor Corporation. 2004-2007. All rights reserved. PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other right s. Cypress Semiconductor does not authorize its pro ducts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semicon ductor products are not war ranted nor intended to be used for medical, life-support , life-saving, critical control or safet y applications, unless pursuant to an express written agreement with Cypress Semiconductor. Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.

Cypress Semiconductor products meet the specifications contained in their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products.

February 15, 2007 Document No. 38-12018 Rev. *J 48

Datasheet CY8C24794 Datasheet (CYPRESS)

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

PSoC® Functional Overview

Getting Started

Development Tools

Designing with User Modules

Document Conventions

1. Pin Information

1.1 56-Pin Part Pinout

1.2 56-Pin Part Pinout (with XRES)

1.3 68-Pin Part Pinout

1.4 68-Pin Part Pinout (On-Chip Debug)

1.5 100-Ball VFBGA Part Pinout

1.6 100-Ball VFBGA Part Pinout (On-Chip Debug)

1.7 100-Pin Part Pinout (On-Chip Debug)

2. Register Reference

2.1 Register Conventions

2.1.1 Abbreviations Used

2.2 Register Mapping Tables

3. Electrical S pecifications

3.1 Absolute Maximum Ratings

3.2 Operating Temperature

3.3 DC Electrical Characteristics

3.3.1 DC Chip-Level Specifications

3.3.2 DC General Purpose IO Specifications

3.3.3 DC Full-Speed USB Specifications

3.3.4 DC Operational Amplifier Specifications

3.3.5 DC Low Power Comparator Specifications

3.3.6 DC Analog Output Buffer Specifications

3.3.7 DC Analog Reference Specifications

3.3.8 DC Analog PSoC Block Specifications

3.3.9 DC POR and LVD Specifications

3.3.10 DC Programming Specifications

3.4 AC Electrical Characteristics

3.4.1 AC Chip-Level Specifications

3.4.2 AC General Purpose IO Specifications

3.4.3 AC Full-Speed USB Specifications

3.4.4 AC Operational Amplifier Specifications

3.4.5 AC Low Power Comparator Specifications

3.4.6 AC Digital Block Specifications

3.4.7 AC External Clock Specifications

3.4.8 AC Analog Output Buffer Specifications

3.4.9 AC Programming Specifications

3.4.10 AC I2C Specifications

4. Packaging Information

4.1 Packaging Dimensions

4.2 Thermal Impedance

4.3 Solder Reflow Peak Temperature

5. Development Tool Selection

5.1 Software

5.1.3 PSoC Programmer

5.2 Development Kits

5.2.1 CY3215-DK Basic Development Kit

5.1.4 CY3202-C iMAGEcraft C Compiler

5.2.2 CY3210-ExpressDK PSoC Express Development Kit

5.3 Evaluation Tools

5.3.1 CY3210-MiniProg1

5.3.2 CY3210-PSoCEval1

5.3.3 CY3214-PSoCEvalUSB

5.4 Device Programmers

5.4.1 CY3216 Modular Programmer

5.4.2 CY3207ISSP In-System Serial Programmer (ISSP)

5.5 Accessories (Emulation and Programming)

5.6 3rd-Party Tools

5.7 Build a PSoC Emulator into Your Board

6. Ordering Information

6.1 Ordering Code Definitions

7. Sales and Company Information

7.1 Revision History

7.2 Copyrights and Code Protection