Datasheet CY7C68000 Datasheet (CYPRESS)

er

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CY7C6800 0

CY7C6800

TX2™ USB 2.0 UTMI Transceiv

1.0 EZ-USB TX2™ Features

The Cypress EZ-USB TX2™ is a Universal Serial Bus (USB)
specifica tion revisi on 2.0 tran sceiver, serial/d eserializer, to a
parallel interface of either 16 bits at 30 MHz or ei ght bits at 60
MHz. The TX2 provides a high-speed physical layer interface
that operates at the maximum allowable USB 2.0 bandwidth.
This allows the system designer to keep the complex high­speed analog USB components external to the digital ASIC
which decreases development time and associated risk. A
standard interface is provided that is USB 2.0-certified and is
compliant with Transceiver Macrocell Interface (UTMI) speci­fication version 1.05 dated 3/29/01.

Two p ackages are defi ned for the fami ly: 56-pin SSOP and 56­pin QFN.

The function block diagram is shown in Figure 1-1. The
features of the EX-USB TX2 are:

• UTMI-compliant/USB-2.0-certified for device operation

• Operates in both USB 2.0 high speed (HS), 480
Mbits/second, and full speed (FS), 12 Mbits/second

• Serial-to-parallel and parallel-to-serial conversions

• 8-bit unidirectional, 8-bit bidirectional, or 16-bit
bidirectional external data interface

CY7C68000

• Synchronous field and EOP detection on receive
packets

• Synchronous field and EOP generation on transmit
packets

• Data and clock recovery from the USB serial stream

• Bit stuffing/unstuffing; bit stuff error detection

• Staging register to manage data rate variation due to
bit stuffing/unstuffing

• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface

• Ability to switch betwee n F S an d HS te rmin ation s a nd
signaling

• Supports detec tion of USB reset, suspend, and resume

• Supports HS identification and de tection as defined by
the USB 2.0 Specification

• Supports transmission of resume signaling

• 3.3 V operation

• Two package options—56-pin QFN, and 56-pin SSOP

• All required terminations, including 1.5K-ohm pull up
on DPLUS, are internal to the chip

• Supports USB 2.0 test modes

XTALIN/

OUT

USB

OSC

USB

2.0

XCVR

20X
PLL

Full-Speed Rx

High-Speed Rx

High-Speed Tx

PLL_480

Traffic

Sync

Elasticity

Buffer

Fast

Digital

Rx

Fast

UTMI CLK

Digital

Rx

UTMI CLK

UTMI Rx Ctl

UTMI Rx Data 8/16

BIDI Option

Also

Digital

Full-Speed Tx

Tx

Digital

Tx

Figure 1-1. Block Diagram

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-08016 Rev. *H Revised May 2, 2006

Tx

UTMI Rx Data 8/16

UTMI Tx Ctl

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CY7C6800

2.0 Applications

• DSL modems

• ATA interface

• Memory card readers

• Legacy conversion devices

• Cameras

• Scanners

• Home PNA

• Wireless LAN

• MP3 players

•Networking

3.0 Functional Overview

3.1 USB Signaling Speed

TX2 operates at two of the rates defined in the USB Specifi­cation 2.0, dated April 27, 2000:

• Full speed, with a signaling bit rate of 12 Mbps

• High speed, with a signaling bit rate of 480 Mbps

TX2 does not support the lo w-sp eed (LS) si gnalin g rate of 1.5
Mbps.

3.2 Transceiver Clock Frequency

TX2 has an on-chip oscillator circuit that uses an external 24­MHz (±100-ppm) crystal with the following characteristics:

• Parallel resonant

• Fundamental mode

•500-μW drive lev el

• 27–33 pF (5% tolerance) load capacitors

An on-chip phase-locked loop (PLL) multiplies the 24-MHz
oscillator up to 30/60 MHz, as required by the transceiver
parallel data bus. The default UTMI interface clock (CLK)
frequency is determined by the DataBus16_8 pin.

3.3 Buses

The two packages allow for 8/16-bit bidirectional data bus for
data transfe rs to a controlling unit.

3.4 Reset Pin

An input pin (Reset) resets the chip. This pin has hysteresis
and is active HIGH according to the UTMI specification. The
internal PLL stabilizes approximately 200 μs after V
reached 3.3V.

3.5 Line State

The Line S tat e output pins Line S t ate[1:0] ar e driven by com bi­national logic and may be toggling between the J and the K
states. They are synchronized to the CLK signal for a valid

CC

has

signal. On the CLK edge the state of these lines reflect the
state of the USB data lines. Upon the clock edge the 0-bit of
the LineState pins is the state of the DPLUS line and the one
bit of Lin eState is the DMINU S li ne. Wh en syn chron ized, the
set up and hold timing of the LineState is identical to the
parallel data bus.

3.6 Full-speed vs. High-speed Select

The FS vs. HS is done through the use of bo th XcvrSelect and
the TermSelect input signals. The TermSelect signal enables
the 1.5 K ohm pull up on to the D PLUS pin . When TermSele ct
is driven LOW , a SE0 is asserted on the USB provi ding the HS
termination and generating the HS Idle state on the bus. The
XcvrSelect signal is the control which selects either the FS
transceivers or the HS transceivers. To select the HS trans­ceivers, set this pin to ‘0’. To select the FS transceivers, set
this pin to ‘1’.

3.7 Operational Modes

The operational m odes ar e controll ed by the O pMode sign als.
The OpMode signals are capable of inhibiting normal
operation of the transceiver and evoking special test
These modes take effect immediately and take precedence
over any pending dat a op eration s. The tran smissi on dat a rate
when in OpMode depends on the state of the XcvrSelect
input.

OpMode[1:0] Mode Description

00 0 Normal operation
01 1 Non-driving
10 2 Disable Bit Stuffing and

11 3 Reserved

Mode 0 allows the transceiver to operate with normal USB
data decoding and encoding.

Mode 1 allows the transceiver logic to support a soft
disconnect feature which three-states both the HS and FS
transmitters, and removes any termination from the USB,
making it appear t o an up stream port that th e device h as been
disconnected from the bus.

Mode 2 disables Bit Stuff and NRZI encoding logic so 1s
loaded from the dat a bus becomes Js on the DPLUS/DMINUS
lines and 0s become Ks.

NRZI encoding

modes.

4.0 DPLUS/DMINUS Impedance Termination

The CY7C68000 does not require external resistors for USB
data line i mpedanc e term inati on or an e xternal pul l up resistor
on the DPLUS line. These resistors are incorporated into the
part. They are factory trimmed to meet the requirements of
USB 2.0. Incorporating these resistors also reduces the pin
count on the part.

Document #: 38-08016 Rev. *H Page 2 of 14

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CY7C6800

5.0 Pin Assignments

The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin SSOP packages.
The packages offered use either an 8-bit (60-MHz) or 16-bit (30-MHz) bus interface.

56-pin QFN

DataBus16_8

TXReady

Suspend

Reset

AV

CC

XTALOUT

XTALIN

AGND

AV

CC

DPLUS

DMINUS

AGND

XcvrSelect

10
11
12

V

CC

55

TXValid

54

ValidH

56

1
2
3
4
5
6
7
8
9

GND

53

Uni_bidi

51

52

CY7C68000

56-pin QFN

CLK

50

D0

49

D1

48

Reserved

47

D2

46

V

CC

45

D3

44

D4

43

42
41
40
39
38
37
36
35
34
33
32
31

GND
D5
Reserved
D6
D7
D8
D9
Reserved
D10
D11
V

CC

D12

TermSelect

OpMode0

Document #: 38-08016 Rev. *H Page 3 of 14

13
14

25

24

23

22

21

20

19

18

17

16

15

Reserved

Reserved

RXError

RXActive

RXValid

GND

LineState1

LineState0

V

GND

OpMode1

CC

Figure 5-1. CY7C68000 56-pin QFN Pin Assignment

26

D15

27

D14

28

V

CC

30
29

GND
D13

0

56-pin SSOP

CY7C6800

1

CLK

2

DataBus16_8

3

Uni_Bidi

4

GND

5

TXValid

6

V

7

ValidH

8

TXReady

9

Suspend

10

Reset

11

AVCC

12

XTALOUT

13

XTALIN

14

AGND

15

AVCC
DPLUS

16

DMINUS

17

AGND

18

XcvrSelect

19

TermSelect

20
21

OpMode0

22

OpMode1

23

GND

24

V
LineState0

25

LineState1

26

GND

27

RXValid

28

56

D0

55

D1

V

GND

D10
D11
V

D12

GND

D13
V

D14
D15

54
53

D2

52

CC

51

D3

50

D4

49
48

D5

47
46

D6

45

D7

44

D8

43

D9

42
41

40
39

CC

38
37

36
35

CC

34
33

32
31

30
29

Reserved

CC

Reserved

Reserved

CC

Reserved
Reserved

RXError

RXActive

Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment

5.1 CY7C68000 Pin Descriptions

Table 5-1. Pin Descriptions

SSOP QFN Name Type Default Description

11 4 AVCC Power N/A Analog V
15 8 AVCC Power N/A Analog V
14 7 AGND Power N/A Analog Ground. Connect to ground with as short a path as possible.
18 11 AGND Power N/A Analog Ground. Connect to ground with as short a path as possible.
16 9 DPLUS I/O/Z Z USB DPLUS Signal. Connect to the USB DPLUS signal.
17 10 DMINUS I/O/Z Z USB DMINUS Signal. Connect to the USB DMINUS signal.

Note:

1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure
signals at power-up and in standby.

Document #: 38-08016 Rev. *H Page 4 of 14

[1]

. This signal provides power to the analog section of the chip.

CC

. This signal provides power to the analog section of the chip.

CC

0

CY7C6800

Table 5-1. Pin Descriptions (continued)

SSOP QFN Name Type Default Description

56 49 D0 I/O Bidirectional Data Bus. This bidirectional bus is used as the entire data
55 48 D1 I/O
53 46 D2 I/O
51 44 D3 I/O
50 43 D4 I/O
48 41 D5 I/O
46 39 D6 I/O
45 38 D7 I/O
44 37 D8 I/O Bidirectional Data Bus. This bidirectional bus is used as the upper eight
43 36 D9 I/O
41 34 D10 I/O
40 33 D11 I/O
38 31 D12 I/O
36 29 D13 I/O
34 27 D14 I/O
33 26 D15 I/O

1 50 CLK Output Clock. This output is used for clocki ng the receive and transmit paralle l data

10 3 Reset Input N/A Active HIGH Reset. Resets the entire chip. This pin can be tied to V

19 12 XcvrSelect Input N/A T ransceiver Select. This signal selects between the Full Speed (FS) and

20 13 TermSelect Input N/A Termination Select. This signal selects between the between the Full

9 2 Suspend Input N/A Suspend. Places the CY7C68000 in a mod e that draws minimal power from

26 19 LineState1 Output Line State. These signals reflect the current state of the single-ended

25 18 LineState0 Output Line State. These signals reflect the current state of the single-ended

[1]

bus in the 8-bit bi direction al mode or th e least sig nificant eig ht bits i n the 16­bit mode or under the 8-b it unidirectional mode these bits are us ed as inputs
for data, selected by the RxValid signal.

bits of the d ata bu s when i n the 16-bit m ode, and not use d when in the 8-bi t
bidirectional mode . Un der th e 8-b it un idir ectio nal mod e the se b its are used
as outputs for data, selected by the TxValid signal.

on the D[15:0] bus.

through a 0.1 μF capacitor and to GN D through a 100 K resistor for a 10
msec RC time constant.

the High Speed (HS) transceivers:
0: HS transceiver enabled
1: FS transceiver enabled

Speed (FS) and the High Speed (HS) terminations:
0: HS termination
1: FS termination

supplies. Shuts down all bloc ks not nec essary for Susp end/Resum e opera­tions. While susp ended, TermSelect must always be in FS mode to ensure
that the 1.5 K ohm pull-up on DPLUS remains powered.
0: CY7C68000 circuitry drawing suspend current
1: CY7C68000 circuitry drawing normal current

receivers. They are combi natorial until a “usable” CLK is available then they
are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
0 0 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1

receivers. They ar e combinatoria l until a ‘u sable’ CL K is available then they
are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
00–0: SE0
01–1: ‘J’ St ate
10–2: ‘K’ Sta t e
11–3: SE1.

CC

Document #: 38-08016 Rev. *H Page 5 of 14

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CY7C6800

Table 5-1. Pin Descriptions (continued)

SSOP QFN Name Type Default Description

22 15 OpMode1 Input Operational Mode. These signals select among various operational

21 14 OpMode0 Input Operational Mode. These signals select among various operational

5 54 TXValid Input T r ansmi t Valid. Indicat es that the dat a bus is va lid. The asse rtion of T ran s-

8 1 TXReady Output Transmit Data Ready. If TXValid is asserted, the SIE must always have

28 21 RXValid Output Receive Data Valid. Indicates that the DataOut bus has valid data. The

29 22 RXActive Output Receive Active. Indicates that the receive state machine has detected

30 23 RXError Output Receive Error.

7 56 ValidH I/O ValidH. This signal indicates that the high-order eight bits of a 16-bit data

[1]

modes:
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved.

modes:
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved.

mit V alid initiates S YNC on the USB. The negation of T ransmit V alid initi ates
EOP on the USB. The start of SYNC must be initiated on the USB no less
than one or no more that two CLKs after the assertion of TXValid.

In HS (XcvrSelect = 0) mode, the SYNC pattern must be asserted on the
USB between 8- and 16-bi t times aft er the assertio n of T XValid is detected
by the Transmit State Machine.

In FS (Xcvr = 1), the SYNC pattern must be asserted on the USB no less
than one or more than two CLKs after the assertion of TXValid is detected
by the Transmit State Machine.

data available fo r c loc ki ng in to the TX H o ldi ng R egi ste r on the rising edge
of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of
CLK, the CY7C68000 will load the data on the data bus into the TX Holding
Register on the next ri sing edge of CLK. At that time, the SIE should immedi­ately present the data for the next transfer on the data bus

Receive Data H oldin g Regi ster i s ful l and ready to be unlo aded. The SIE is
expected to latch the DataOut bus on the clock edge.

SYNC and is active.
RXActive is negated after a bit stuff error or an EOP is detected.

0 Indicates no error.
1 Indicates that a receive error has been detected.

word presented on the Data bus are valid. When DataBus16_8 = 1 and
TXValid = 0, ValidH is an output, indicating that the high-order receive data
byte on the Data bus is valid. When DataBus16_8 = 1 and TXValid = 1,
ValidH is an input and indicates that the high-order transmit data byte,
presented on the Data bus by the tr ansceiver , is valid. Whe n DataBus16_8
= 0, ValidH is undefined. The status of the receive low-order data byte is
determined by RXValid and are present on D0–D7.

.

2 51 DataBus16_8 Input Data Bus 16_8. Selects between 8- and 16-bit data transfers.

1–16-bit data path operation enabled. CLK = 30 MHz.
0–8-bit data pa th o pera tion enabled. When Uni_Bidi = 0, D[8:15] are unde­fined. When Uni_Bidi =1, D[0:7] are valid on RxValid and D[8:15] are valid
on TxValid. CLK = 60 MHz

Note: DataBus16_8 is static after Power-on Reset (PO R ) and is onl y sa m-
pled at the end of Reset.

Document #: 38-08016 Rev. *H Page 6 of 14

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CY7C6800

Table 5-1. Pin Descriptions (continued)

SSOP QFN Name Type Default Description

13 6 XTALIN Input N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant, funda-

12 5 XTALOUT Output N/A Crystal Output. Connect this signal to a 24-MHz parallel-resonant, funda-

3 52 Uni_Bidi Input Driving this pin HIGH enables the unidirectional mode when the 8-bit

655V
24 17 V
35 28 V
39 32 V
52 45 V

4 53 GND Ground N/A Ground.
23 16 GND Ground N/A Ground.
27 20 GND Ground N/A Ground.
37 30 GND Ground N/A Ground.
49 42 GND Ground N/A Ground.

CC
CC
CC
CC
CC

Power VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.

[1]

mental mode crystal and 20- pF capacitor to GND.
It is also correct to drive XTALIN with an external 24-MHz square wave

derived from another clock source.

mental mode crystal and 30-pF (nominal) capacitor to GND. If an external
clock is used to drive XTALIN, leave this pin open.

interface is selected. Uni_Bidi is static after power on reset (POR).

31 24 Reserved INPUT Connect pin to Ground.
54 47 Reserved INPUT Connect pin to Ground.
47 40 Reserved INPUT Connect pin to Ground.
42 35 Reserved INPUT Connect pin to Ground.
32 25 Reserved INPUT Connect pin to Ground.

Document #: 38-08016 Rev. *H Page 7 of 14

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CY7C6800

6.0 Absolute Maximum Ratings

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with Power Supplied......0°C to +70°C

Supply Voltage to Ground Potential...............–0.5V to +4.0V

DC Input Voltage to Any Input Pin .............................. 5.25 V

DC Voltage Applied to Outputs

in High-Z State .......................................–0.5V to V

CC

+ 0.5V

7.0 Operating Conditions

TA (Ambient Temperature Under Bias)............. 0°C to +70°C

Supply Voltage................................................+3.0V to +3.6V

Ground Voltage..................................................................0V

(Oscillator or Crystal Frequency)....24 MHz ± 100 ppm

F

OSC

...................................................................Parallel Resonant

Power Dissipation.....................................................630 mW

Static Discharge Voltage...........................................> 2000V

Max Output Current, per IO pin..................................... 4 mA

Max Output Current, all 21–IO pins ............................84 mA

8.0 DC Characteristics

Table 8-1. DC Characteristics

Parameter Description Conditions Min. Typ. Max. Unit

V

CC

V

IH

V

IL

I

I

V

OH

V

OL

I

OH

I

OL

C

IN

C

LOAD

I

SUSP

I

CC

I

CC

t

RESET

Supply Voltage 3.0 3.3 3.6 V
Input High Voltage 2 5.25 V
Input Low Voltage –0.5 0.8 V
Input Leakage Current 0< VIN < V
Output Voltage High I
Output Low Voltage I

= 4 mA 2.4 V

OUT

= –4 mA 0.4 V

OUT

CC

±10 μA

Output Current High 4mA
Output Current Low 4mA
Input Pin Capacitance Except DPLUS/DMINUS/CLK 10 pF

DPLUS/DMINUS/CLK 15 pF
Maximum Output Capacitance Output pins 30 pF
Suspend Current Connected

Disconnected

[2]

[2]

235 293 μA

15 55 μA
Supply Current HS Mode Normal operation OPMOD[1:0] = 00 175 mA
Supply Current FS Mode Normal operation OPMOD[1:0] = 00 90 mA
Minimum Reset ti me 1.9 ms

8.1 USB 2.0 Transceiver

USB 2.0 compliant in FS and HS modes.

Note:

2. Connected to the USB includes 1.5k-ohm internal pull-up. Disconnected has the 1.5k-ohm internal pull-up excluded.

Document #: 38-08016 Rev. *H Page 8 of 14

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9.0 AC Electrical Characteristics

9.1 USB 2.0 Transceiver

USB 2.0 certified in FS and HS.

9.2 Timing Diagram

9.2.1 HS/FS Interface Timing–60 MHz

CLK

TCSU_MIN

Control_In

TDSU_MIN

DataIn

Control_Out

DataOut

Figure 9-1. 60-MHz Interface Timing Constraints

CY7C6800

TCH_MIN

TDH_MIN

TCCO

TCDO

Table 9-1. 60-MHz Interface Timing Constraints Parameters

Parameter Description Min. Typ. Max. Unit Notes

T

CSU_MIN

T

CH_MIN

T

DSU_MIN

T

DH_MIN

T

CCO

T

CDO

Minimum set-up time for TXValid 8 ns
Minimum hold time for TXValid 1 ns
Minimum set-up time for Data (transmit direction) 8 ns
Minimum hold time for Data (transmit direction) 1 ns
Clock to Control out time for TXReady, RXValid,

18ns

RXActive and RXError
Clock to Data out time (Receive direction) 1 8 ns

Document #: 38-08016 Rev. *H Page 9 of 14

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CY7C6800

9.2.2 HS/FS Interface Timing–30 MHz

CLK

TCSU_MIN

Control_In

TDSU_MIN

DataIn

Control_Out

DataOut

TVSU_MIN

Figure 9-2. 30-MHz Timing Interface Timing Constraints

Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters

Parameter Description Min. Typ. Max. Unit Notes

T

CSU_MIN

T

CH_MIN

T

DSU_MIN

T

DH_MIN

T

CCO

T

CDO

T

VSU_MIN

T

VH_MIN

T

CVO

Minimum set-up time for TXValid 20 ns
Minimum hold time for TXValid 1 ns
Minimum set-up time for Data (Transmit direction) 20 ns
Minimum hold ti me for Data (Transmit direction) 1 ns
Clock to Control Out time for TXReady, RXValid,

RXActive and RXError
Clock to Data out time (Receive direction) 1 20 ns
Minimum set-up time for ValidH (transmit Direction) 20 ns
Minimum hold time for ValidH (Transmit direction) 1 ns
Clock to ValidH out time (Receive direction) 1 20 ns

TCH_MIN

TDH_MIN

TVH_MIN

TCDO
TCCO
TCVO

120ns

Document #: 38-08016 Rev. *H Page 10 of 14

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10.0 Ordering Information

Table 10-1. Ordering Information

Ordering Code Package Type

CY7C68000-56LFXC 56 QFN (Pb-Free)
CY7C68000-56LFXCT 56 QFN (Pb-Free) Tap/Reel
CY7C68000-56PVC 56 SSOP
CY7C68000-56PVCT 56 SSOP Tape/Reel
CY7C68000-56PVXC 56 SSOP (Pb-Free)
CY7C68000-56PVXCT 56 SSOP (Pb-Free) Tape/Reel
CY3683 EZ-USB TX2 Development Board

11.0 Package Diagrams

The TX2 is available in two packages:

• 56-pin SSOP

• 56-pin QFN.

CY7C6800

51-85062-*C

Figure 11-1. 56-lead Shrunk Small Outline Package O56

Document #: 38-08016 Rev. *H P age 11 of 14

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DIMENSIONS IN MM[INCHES] MIN.

REFERENCE JEDEC MO-220

TOP VIEW

56-Lead QFN 8 x 8 mm (Sawn Version) LS56B

MAX.

SIDE VIEW

CY7C6800

BOTTOM VIEW

0.20[0.008] REF.

0.04[0.0015] MAX.

SEATING
PLANE

C0.08[0.003]

0.30[0.012]

0.50[0.020]

0.18[0.007]

0.28[0.011]

E-PAD

(PAD SIZE VARY

BY DEVICE TYPE)

6.45[0.254]

6.55[0.258]

0.50[0.020]

PIN #1

CORNER

6.45[0.254]

51-85187-*A

6.55[0.258]

A

PIN #1

CORNER

E-PAD maximum size

4.75 X 5.46 mm [187 x 215 mils] (width x length).

7.90[0.311]

8.10[0.319]

1.00[0.039] MAX.

7.90[0.311]

8.10[0.319]

C

Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 x 8 mm) (SAWN VERSION)

12.0 PCB Layout Recommendations

The following recommendations should be follow ed to e ns ure
reliable high-performance operation.

• At least a four-layer impedance controlled boards are
required to maintain signal quality.

• Specify impedance targets (ask your board vendor what
they can achieve).

• To control impedance, maintain trace widths and trace
spacing to within specifications.

• Minimize stubs to minimize reflected signals.

• Connection s bet ween the USB co nn ect or she ll and signal
ground must be done near the USB connector.

Note:

3. Source for recommendations: EZ-USB FX2™ PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf High­Speed USB Platform Design Guidelines, http://www.usb.org/developers/do cs/h s_us b_p dg_r1_0.pdf.

[3]

• Bypass/flyba ck capacitors on VBus, near the c onnector, are
recommended.

• DPLUS and DMIN US trace lengths sho uld be kept to withi n
2 mm of each other in le ngth, with preferred leng th of 20–30
mm.

• Maintain a solid ground plane under the DPLUS and
DMINUS traces. Do not allow the plane to be split under
these traces.

• If possible, do not place any vias on the DP LUS or DMINUS
trace routing.

• Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.

Document #: 38-08016 Rev. *H Page 12 of 14

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CY7C6800

13.0 Quad Flat Package No Leads (QFN) Package Design Notes

Electrical contact of the p art to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. H ence, special atten tion is required to th e
heat transfer area below the package to provide a good ther­mal bond to the circuit board. A Copper (Cu) fill is to be de­signed into the PCB a s a thermal p ad under the p ackage. Heat
is transferred from the TX2 through the device’s metal paddle
on the bottom s ide of the package. H eat from here, is conduc t­ed to the PCB at the ther mal pad. I t is then conduc ted from the
thermal pad to th e PC B inn er grou nd pla ne by an array of via.
A via is a plated through hole in the PCB wi th a fini shed d iam­eter of 13 mil. The QFN’s metal die paddle must be soldered
to the PCB’s therm al p ad. Sol der mask is pla ced on the board
top side over each via to resist solder flow into the via. The

Solder Mask

Cu Fill

PCB Material

Via hole for thermally connecting the
QFN to the circuit board ground plane.

Figure 13-1. Crosssection of the Area Underneath the QFN Package

mask on the top side also minimizes outgassing during the
solder reflow process.

For further information on this package design please refer to
the application note “Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) Technology.” This application note
can be downloaded from AMKOR’ s web site from the followin g
URL http://www.amkor.com/products/notes_papers/MLFApp
Note.pdf. The application note provides detailed information
on board mounting guidelin es, sold ering flo w , re work proce ss,
etc.

Figure 13-1 below di splays a cross-se ctional are a undernea th
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. Cypre ss reco mm ends that ’No Clean’, type 3
solder paste is us ed for mo unting the part. Nit rogen pur ge is
recommended during reflow.

0.017” dia

Cu Fill

0.013” dia

This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane

PCB Material

Figure 13-2 is a plot of the solder mask pattern image of the assembly (darker areas indicate solder).

Figure 13-2. Plot of the Solder Mask (White Area)

EZ-USB TX2 is a trade mark of Cypress Semiconductor C orporation. All pro duct and comp any names me ntioned in this document
are the trademarks of their respective hold ers.

Document #: 38-08016 Rev. *H Page 13 of 14

© Cypress Semiconductor Corporation, 2006. The informat i on cont ained her ein i s subject to change with out notice. Cy pr ess Semiconducto r Corporation assum es no respo nsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C6800

Document History Page

Document Title: CY7C680 00 TX2™ USB 2.0 U TMI Transceiver
Document Number: 38-08016

REV. ECN NO. Issue Date

** 112019 03/01/02 KKU New data sheet

*A 113885 07/01/02 KKU Updated pinouts on BGA package, signal names.

*B 118521 11/18/02 KKU/

*C 124507 02/21/03 BHA Changed ISB Suspend Current maximums.
*D 126665 07/03/03 KKU Removed BGA p ackage and added Rev C of QF N package drawing w ith PCB

*E 285634 SEE ECN KKU Updated description on signals DataBus16_8, and D0-D15.

*F 301832 SEE ECN KKU Removed Preliminary and c hanged blo ck diagram on input to Digit al Tx block;

*G 375694 SEE ECN KKU Added note to figure 11-2:

*H 448451 SEE ECN TEH Updated Ordering information to include Pb-Free part numbers.

Orig. of

Change Description of Change

Added timing diagrams.

BHA

Added USB Logo.
Updated characterization data.
Changed from Preliminary to Final.

layout Recommendations for the QFN package.

Updated data sheet format.

was “UTMI Rx Data 8/16” changed to “UTMI Tx Data 8/16”

E-PAD maximum size 4.75 X 5.46 mm [187 x 215 mils] (width x length).

Document #: 38-08016 Rev. *H Page 14 of 14