Datasheet CY7C68000 Datasheet (CYPRESS)

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CY7C68000

CY7C6800

TX2™ USB 2.0 UTMI Transceiver

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-08016 Rev. *D Revised June 23, 2003

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TABLE OF CONTENTS

1.0 EZ-USB TX2 FEATURES ............................................. .. .. .. ............................. .. ..............................4

2.0 APPLICATIONS ...............................................................................................................................5

3.0 FUNCTIONAL OVERVIEW ........................................... .. .. .... .. ...................................... .. .................5

3.1 USB Signaling Speed .......................................................................................... .. .....................5

3.2 Transceiver Clock Frequency ......... .................................... ........................................................5

3.3 Buses ..........................................................................................................................................5

3.4 Reset Pin ....................................................................................................................................5

3.5 Line State ....................................................................................................................................5

3.6 Full-speed vs. High-speed Select .............. ............................................ .....................................5

3.7 Operational Modes ........... .................. ................... .................................. ................... .................5

4.0 DPLUS/DMINUS IMPEDANCE TERMINATION ..............................................................................6

5.0 PIN ASSIGNMENTS ............................................................................... .........................................6

5.1 CY7C68000 Pin Descriptions .................................... .................................................................7

6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................12

7.0 OPERATING CONDITIONS ............................... ........................ .............................................. ......12

8.0 DC CHARACTERISTICS ........................ .. .. .. .. .. ................................. ............................................12

8.1 USB 2.0 Transceiver .................................................................................................................13

CY7C6800

9.0 AC ELECTRICAL CHARACTERISTICS ..................................... .. ...................... .. ...................... ..13

9.1 USB 2.0 Transceiver .................................................................................................................13

9.2 Timing Dia g ra m .......... .. .............. .. .. ............. ... ............. .. .. ............. ... ............. .. .............. .............13

9.2.1 HS/FS Interface Timing–60 MHz ..................................................................................................13

9.2.2 HS/FS Interface Timing–30 MHz ....................................................................................................13

10.0 ORDERING INFORMATION ................................ .. .. .. ..................................................................14

11.0 PACKAGE DIAGRAMS ..................................... .. .... .. ...................................... .... ........................14

12.0 PCB LAYOUT RECOMMENDATIONS............... .. .... .. ................................ .. .... .. .. ........................15

13.0 QUAD FLAT PACKAGE NO LEADS (QFN) PACKAGE DESIGN NOTES .................. .. .............16

Document #: 38-08016 Rev. *D Page 2 of 17

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LIST OF FIGURES

Figure 1-1. Blo c k Di a gr a m .......................... .. ... ............. .. ............. .. ........................... .. .............................4

Figure 5-1. CY7C68000 56-pin QFN Pin Assignment.............................................................................7

Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment...........................................................................8

Figure 9-1. 60 -M Hz Interface Timing Constra i n t s........... ............. .. ... ............. .. ............. ... ............. .. .......13

Figure 9-2. 30 -M Hz Timing Int e rf ac e T im in g C o n straints... ... ............. .. ............. ... ............. .. ............. .. ... 13

Figure 11-1. 56-lead Shrunk Small Outline Package O56.....................................................................14

Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 x 8 mm) LF56.............................................15

Figure 13-1. Cross-Section of the area underneath the QFN package.................................................16

Figure 13-2. P lo t of th e so l de r m as k........... .. .............. .. .. ............. .. .............. .. .. ............. ... ......................16

LIST OF TABLES

CY7C6800

Table 5-1. Table 8-1.

Table 9-1. 60-MHz Interface Timing Constraints Parameters ..............................................................13

Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters ...................................................13

Table 10-1. Ordering Info rm a t io n .................... .. ............. .. ........................... .. ............. .. .............. .. .. .......14

Pin Descriptions ...................... ......... ...... ......... ......... ......... ...... ......... ......... ....... ......... ........ .....8

DC Characteristics ...............................................................................................................12

Document #: 38-08016 Rev. *D Page 3 of 17

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CY7C6800 0

CY7C6800

1.0 EZ-USB TX2 Features

The Cypress EZ-USB TX2 i s a Universal Serial Bus (USB) specificatio n revision 2.0 trans ceiver , serial /deserializ er , to a paralle l interface of eit her 16 bi ts at 30 MHz or eight bits at 60 MHz. T he TX2 pro vides a high-sp eed physi cal layer interface that ope rates at the maximum allowable USB 2.0 bandwidth. This allows the system designer to keep the complex high-speed analog USB components ex ternal to the di gital ASIC whi ch decr eases d evelopment time and a ssociated risk. A stand ard interfac e is p rovided that is USB 2.0-certified and is compliant with Transceiver Macrocell Interface (UTMI) specification version 1.05 dated 3/29/01.

Two packages are defined for the family: 56-pin SSOP and 56-pin QFN. The function block diagram is shown in Figure 1-1.

CY7C68000

XTALIN/

OUT

USB

OSC

USB

2.0

XCVR

20X PLL

Full-Speed Rx

High-Speed Rx

High-Speed Tx

PLL_480

Traffic

Sync

Elasticity

Buffer

Fast

Digital

Fast

UTMI CLK

Digital

Full-Speed Tx

Digital

Figure 1-1. Block Diagram

• UTMI-compliant/USB-2.0-certified for device operation

• Operates in both USB 2.0 high speed (HS), 480 Mbits/second, and full speed (FS), 12 Mbits/second

• Serial-to-parallel and parallel-to-serial conversions

• 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional external data interface

• Synchronous field and EOP detection on receive packets

• Synchronous field and EOP generation on transmit packets

• Data and clock recovery from the USB serial stream

• Bit stuffing/unstuffing; bit stuff error detection

• Staging register to manage data rate variation due to bit stuffing/unstuffing

• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface

• Ability to switch between FS and HS terminations and signaling

• Supports detection of USB reset, suspend, and resume

• Supports HS identification and detection as defined by the USB 2.0 Specification

• Supports transmission of resume signaling

• 3.3V operation

• Two package options—56-pin QFN, and 56-pin SSOP

• All required terminations, including 1.5-K ohm pull-up on DPLUS, are internal to chip

• Supports USB 2.0 test modes.

UTMI CLK

UTMI Rx Ctl

UTMI Rx Data 8/16

BIDI Option

Also

UTMI Rx Data 8/16

UTMI Tx Ctl

Document #: 38-08016 Rev. *D Page 4 of 17

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CY7C6800

2.0 Applications

• DSL modems

• ATA interface

• Memory card readers

• Legacy conversion devices

• Cameras

• Scanners

•Home PNA

• Wireless LAN

• MP3 players

• Networking.

3.0 Functional Overview

3.1 USB Signaling Speed

TX2 operates at two of the rates defined in the USB Specification 2.0, dated April 27, 2000:

• Full speed, with a signaling bit rate of 12 Mbps

• High speed, with a signaling bit rate of 480 Mbps.

TX2 does not support the low-speed (LS) signaling rate of 1.5 Mbps.

3.2 Transceiver Clock Frequency

TX2 has an on-chip oscillator circuit that uses an external 24-MHz (±100-ppm) crystal with the following characteristics:

• Parallel resonant

• Fundamental mode

• 500-µW drive level

• 27–33 pF (5% tolerance) load capacitors.

An on-chip phase-lock ed loop (PLL) m ultiplies the 24- MHz oscilla tor up to 30/60 M Hz, as required by the trans ceiver paral lel data bus. The default UTMI interface clock (CLK) frequency is determined by the DataBus16_8 pin.

3.3 Buses

The two packages allow for 8/16-bit bidirectional data bus for data transfers to a controlling unit.

3.4 Reset Pin

An input pin (Rese t) reset s t he ch ip. This pin ha s hyst eres is and is a ctive HIGH ac cordi ng to the U TMI s pecifica tion. T he internal PLL stabilizes approximately 200 µs after V

has reached 3.3V.

3.5 Line State

The Line State output pins LineState[1:0] are driven by combinational logic and may be toggling between the “J” and the “K” states. They are synchronized to the CLK signal for a valid signal. On the CLK edge the state of these lines reflect the state of the USB data lines. Upon the clock edg e the 0-bit of the Li neS tat e pins is the s tate of the DP LUS line and the one bit of LineState is the DMINUS line. When synchronized, the set-up and hold timing of the LineState is identical to the parallel data bus.

3.6 Full-speed vs. High-speed Select

The FS vs. HS is done through the u se of bot h Xcv rSel ec t and the TermSelect input signals . The TermSelect signal enables th e

1.5 K ohm pull-up on to the DPLUS pin. When TermSelect is driven LOW, a SE0 is asserted on the USB providing the HS termination and generating the HS Idle state on the bus. The XcvrSelect signal is the control which selects either the FS transceivers or the HS transceive rs. By sett ing this pin to a “0” the HS tran sc ei vers are s ele ct ed an d by setti ng this bit to a “1 ” the FS transceiver s are selected.

3.7 Operational Modes

The operational modes are controlled by the OpMode signals. The OpMode signals are c apabl e of inhi biti ng n orm al op erat ion of the transceiver an d evo king s pecial test modes. These mo des t ake ef fect im medi ately and t a ke prec edenc e ove r any pen ding data operations. The transmission data rate when in OpMode depends on the state of the XcvrSelect input.

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OpMode[1:0] Mode Description

00 0 Normal operation 01 1 Non-driving 10 2 Disable Bit Stuffing and NRZI encoding 11 3 Reserved

Mode 0 allows the transceiver to operate with normal USB data decoding and encoding. Mode 1 allows the transc eive r logic to su pport a soft d isconne ct feat ure which t hree-states both the HS and F S transm itters , an d

removes any t ermination from the USB, making it appear to an upstream port that the device has been disconnected from the bus. Mode 2 disables Bit Stuff and NRZI encoding logic so 1s loaded from the data bus becomes Js on the DPLUS/DMINUS lines

and 0s become Ks.

CY7C6800

4.0 DPLUS/DMINUS Impedance Termination

The CY7C68000 does not require external resistors for USB data line impedance termination or an external pull up resistor on the DPLUS line. These resistors are incorporated into the part. They are factory trimmed to meet the requirements of USB 2.0. Incorporating these resistors also reduces the pin count on the part.

Document #: 38-08016 Rev. *D Page 6 of 17

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CY7C6800

5.0 Pin Assignments

The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin SSOP packages. The packages offered use either an 8-bit (60-MHz) or 16-bit (30-MHz) bus interface.

56-pin QFN

DataBus16_8

TXReady

Suspend

Reset

XTALOUT

XTALIN

AGND

DPLUS

DMINUS

AGND

XcvrSelect

10 11 12

TXValid

ValidH

1 2 3 4 5 6 7 8 9

GND

Uni_bidi

CY7C68000

56-pin QFN

CLK

Reserved

42 41 40 39 38 37 36 35 34 33 32 31

GND D5 Reserved D6 D7 D8 D9 Reserved D10 D11 V

D12

TermSelect

OpMode0

13 14

Reserved

RXError

RXActive

RXValid

GND

LineState1

LineState0

GND

OpMode1

Figure 5-1. CY7C68000 56-pin QFN Pin Assignment

D15

D14

30 29

GND D13

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56-pin SSOP

CY7C6800

1 2

3 4

5 6

7 8

10 11

13 14

16 17

19 20

21 22

23 24

25 26

27 28

CLK DataBus16_8

Uni_Bidi GND

TXValid V

ValidH TXReady

Suspend Reset

AVCC XTALOUT

XTALIN AGND

AVCC DPLUS

DMINUS AGND

XcvrSelect TermSelect

OpMode0 OpMode1

GND V

LineState0 LineState1

GND RXValid

Reserved

GND

Reserved

D10 D11 V

D12

GND

D13 V

D14

D15 Reserved Reserved

RXError

RXActive

54 53

49 48

47 46

42 41

40 39

38 37

36 35

34 33

32 31

30 29

Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment

5.1 CY7C68000 Pin Descript ion s

Table 5-1. Pin Descriptions

SSOP QFN Name Type Default Description

11 4 AVCC Power N/A Analog V 15 8 AVCC Power N/A Analog V 14 7 AGND Power N/A Analog Ground. Connect to ground with as short a path as possible. 18 11 AGND Power N/A Analog Ground. Connect to ground with as short a path as possible. 16 9 DPLUS I/O/Z Z USB DPLUS Signal. Connect to the USB DPLUS signal. 17 10 DMINUS I/O/Z Z USB DMINUS Signal. Connect to the USB DMINUS signal.

Note:

1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled u p o r dow n to en sur e signals at power-up and in standby.

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. This signal p rov id es po we r to th e a nalog section of the chip.

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CY7C6800

Table 5-1. Pin Descriptions (continued)

SSOP QFN Name Type Default Description

56 49 D0 I/O Bidirectional Data Bus. This bidirectional bus is used as the entire data 55 48 D1 I/O 53 46 D2 I/O 51 44 D3 I/O 50 43 D4 I/O 48 41 D5 I/O 46 39 D6 I/O 45 38 D7 I/O 44 37 D8 I/O Bidirectional Data Bus. This bidirectional bus is used as the upper eight 43 36 D9 I/O 41 34 D10 I/O 40 33 D11 I/O 38 31 D12 I/O 36 29 D13 I/O 34 27 D14 I/O 33 26 D15 I/O

1 50 CLK Output Clock. This output is used for cloc king the receive and transmit pa rallel data

10 3 Reset Input N/A Active HIGH Reset. Resets the entire chip. This pin can be tied to V

19 12 XcvrSelect Input N/A Transceiver Select. This sig nal sel ects between the Full Speed (F S) and

20 13 TermSelect Input N/A Termination Select. This signal selects between the between the Full

9 2 Suspend Input N/A Suspend. Places the CY7C68000 in a mode that draws minimal power

26 19 LineState1 Output Line State. These signals reflect the current state of the single-ended

[1]

bus in the 8-bit mode or the least significant eight bits in the 16-bit mode.

bits of the data bus when in the 16-bit mode, and not used when in the 8bit mode.

on the D[15:0] bus.

through a 0.1-µF capacitor and to GND through a 100K resistor for a 10 msec RC time constant.

the High Speed (HS) transceivers: 0: HS transceiver enabled 1: FS transceiver enabled

Speed (FS) and the High Speed (HS) terminations: 0: HS termination 1: FS termination

from supplies. Shuts down all blocks not necessary for Suspend/Resume operations. While suspended, TermSelect must always be in FS mode to ensure that the 1.5 K ohm pull-up on DPLUS remains powered. 0: CY7C68000 circuitry drawing suspend current 1: CY7C68000 circuitry drawing normal current

receivers. They a re combinatorial until a “usable” CLK is availab le then they are synchronized to CLK. They directly reflect the current state of the DPLUS (LineS t ate0) and DMINUS (LineS tate1). D- D+ Description 0 0 0: SE0 0 1 1: ‘J’ State 1 0 2: ‘K’ State 1 1 3: SE1

Document #: 38-08016 Rev. *D Page 9 of 17

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CY7C6800

Table 5-1. Pin Descriptions (continued)

SSOP QFN Name Type Default Description

25 18 LineState0 Output Line State. These signals reflect the current state of the single-ended

22 15 OpMode1 Input Operational Mode. These signals select among various operational

21 14 OpMode0 Input Operational Mode. These signals select among various operational

554TXValid Input Transmit Valid. Indicates that the data bus is valid. The assertion of

8 1 TXReady Output Transmit Data Ready. If TXValid is asserted, the SIE must always have

28 21 RXValid Output Receive Data Valid. Indicates that the DataOut bus has valid data. The

29 22 RXActive Output Receive Active. Indicates that the receive state machine has detected

30 23 RXError Output Receive Error.

7 56 ValidH I/O ValidH. This signal indicates that the high-order eight bits of a 16-bit data

[1]

receivers. They a re combinatorial until a “usable” CLK is availab le then they are synchronized to CLK. They directly reflect the current state of the DPLUS (LineS t ate0) and DMINUS (LineS tate1). D- D+ Description 00–0: SE0 01–1: ‘J’ State 10–2: ‘K’ State 1 1– 3: SE1.

modes: 10 Description 00–0: Normal Operation 01–1: Non-driving 10–2: Disable Bit Stuffing and NRZI encoding 11–3: Reserved.

Transmit Valid initiates SYNC on the USB. The negation of Transmit Valid initiates EOP on the USB. The start of SYNC mu st be initiated on the USB no less than one or no more that two CLKs after the assertion of TXValid.

In HS (XcvrSelect = 0) mode, the SYNC pattern must be asserted on the USB between 8- and 16-b it times aft er the ass ertion of TXValid is detected by the Transmit State Machine.

In FS (Xcvr = 1), the SYNC pattern must be asserted on the USB no less than one or more than two CLKs aft er the asse rtion of TXValid is detected by the Transmit State Machine.

data availab le for clocki ng in to the T X Ho lding Regist er on the rising e dge of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of CLK, the CY7C68000 w ill load the dat a on the data bus in to the TX Holding Register on the ne xt rising edge of CLK. At that time, the SIE shou ld immediately present the data for the next transfer on the data bus

Receive Data Hol ding Register is fu ll and ready to be unl oaded. The SIE is expected to latch the DataOut bus on the clock edge .

SYNC and is active. RXActive is negated after a bit stuff error or an EOP is detected.

0 Indicate s no error. 1 Indicates that a receive error has been detected.

word presented on the Data bus are valid. When DataBus16_8 = 1 and TXValid = 0, ValidH is an output, indicating that the high-order re ceive data byte on the Data bus is valid. When DataBus16_8 = 1 and TXValid = 1, ValidH is an input and indicates that the high-order transmit data byte, presented on the Data bus by the transceiver , is valid. When DataBus16_8 = 0, ValidH is undefined. The status of the receive low-order data byte is determined by RXValid and are present on D0–D7.

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CY7C6800

Table 5-1. Pin Descriptions (continued)

SSOP QFN Name Type Default Description

2 51 DataBus16_8 Input Data Bus 16_8. Selects between 8- and 16-bit data transfers.

13 6 XTALIN Input N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant, funda-

12 5 XTALOUT Output N/A Crystal Output. Conne ct thi s s ig nal to a 24 -MH z parallel-resonant, fun da-

3 52 Uni_Bidi Input Driving this pin HIGH enables the unidir ection al mode w hen the 8-bit

655V 24 17 V 35 28 V 39 32 V 52 45 V

CC CC CC CC CC

Power VCC. Connect to 3.3V power source. Power N/A VCC. Connect to 3.3V power source. Power N/A VCC. Connect to 3.3V power source. Power N/A VCC. Connect to 3.3V power source. Power N/A VCC. Connect to 3.3V power source.

[1]

1–16-bit data path operation enabled. CLK = 30 MHz. 0–8-bit data path operation enabled. When Uni_Bidi = 0, D[8:15] are undefined. When Uni_ Bidi =1, D[0:7] are valid on RxValid and D[8:15] are valid on TxValid. CLK = 60 MHz

Note: DataBus16_8 is static after Power-on Reset (POR) and is only sampled at the end of Reset.

mental mode crystal and 20-pF capacitor to GND. It is also correct to drive XTALIN with an external 24-MHz square wave

derived fro m another clock source.

mental mode crys t al and 30-p F (no mi nal ) ca p ac ito r to G ND. If a n extern al clock is used to drive XTALIN, leave this pin open.

interface is selected. Uni_Bidi is static after power on reset (POR).

4 53 GND Ground N/A Ground. 23 16 GND Ground N/A Ground. 27 20 GND Ground N/A Ground. 37 30 GND Ground N/A Ground. 49 42 GND Ground N/A Ground.

31 24 Reserved INPUT Connect pin to Ground. 54 47 Reserved INPUT Connect pin to Ground. 47 40 Reserved INPUT Connect pin to Ground. 42 35 Reserved INPUT Connect pin to Ground. 32 25 Reserved INPUT Connect pin to Ground.

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CY7C6800

6.0 Absolute Maximum Ratings

Storage Temperature ............................................................ .......................................................... ..... ...... ...... ..–65°C to +150°C

Ambient Temperature with Power Supplied........................... ...................................................................................0°C to +70°C

Supply Voltage to Ground Potential....................................... ................................................................................–0.5V to +4.0V

DC Input Voltage to Any Input Pin......................................... ............................................................................................ 5.25 V

DC Voltage Applied to Outputs in High-Z State ..................... ....................................................................... –0.5V to V

+ 0.5V

Power Dissipation.................................................................. ...........................................................................................630 mW

Static Discharge Voltage........................................................ .................................................... ...................................... > 2000V

Max Output Current, per IO pin.............................................. .............................................................................................. 4 mA

Max Output Current, all 21–IO pins ...................................... ............................................................................................. 84 mA

7.0 Operating Conditions

TA (Ambient Temperature Under Bias) .................................. ...................................................................................0°C to +70°C

Supply Voltage....................................................................... ................................................................................+3.0V to +3.6V

Ground V oltage.................................................. ...... ..... ...... ................................. ..... ...... .......................................................... 0V

(Oscillator or Crystal Frequency)............................................................................................................24 MHz ± 100 ppm

OSC

............................................................................................... Parallel Resonant

8.0 DC Characteristics

Table 8-1. DC Characteristics

Parameter Description Conditions Min. Typ. Max. Unit

V V V I V V I I C

CC IH IL

OL OH OL

Supply Voltage 3.0 3.3 3.6 V Input High Voltage 2 5.25 V Input Low Voltage –0.5 0.8 V Input Leakage Current 0< VIN < V Output Voltage High I Output Low Voltage I

= 4 mA 2.4 V

OUT

= –4 mA 0.4 V

OUT

±10 µA

Output Current High 4mA Output Current Low 4mA Input Pin Capacitance Except DPLUS/DMINUS/CLK 10 pF

DPLUS/DMINUS/CLK 15 pF

LOAD

SUSP

RESET

Maximum Out put Capacitance Output pins 30 pF Suspend Current Connected

Disconnected

[2]

235 293 µA

15 55 µA Supply Current HS Mode Normal operation OPMOD[1:0] = 00 175 mA Supply Current FS Mode Normal operation OPMOD[1:0] = 00 90 mA Minimum Reset time 1.9 ms

8.1 USB 2.0 Transceiver

USB 2.0 certified in FS and HS modes.

Note:

2. Connected to the USB includes 1.5k ohm internal pull-up. Disconnected has the 1.5k-ohm internal pull-up excluded.

Document #: 38-08016 Rev. *D Page 12 of 17

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CY7C6800

9.0 AC Electrical Characteristics

9.1 USB 2.0 Transceiver

USB 2.0 certified in FS and HS.

9.2 Timing Diagram

9.2.1 HS/FS Interface Timing–60 MHz

CLK

TCSU_MIN

Control_In

TDSU_MIN

DataIn

Control_Out

DataOut

Figure 9-1. 60-MHz Interface Timing Constraints

Table 9-1. 60-MHz Interface Timing Constraints Parameters

Parameter Description Min. Typ. Max. Unit Notes

CSU_MIN

CH_MIN

DSU_MIN

DH_MIN

CCO

CDO

Minimum set-up time for TXValid 8 ns Minimum hold time for TXValid 1 ns Minimum set-up time for Data (transmit direction) 8 ns Minimum hold time for Data (transmit direction) 1 ns Clock to Control out time for TXReady, RXValid,

RXActive and RXError Clock to Data out time (Receive direction) 1 8 ns

TCH_MIN

TDH_MIN

TCCO

TDCO

18ns

9.2.2 HS/FS Interface Timing–30 MHz

CLK

TCSU_MIN

Control_In

TDSU_MIN

DataIn

Control_Out

TVSU_MIN

DataOut

TCH_MIN

TDH_MIN

TVH_MIN

TCDO

TCCO

TCVO

Figure 9-2. 30-MHz Timing Interface Timing Constraints

Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters

Parameter Description Min. Typ. Max. Unit Notes

CSU_MIN

CH_MIN

DSU_MIN

DH_MIN

Minimum set-up time for TXValid 20 ns Minimum hold time for TXValid 1 ns Minimum set-up time for Data (Transmit direction) 20 ns Minimum hold time for Data (Transmit direction) 1 ns

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Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters (continued)

Parameter Description Min. Typ. Max. Unit Notes

CCO

CDO

VSU_MIN

VH_MIN

CVO

Clock to Control Out time for TXReady, RXValid, RXActive and RXError

Clock to Data out time (Receive direction) 1 20 ns Minimum set-up time for ValidH (transmit Direction) 20 ns Minimum hold time for ValidH (Transmit direction 1 ns Clock to ValidH out time (Receive direction) 1 20 ns

120ns

CY7C6800

10.0 Ordering Information

Table 10-1. Ordering Information

Ordering Code Package Type

CY7C68000-56LFC 56 QFN CY7C68000-56PVC 56 SSOP CY7C68000-56PVCT 56 SSOP Tape/Reel CY3683 EZ-USB TX2 Development Board

11. 0 Package Diagrams

The TX2 is available in two packages:

• 56-pin SSOP

• 56-pin QFN.

56-lead Shrunk Small Outline Package O56

51-85062-*C

Figure 11-1. 56-lead Shrunk Small Outline Package O56

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CY7C6800

51-85187-**

Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 x 8 mm) (SAWN VERSION)

12.0 PCB Layout Recommendations

The following recommendations should be followed to ensure reliable high-performance operation.

• At least a four-layer impedance controlled boards are required to maintain signal quality.

• Specify impedance targets (ask your board vendor what they can achieve).

• To control impedance, maintain trace widths and trace spacing.

• Minimize stubs to minimize reflected signals.

• Connections between the USB connector shell and signal ground must be done near the USB connector.

• Bypass/flyback caps on VBus, near connector, are recommended.

• DPLUS and DMINUS trace len gth s s hou ld b e k ept to w it hin 2 m m o f eac h o the r in l eng th, w i th p refe rred l ength of 20–30mm.

• Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces.

• It is preferred is to have no vias placed on the DPLUS or DMINUS trace routing.

• Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.

Note:

3. Source for recommendations: EZ-USB FX2™ PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf HighSpeed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.

[3]

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CY7C6800

13.0 Quad Flat Package No Leads (QFN) Package Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circu it board. A Copper (Cu) fill is to be des igned into the PCB as a thermal pa d under the pack age. Heat is trans ferred from the TX2 through the device’s metal paddle on the bottom side of the package. Heat from here, is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by an array of via. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassi ng duri ng the so lder reflow process.

For further information on this package design please refer to the application note “Surface Mount Assembly of AMKOR’s MicroLeadFrame (MLF) Technology.” This application note can be downloaded from AMKOR’s web site from the following URL http://www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc.

Figure 13-1 below d ispla y a c ross-s ectio nal are a unde rneath the pa ckage . The c ross se ction is of only one v ia. The sold er pas te template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recomm ended tha t “No Clean”, type 3 s older pas te is u sed for moun ting the part. Nit rogen purg e is recomm ended d uring reflow.

0.017” dia

Solder Mask

Cu Fill

PCB Material

Via hole for thermally connecting the QFN to the circuit board ground plane.

0.013” dia

This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane

PCB Material

Figure 13-1. Crosssection of the Area Underneath the QFN Package

Figure 13-2 is a plot of the solder mask pattern image of the assembly (darker areas indicate solder).

Figure 13-2. Plot of the Solder Mask (White Area)

EZ-USB TX2 is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademark s of their respective holders.

Document #: 38-08016 Rev. *D Page 16 of 17

© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other ri ghts. Cypre ss Semiconductor does not autho rize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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CY7C6800

Document History Page

Document Title: CY7C68000 TX2™ USB 2.0 UTMI Transceiver Document Number: 38-08016

REV. ECN NO.

** 112019 03/01/02 KKU New data sheet

*A 1 1 388 5 07/01/02 KKU Updated pinouts on BGA package, signa l nam es .

*B 118521 11/18/02 KKU/

*C 124507 02/21/03 BHA Changed ISB Suspend Current maximums. *D 126665 07/03/03 KKU Removed BGA package and added Rev C of QFN package drawin g with PCB

Issue

Date

Orig. of

Change Description of Change

Added timing diagrams. Added USB Logo.

BHA

Updated characterization data. Changed from Preliminary to Final.

layout Recommendations for the QFN package.

Document #: 38-08016 Rev. *D Page 17 of 17

Datasheet CY7C68000 Datasheet (CYPRESS)

Specifications and Main Features

Frequently Asked Questions

User Manual