Datasheet CY7C65013, CY7C65113 Datasheet (CYPRESS)

CY7C6501

3
3

CY7C6511

USB Hub with Microcontroller

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-08002 Rev. *B Revised March 12, 2003

CY7C6501

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3

TABLE OF CONTENTS

1.0 FEATURES ............................................ .. .. .. .. .................................................................................6

2.0 FUNCTIONAL OVERVIEW .................... ........................ .................................................................7

3.0 PIN CONFIGURATIONS .............................. .. .. ................................. ..............................................9

4.0 PRODUCT SUMMARY TABLES .................................................. .. .. ...................................... .. .. ....9

4.1 Pin Assignm e n ts ...................... .. ............. .. ........................... .. ............. ... ............. .. .. ..................9

4.2 I/O Registe r S u m ma ry ......... .............. .. ............. .. ............. ... ............. .. ............. ... .. ....................10

4.3 Instruction S e t S u mm a r y ........... .. .. ............. ... ............. .. .. ............. ... ............. .. ............. ... .. . ........11

5.0 PROGRAMM I N G M OD E L .................. .. .............. .. .. ............. .. .............. .. ............. .. ... ............. .. .......12

5.1 14-bit Program Counter ............................... ..................... ...................................... .................12

5.1.1 Program Memory Organization ......................................................................................................13

5.2 8-bit Accumulator (A) ...............................................................................................................14

5.3 8-bit Tempo r a ry R e gister (X) ............... .. ............. .. .............. .. .. ............. ... ............. .. ..................14

5.4 8-bit Program Stack Pointer (PSP) ..........................................................................................14

5.4.1 Data Memory Organization ............................................................................................................14

5.5 8-bit Data Stack Pointer (DSP) ................................. .................... .................... .......................15

5.6 Address Modes .......... .. ......................... .. ..................................................... ............................15

5.6.1 Data (Immediate) ...........................................................................................................................15

5.6.2 Direct ..............................................................................................................................................15

5.6.3 Indexed ..........................................................................................................................................15

6.0 CLOCKING ....................................................................................................................................16

CY7C6511

7.0 RESET ...................................... .. .. ............................. .. ............................. .. ...................................16

7.1 Power-on Reset .......................................................................................................................16

7.2 Watchdog Reset ......................................................................................................................17

8.0 SUSPEND MODE .................................. ........................................ .. .. ............................................17

9.0 GENERAL-PURPOSE I/O PORTS .................................... .. .. .................................... .. .. .. .............18

9.1 GPIO Configuration Port ..........................................................................................................19

9.2 GPIO Interrupt Enable Ports ............................ ........................ ................................................20

10.0 12-BIT FREE-RUNNING TIMER ....................... .. .. ......................................................... .............21

11.0 I

12.0 I2C-COMP ATIBLE CONT R OL L E R ... ... ............. .. ............. .. ........................... .. ............. ... ...........22

13.0 PROCESSOR STATUS AND CONTROL REGISTER ...............................................................24

14.0 INTERRUPTS ....................................................................... ............................... ........................25

2

C CONFIGURATION REGISTER ............................................................................................22

14.1 Interrupt Vectors ....................................................................................................................27

14.2 Interrupt Latency ....................................................................................................................28

14.3 USB Bus Reset Interrupt ........................................................................................................28

14.4 Timer Interrupt .......................................................................................................................28

14.5 USB Endpoint Interrupts ........................................................................................................28

14.6 USB Hub Interrupt ..................................................................................................................28

14.7 GPIO Interrupt ........................................................................................................................29

14.8 I

2

C Interrupt ............................................................................................................................29

15.0 USB OVERVIEW .........................................................................................................................30

15.1 USB Serial Interface Engine (SIE) .........................................................................................30

15.2 USB Enumeration ..................................................................................................................30

Document #: 38-08002 Rev. *B Page 2 of 51

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TABLE OF CONTENTS (continued)

16.0 USB HUB ....................................................................................................................................31

16.1 Connecting/Disconnecting a USB Device .............................................................................. 31

16.2 Enabling/Disabling a USB Device ..........................................................................................32

16.3 Hub Downs tr e a m P or ts S ta t us a nd C o n tr o l ................... ... ............. .. ............. ... .. ............. .. .....32

16.4 Downstream Port Suspend and Resume .................. .. ............................................... ............34

16.5 USB Upstream Port Status and Control ............................................ .....................................35

17.0 USB SERIAL INTERFACE ENGINE OPERATION ....................................................................36

17.1 USB Device Addresses ..........................................................................................................36

17.2 USB Device Endpoints ...........................................................................................................37

17.3 USB Control Endpoint Mode Registers ..................................................................................37

17.4 USB Non-control Endpoint Mode Registers ........................................ ....................... .. ..........38

17.5 USB Endpoint Counter Registers .......................................................... ................................39

17.6 Endpoint Mode/Count Registers Update and Locking Mechanism ........................................39

18.0 USB MODE TABLES ..................................................................................................................41

19.0 REGISTER SUMMARY .............. .................................. .. .. .... .................................. .. .. .. .. .............45

20.0 SAMPLE SCHEMATIC ...............................................................................................................47

CY7C6511

21.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................47

22.0 ELECTRICAL CHARACTERISTICS ....................... .. ................................................................ ..48

23.0 SWITCHING CHARACTERISTICS

24.0 ORDERING INFORMATION .......................................................................................................49

25.0 PACKAGE DIAGRAMS ........................... .. ................................................................ .................49

(f

= 6.0 MHz) ..................................................................................... 48

OSC

Document #: 38-08002 Rev. *B Page 3 of 51

CY7C6501

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LIST OF FIGURES

Figure 5-1. Pro g ra m M e mory Space wit h In te rrupt Vector T ab le .............. ............. .. ............. .............. 13

Figure 6-1. Clo ck Os cillator On-Ch i p Cir cuit .. .. .. ............. .. .............. .. .......................... ... ............. .. .......16

Figure 7-1. Watchdog Reset (Address 0x26) ......................................................................................17

Figure 9-1. Blo ck Di a g ra m of a GPIO Pin ................. ............. .. .. ............. ... ............. .. .. .............. .. .........18

Figure 9-2. Por t 0 Dat a ..... .. ............. .. .............. .. .. ............. ... ............. .. .. .............. .. ............. ..................18

Figure 9-3. Por t1 Da ta ...... ............. .. .............. .. .. ............. .. .............. .. .. ............. ... ............. .. ..................18

Figure 9-4. Por t 2 Dat a ..... .. ............. .. .............. .. .. ............. ... ............. .. .. .............. .. ............. ..................18

Figure 9-6. GPIO C o n fig u r a tio n R e g is te r .... ... ............. .. .......................... ... ............. .. ............. ... .. .........19

Figure 9-5. Por t 3 Dat a ..... .. ............. .. .............. .. .. ............. ... ............. .. .. .............. .. ............. ..................19

Figure 9-7. Por t 0 Int e rr u p t E na b l e .... .............. .. ............. .. .............. .. .. ............. ... ............. .. ..................20

Figure 9-8. Por t 1 Int e rr u p t E na b l e .... .............. .. ............. .. .............. .. .. ............. ... ............. .. ..................20

Figure 10-1. Ti m e r L SB Re g is t e r .............. .. .............. .. .. ............. .. .............. .. .. ............. ... ......................21

Figure 10-2. Ti m e r MS B R egister .................... .. .. ............. ... ............. .. .. .............. .. ............. .. ................21

Figure 9-9. Por t 2 Int e rr u p t E na b l e .... .............. .. ............. .. .............. .. .. ............. ... ............. .. ..................21

Figure 9-10. Port 3 Interrupt Enable ....................................................................................................21

Figure 10-3. Ti m e r Bl o c k D ia g r a m .............. .............. .. .. ............. .. .............. .. .......................... ... ...........22

Figure 11-1. I
Figure 12-1. I
Figure 12-2. I

Figure 13-1. Processor Status and Control Register ...........................................................................24

Figure 14-1. Global Interrupt Enable Register .....................................................................................25

Figure 14-2. USB Endpoint Interrupt Enable Register .........................................................................26

Figure 14-3. Interrupt Controller Function Diagram .............................................................................27

Figure 14-4. GP IO In t er ru p t Structure ................. ............. ... ............. .. .. .............. .. ............. .. .. .............. 29

Figure 16-1. Hub Ports Connect Status ...............................................................................................31

Figure 16-2. Hub Ports Speed .............................................................................................................31

Figure 16-3. Hub Ports Enable Register ..............................................................................................32

Figure 16-4. Hub Downstrea m P o rts Control Re gi s te r .... . ... ............. .. ............. ... ............. .. ............. .. ... 33

Figure 16-5. Hub P o rt s F o rce Low Registe r .... .. ............. .. .............. .. .. ............. ... ............. .. .. ................33

Figure 16-6. Hub P o rt s F o rce Low Registe r .... .. ............. .. .............. .. .. ............. ... ............. .. .. ................33

Figure 16-7. Hub P o rts SE0 Status Re g i ster .................... ... ............. .. ............. ... ............. .. .. ................33

Figure 16-8. Hub P o rt s D a ta R e g is te r .......................... .. .. .............. .. ............. .. .............. .. .. ..................34

Figure 16-9. Hub Ports Suspend Register ...........................................................................................34

Figure 16-10 . Hub P o rts R e su me Status Reg ister ...................... .............. .. ............. .. .............. .. .........35

Figure 16-11. USB Status and Control Register ..................................................................................35

Figure 17-1. USB Device Address Registers .......................................................................................36

Figure 17-2. USB Device Endpoint Zero Mode Registers ...................................................................37

Figure 17-3. USB Non-control Device Endpoint Mode Registers ........................................................38

Figure 17-4. USB Endpoint Counter Registers ....................................................................................39

Figure 17-5. Token/Data Packet Flow Diagram ...................................................................................40

2

C Configuration Registe r ................. ... .. ............. .. ............. ... ............. .. ............. ... ...........22

2

C Data Regist e r .............. .. ............. .. .............. .. .. ............. .. .............. .. ............. .. .............. 23

2

C Status and Co n trol Register ................................. .. ............. .. ... ............. .. ............. .. ... 23

CY7C6511

Document #: 38-08002 Rev. *B Page 4 of 51

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LIST OF TABLES

Table 4-1. Pin Assignments ..................................................................... ..............................................9

Table 4-2. I/O Register Summary .............. ................................................. .......................... ...............10

Table 4-3. Instruction Set Summary ....................................................................................................11

Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarit y .............................................20

Table 11-1. I
Table 12-1. I

Table 14-1. Interrupt Vector Assignments ................. ...................... ...................... ..............................27

Table 16-1. Control Bit Definition for Downstream Ports ....................... ..............................................33

Table 16-2. Control Bit Definition for Upstream Port .................................. ...................... ...................36

Table 17-1. Memory Allocation for Endpoints ..................................... ...................... ..........................37

Table 18-1. USB Register Mode Encoding ......................... .................................................................41

Table 18-2. Decode table for Table 18-3: “Details of Modes for Differing Traffic Conditions” .............42

Table 18-3. Details of Modes for Differing Traffic Co nditions (see Table 18-2 for the decode legend) 43

2

C Port Configuration .......................................................................................................22

2

C Status and Control Register Bit Definitions ......................................... .................... ....23

CY7C6511

Document #: 38-08002 Rev. *B Page 5 of 51

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1.0 Features

• USB hub with an integrated microcontroller

• 8-bit USB optimized microcontroller
—Harvard arc hitecture

—6-MHz external clock source
—12-MHz internal CPU clock
—48-MHz internal hub clock

• Internal memory
—256 bytes of RAM

—8 KB of PROM

• Integrated Master/Slave I

•I/O ports
—Three GPIO ports (Port 0 to 2) capable of sinking 7 mA per pin (typical)

—An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs
—Higher current drive achievable by connecting multiple GPIO pins together to drive a common output
—Each GPIO port can be configured as input s with internal pull-ups or open drain output s or traditional CMOS outputs
—Maskable interrupts on all I/O pins

• 12-bit free-running timer with one microsecond clock ticks

• Watchdog timer (WDT)

• Internal Power-on Reset (POR)

• USB Specification compliance
—Conforms to USB Specification, Version 1.1

—Conforms to USB HID Specification, Version 1.1
—Supports one or two device addresses with up to 5 user-configured endpoints

Up to two 8-byte control endpoints
Up to four 8-byte data endpoints

Up to two 32-byte data endpoints
—Integrated USB transceivers
—Supports seven (CY7C65013) or four (CY7C65113) downstream USB ports
—GPIO pins can provide individual power control outputs for each downstream USB port
—GPIO pins can provide individual port over current inputs for each downstream USB port

• Improved output drivers to reduce electromagnetic interference (EMI)

• Operating voltage from 4.0V to 5.5V DC

• Operating temperature from 0° to 70° C

• CY7C65013 available in 48-pin PDIP (-PC) or 48-pin SSOP (-PVC) packages

• CY7C65113 available in 28-pin SOIC (-SC) or 28-pin PDIP (-PC) packages

• Industry-standard programmer support.

2

C-compatible Controller (100 kHz) enabled through General-purpose I/O (GPIO) pins

CY7C6511

Document #: 38-08002 Rev. *B Page 6 of 51

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2.0 Functional Overview

The CY7C65x13 device s are one-time pro grammable 8- bit microc ontrollers with a built- in 12-M bp s USB hu b t hat su pport s up to
seven downstream ports. The microcontroller instruction set has been optimized specifically for USB operations, although the
microcontrollers can be used for a variety of non-USB embedded applications.

GPIO

CY7C65013

The CY7C65013 featur es 22 GPIO pin s to support USB and other applicatio ns. The I/O p ins are grouped int o four port s (P0[7:0],
P1[7:4,2:0], P2[7:3], P3[1:0 ]) where eac h port can be co nfigured as inputs with internal pul l-ups, op en drain outpu ts, or tradi tional
CMOS outputs. Ports 0 to 2 are rated at 7 mA per pin (typical) sink current. Port 3 pins are rated at 12 mA per pin (typical) sink
current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more
drive current capa city. Additionally, ea ch I/O pin c an be u sed to genera te a GPI O inte rrupt to t he micr ocon troller. All of the GPIO
interrupts all share the same “GPIO” interrupt vector.

CY7C65113
The CY7C65113 has 11 GPIO pins (P0[7:0], P1[2:0]), both rated at 7 mA per pin (typical) sink current. Multiple GPIO pins can

be connected together to drive a single output for more drive current capacity.

Clock

The microcontroller us es an ex tern al 6 -MH z cry st a l an d an i nter nal oscillator to provide a referenc e to an inte rnal phase-locked
loop (PLL)-based clock generator. This technology allows the customer application to use an inexpensive 6-MHz fundamental
crystal that red uces the clock-related no ise emissions (EMI). A PLL cl ock generator provides the 6 -, 12-, and 48-MHz clock s ignals
for distribution within the microcontroller.

Memory

The CY7C65013 and the CY7C65113 are offered with 8 KB of PROM.

Power-on Reset, Watchdog, and Free-running Timer

These parts in clude power-o n reset logic , a Wa tchdog timer, and a 12-bit free-running timer. The PO R logic detect s when power
is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000. The
Watchdog timer is u sed to ensure the mi crocontrol ler rec overs afte r a perio d of ina ctivi ty. The firmware may become inactive for
a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs.

2

C

I

2

The microcontroller can communicate with external electronics through the GPIO pins. An I
dates a 100-kHz serial link with an external device.

Timer

The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-µs and 1.024-ms. The timer can be used to
measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is
complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of
the timer are lat ched into an internal regi ster when the firmware reads the lower e ight bits. A read from th e upper four bits actually
reads data from the inte rnal register , in stead of the ti mer . This featur e eliminates the ne ed for firmware to t ry to compensate if the
upper four bits increment immediately after the lower eight bits are read.

Interrupts

The microcontroller su ppo rts ten maskable interrupt s in the vectored interrupt contro lle r. Interrupt sources include the USB Bus
Reset interrupt, the 128-µs (bit 6 ) and 1.024-ms (bi t 9) outpu ts from the free -running ti mer, five USB end points, the USB h ub, the
GPIO ports, and the I
from LOW ‘0’ to HIGH ‘1’. Th e USB endpoi nts i nterrupt afte r the USB h ost has w ritten dat a to the endpoint FIFO or after the USB
controller sends a p ac ke t to th e U SB hos t. T he GPIO ports also hav e a le vel of masking to select w hic h GPI O inp uts can cause
a GPIO interrupt. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt
polarity can be rising edge (‘0’ to ‘1’) or falling edge (‘1’ to ‘0’).

USB

The CY7C65013 and CY7C65113 include an integrated USB Serial Interface Engine (SIE) that supports the integrated periph­erals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the
hub (two endpoint s) and a device address for a compoun d device (three end points). The SIE a llows the USB host to c ommunicate
with the hub and fu nctions integrated into the microcon troller . The CY7C651 13 p art includes a 1:4 hub repeater with one upstream
port and four downstream ports, while the CY 7C65013 part inclu des a 1:7 hub repeater . The USB Hub allows power management
control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the
downstream ports together with a single pair of power management pins, or providing power management for each port with four
(CY7C65113) or seven (CY7C65013) pairs of power management pins.

2

C-compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles

C-compatible interface ac commo-

CY7C6511

Document #: 38-08002 Rev. *B Page 7 of 51

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Logic Block Diagram

CY7C6511

6-MHz crystal

PLL

48 MHz

Clock

Divider

6 MHz

12 MHz

12-MHz

8-bit

CPU

PROM

8 KB

RAM

256 byte

12-bit
Timer

8-bit Bus

USB

SIE

Interrupt

Controller

GPIO

PORT 0

P0[0]

P0[7]

USB

Transceiver

Repeater

D+[0]

Upstream
USB Port

D–[0]

Downstream USB Ports

USB

Transceiver

USB

Transceiver

USB

Transceiver

USB

Transceiver

CY7C65013 only

Power management under firmware

control using GPIO pins

D+[1]
D–[1]

D+[4]
D–[4]

D+[5]
D–[5]

D+[7]
D–[7]

Watchdog

Timer

Power-on

Reset

GPIO

PORT 1

GPIO

PORT 2

GPIO

PORT 3

I2C comp.
Interface

2

*I

C-compatible interface enabled by firmware through

P2[1:0] or P1[1:0]

P1[0]

P1[2]

P2[7]

P2[3]

High Current

P3[1]

Outputs

P3[0]

CY7C65013 only

SCLK
SDATA

Document #: 38-08002 Rev. *B Page 8 of 51

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3.0 Pin Configurations

XTALOUT

XTALIN

48-pin SSOP

P1[1]
P1[5]
P1[7]
P3[1]
D+[0]

D–[0]

GND

D+[1]

D–[1]

V

REF

D+[2]

D–[2]

P2[3]

GND
P2[5]
D+[7]

D–[7]

P2[7]
P0[7]
P0[5]
P0[3]
P0[1]

CY7C65013

48

1
2

47
46

3
4

45

5

44
43

6

42

7

41

8
9

40
39

10
11

38
37

12
13

36
35

14

34

15
16

33

17

32
31

18
19

30
29

20
21

28

22

27

23

26
25

24

CY7C6501

Top View

CY7C65113

28-pin SOIC

V

CC

P1[0]
P1[2]
P1[4]
P1[6]
P3[0]
D–[3]
D+[3]

GND
D–[4]
D+[4]
V

REF

D–[5]
D+[5]
GND
P2[4]
D–[6]
D+[6]
P2[6]
V

PP

P0[0]
P0[2]
P0[4]
P0[6]

XTALOUT

XTALIN

V
GND

D+[0]

D–[0]

D+[1]

D–[1]

D+[2]

D–[2]

P0[7]
P0[5]
P0[3]
P0[1]

REF

1

28

V
2
3
4

5
6
7
8
9
10
11
12
13
14

CC

27

P1[1]

26

P1[0]

P1[2]

25

D–[3]

24

D+[3]

23

D–[4]

22

D+[4]

21

GND

20
19

V

PP

18

P0[0]

17

P0[2]

P0[4]

16
15

P0[6]

CY7C6511

4.0 Product Summary Tables

4.1 Pin Assignments

Table 4-1. Pin Assignments

Name I/O 48-pin 28-pin Description

D+[0], D–[0] I/O 7, 8 5, 6 Upstream port, USB differential data.
D+[1], D–[1] I/O 10, 11 7, 8 Downstream Port 1, USB differential data.
D+[2], D–[2] I/O 13, 14 9, 10 Downstream Port 2, USB differential data.
D+[3], D– [3] I/ O 41, 42 23, 24 Downstream Port 3, US B differential data.
D+[4], D– [4] I/ O 38, 39 21, 22 Downstream Port 4, US B differential data.
D+[5], D–[5] I/O 35, 36 Downstream Port 5, USB differential data.
D+[6], D–[6] I/O 31, 32 Downstream Port 6, USB differential data.
D+[7], D–[7] I/O 18, 19 Downstream Port 7, USB differential data.
P0 I/O P1[7:0]

21, 25, 22, 26, 23, 27,
24, 28

P1 I/O P1[7:4,2:0]

5, 44, 4, 45; 46, 3, 47

P2 I/O P2[7:3]

20, 30, 17,33, 15

P3 I/O P3[1:0]

6, 43

XTAL

IN

IN 2 2 6-MHz crystal or external clock input.

P1[7:0]
11, 15, 12, 16, 13,
17, 14, 18

P1[2:0]
25, 27, 26

GPIO Port 0 capable of sinking 7 mA (typical).

GPIO Port 1 capable of sinking 7 mA (typical).

GPIO Port 2 capable of sinking 12 mA (typical).

GPIO Port 3, capable of sinking 12 mA (typical).

Document #: 38-08002 Rev. *B Page 9 of 51

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Table 4-1. Pin Assignments (continued)

Name I/O 48-pin 28-pin Description

XTAL

OUT

V

PP

V

CC

GND 9, 16, 34, 40 4, 20 Ground.
V

REF

4.2 I/O Register Summary

I/O registers are accessed v ia the I/O Read (IORD) a nd I/O W rite (IOWR , IOWX) instructi ons. IORD reads data from the sel ected
port into the accumu lator . IOWR perform s the revers e; it wri tes dat a from the a ccumulator to the sel ected por t. Indexed I/O W rite
(IOWX) adds the co ntent s of X to t he add ress in th e ins tructio n to form the p ort add ress a nd wri tes da ta from th e acc umula tor t o
the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X.

All undefined registers are reserved. Do not write to reserved registers as this may cause an undefined operation or increased
current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with ‘0.’

Table 4-2. I/O Register Summary

Port 0 Data 0x00 R/W GPIO Port 0 Data 18
Port 1 Data 0x01 R/W GPIO Port 1 Data 17
Port 2 Data 0x02 R/W GPIO Port 2 Data 17
Port 3 Data 0x03 R/W GPIO Port 3 Data 19
Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 19
Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 19
Port 2 Interrupt Enable 0x06 W Interrupt Enable for Pins in Port 2 19
Port 3 Interrupt Enable 0x07 W Interrupt Enable for Pins in Port 3 19
GPIO Configuration 0x08 R/W GPIO Port Configurations 18

2

C Configuration 0x09 R/W I2C Position Configuration 20

I
USB Device Address A 0x10 R/W USB Device Address A 36
EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 Counter 38
EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 Configuration 37
EP A1 Counter Register 0x13 R/W USB Address A, Endpoint 1 Counter 38
EP A1 Mode Register 0x14 R/W USB Address A, Endpoint 1 Configuration 38
EP A2 Counter Register 0x15 R/W USB Address A, Endpoint 2 Counter 38
EP A2 Mode Register 0x16 R/W USB Address A, Endpoint 2 Configuration 38
USB Status & Control 0x1F R/W USB Upstream Port Traffic Status and Control 35
Global Interrupt Enable 0x20 R/W Global Interrupt Enable 25
Endpoint Interrupt Enable 0x21 R/W USB Endpoint Interrupt Enables 26
Interrupt Vector 0x23 R Pending Interrupt Vector Read/Clear 27
Timer (LSB) 0x24 R Lower Eight Bits of Free-running Timer (1 MHz) 20
Timer (MSB) 0x25 R Upper Four Bits of Free-running Timer 20
WDR Clear 0x26 W Watchdog Reset Clear 17

2

C Control & Sta tus 0x28 R/W I2C Status and Control 21

I

2

C Data 0x29 R/W I2C Data 23

I

OUT 1 1 6-MHz crystal out.

29 19 Programming voltage supply, tie to ground during normal

operation.

48 28 Voltage supply.

IN 12, 37 3 External 3.3V supply voltage for the down stream dif ferential

data output buffers and the D+ pull up.

Register Name I/O Address Read/Write Function Page

CY7C6511

Document #: 38-08002 Rev. *B Page 10 of 51

CY7C6501

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Table 4-2. I/O Register Summary (continued)

Register Name I/O Address Read/Write Function Page

Reserved 0x30 Reserved
Reserved 0x31 Reserved
Reserved 0x32 Reserved
Reserved 0x38-0x3F Reserved
USB Device Address B 0x40 R/W USB Device Address B (not used in 5-endpoint mod e) 36
EP B0 Counter Register 0x41 R/W USB Address B, Endpoint 0 Counter 38
EP B0 Mode Register 0x42 R/W USB Address B, Endpoint 0 Configuration, or

USB Address A, Endpoint 3 in 5-endpoint mode
EP B1 Counter Register 0x43 R/W USB Address B, Endpoint 1 Counter 38
EP B1 Mode Register 0x44 R/W USB Address B, Endpoint 1 Configuration, or

USB Address A, Endpoint 4 in 5-endpoint mode
Hub Port Connect Status 0x48 R/W Hub Downstream Port Connect Status 31
Hub Port Enable 0x49 R/W Hub Downstream Ports Enable 32
Hub Port Speed 0x4A R/W Hub Downstream Ports Speed 31
Hub Port Control (Ports [4:1]) 0x4B R/W Hub Downstream Ports Control (Ports [4:1]) 33
Hub Port Control (Ports [7:5]) 0x4C R/W Hub Downstream Ports Control (Ports [7:5]) 33
Hub Port Suspend 0x4D R/W Hub Downstream Port Suspend Control 34
Hub Port Resume Status 0x4E R Hub Downstream Ports Resume Status 35
Hub Ports SE0 Status 0x4F R Hub Downstream Ports SE0 Status 33
Hub Ports Data 0x50 R Hub Downstream Ports Differential Data 34
Hub Downstream Force Low 0x51 R/W Hub Downstream Ports Force LOW (Ports [1:4]) 33
Hub Downstream Force High 0x52 R/W Hub Downstream Ports Force HIGH (Ports [5:7]) 33
Processor Status & Control 0xFF R/W Microprocessor Status and Control Register 24

CY7C6511

37

38

4.3 Instruction Set Summary

Refer to the CYASM Assembler User’s Guide for more details. Note that conditional jump instructions (i.e. JC, JNC, JZ, JNZ)
take five cycles if jump is taken, four cycles if no jump.

Table 4-3. Instruction Set Summary

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles

HALT 00 7 NOP 20 4
ADD A,expr data 01 4 INC A acc 21 4
ADD A,[expr] direct 02 6 INC X x 22 4
ADD A,[X+expr] index 03 7 INC [expr] direct 23 7
ADC A,expr data 04 4 INC [X+expr] index 24 8
ADC A,[expr] direct 05 6 DEC A acc 2 5 4
ADC A,[X+expr] index 06 7 DEC X x 26 4
SUB A,expr data 07 4 DEC [expr] direct 27 7
SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8
SUB A,[X+expr] index 09 7 IORD expr address 29 5
SBB A,expr data 0A 4 IOWR expr address 2A 5
SBB A,[expr] direct 0B 6 POP A 2B 4
SBB A,[X+expr] index 0C 7 POP X 2C 4
OR A,expr data 0D 4 PUSH A 2D 5

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Table 4-3. Instruction Set Summary (continued)

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles

OR A,[expr] direct 0E 6 PUSH X 2E 5
OR A,[X+expr] index 0F 7 SWAP A,X 2F 5
AND A,expr data 10 4 SWAP A,DSP 30 5
AND A,[expr] direct 11 6 MOV [expr],A direct 31 5
AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6
XOR A,expr data 13 4 OR [ex pr],A direct 33 7
XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8
XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7
CMP A,expr data 16 5 AND [X+expr],A index 36 8
CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7
CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8
MOV A,expr data 19 4 IOWX [X+expr] index 39 6
MOV A,[expr] direct 1A 5 CPL 3A 4
MOV A,[X+expr] index 1B 6 ASL 3B 4
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[expr] direct 1D 5 RLC 3D 4
reserved 1E RRC 3E 4
XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50-5F 10 JC addr C0-CF 5 (or 4)
JMP addr 80-8F 5 JNC addr D0-DF 5 (or 4)
CALL addr 90-9F 10 JACC addr E0-EF 7
JZ addr A0-AF 5 (or 4) INDEX addr F0-FF 14
JNZ addr B0-BF 5 (or 4)

CY7C6511

5.0 Programming Model

5.1 14-bit Program Counter

The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C65x13 architecture. The top
32 bytes of the ROM in the 8K part are re serve d for testing purposes. The program c ounter is clea red during re set, su ch that the
first instruction e xecuted a fter a res et is a t addres s 0x0 000h. Typically, this is a jum p ins tructio n to a res et han dler tha t initializes
the application (see Interrupt Vectors on page 27).

The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the
program counter are increm ented by executing an XP AGE instructi on. As a result, the las t instruction exec uted within a 256-by te
“page” of sequen tial cod e should be an XPAGE instruction. The assemble r directive “XPAGEON” causes the as sembler to insert
XPAGE instructions au tomatical l y. Because instructions can be either one or two bytes lon g, the assembler may occasionally
need to insert a NOP followed by an XPAGE to execute correctly.

The address of the next ins truction to be execute d, the carry fl ag, and the zero fl ag are save d as two bytes on the progra m stack
during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the
program stack during a RETI instruction. Only the program counter is restored during a RET instruction.

The program counter ca nnot be accesse d direct ly by the firm ware . The progr am st ack can be exam ined by read in g SRAM from
location 0x00 and up.

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5.1.1 Program Memory Organization

after reset Address

14-bit PC 0x0000 Program execution begins here after a reset

0x0002 USB Bus Reset interrupt vector

0x0004 128-µs timer interrupt vector

0x0006 1.024-ms timer interrupt vector

0x0008 USB address A endpoint 0 interrupt vector

0x000A USB address A endpoint 1 interrupt vector

0x000C USB address A endpoint 2 interrupt vector

0x000E USB address B endpoint 0 interrupt vector

CY7C6501

CY7C6511

0x0010 USB address B endpoint 1 interrupt vector

0x0012 Hub interrupt vector

0x0014 Reserved

0x0016 GPIO interrupt vector

0x0018

0x001A Program Memory begi ns here

I2C interrupt vector

0x1FDF (8 KB -32) PROM ends here (CY7C65013, CY7C65113)

Figure 5-1. Program Memory Space with Interrupt Vector Table

Note that

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the upper 32 bytes of the 8K PROM are reserved. Therefore, user’s program must not overwrite this space.

CY7C6501

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5.2 8-bit Accumulator (A)

The accumulator is the general-purpose register for the microcontroller.

5.3 8-bit Temporary Register (X)

The “X” register is available to the firmware for temporary st orage of intermediate resul ts. The microcontroller can perform indexed
operations based on the value in X. Refer to Section 5.6.3 for additional information.

5.4 8-bit Program Stack Pointer (PSP)

During a reset, the Program Stack Pointer (PSP) is set to 0x00 and “grows” upward from this address. The PSP may be set by
firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and
RETI instructions under firmware control. The PSP is not readable by the firmware.

During an interrupt a ck nowl edge, interrupts are dis abl ed and the 14-bit program coun ter, carry flag, and zero flag are written as
two bytes of dat a memory . The first byte is stored in the me mory addresse d by the PSP, then the PSP is increm ented. The second
byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program
counter and flags on the program “stack” and increment the PSP by two.

The Return From Interr upt (RETI) instruc tion decrem ents the PSP, then restores the second byt e from memor y addressed by the
PSP . The PSP is decremented again and the first byte is restored from memory ad dressed by the PSP. After the program counter
and flags have b een rest ored from s tack, th e interrupt s are enab led. The o verall ef fect is t o restore the program counter and flags
from the program stack, decrement the PSP by two, and re-enable interrupts.

The Call Subroutine (CALL) instruction stor es the prog ram coun ter and fla gs on the prog ram st ac k and inc rem en t s the PSP by
two.

The Return From Subroutine (RET) instruction restores the program counter but not the flags from the program stack and
decrements the PSP by two.

CY7C6511

5.4.1 Data Memory Organization

The CY7C65x13 microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program
stack, user va riables, data s tack, and USB e ndpoint FIFOs. The following is one ex ample of where the program stack, dat a stack ,
and user variables areas could be located.

After reset Address

8-bit DSP 8-bit PSP 0x00 Program Stack Growth

(Move DSP

8-bit DSP

Notes:

1. Refer to Section 5.5 for a description of DSP.

2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7). See Table17-1.

[1]

)

user selected Data Stack Growth

User variables

USB FIFO space for up to tw o Address es and f ive endp oint s

0xFF

[2]

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5.5 8-bit Data Stack Pointer (DSP)

The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads
data from the memory location addressed by the DSP, then post-increments the DSP.

During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM
(address 0xFF). This writes dat a to the memory area res erved fo r USB en dp oin t FIFO s. There fore , the DSP shou ld b e ind ex ed
at an appropriate memory location that does not compromise the Program Stack, user-de fin ed me mory (variables), or the USB
endpoint FIFOs.

For USB applications , the firmware s hould set the DSP to an appropri ate location to avoid a mem ory conflict w ith RAM dedic ated
to USB FIFOs. The me mo ry requirements for the U SB en dpo ints are described in Sec t io n 1 7.2. Exa mp le as se mbl y ins truc ti ons
to do this with two device addresses (FIFOs begin at 0xD8) are shown below:

MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less)
SWAP A,DSP ; swap accumulator value into DSP register.

5.6 Address Modes

The CY7C65013 and CY 7C65113 microcontrollers support three addressin g modes for ins tructions that require da ta opera nds::
data, direct, and indexed.

5.6.1 Data (Immediate)

“Data” address m ode refers t o a data operand th at is actuall y a cons tant en coded in t he instruc tion. As an example, c onsider th e
instruction that loads A with the constant 0xD8:

• MOV A, 0D8h.

This instruction requires two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction is the constant “0xD8.” A constant may be referred to by name if a prior “EQU”
statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:

• DSPINIT: EQU 0D8h

• MOV A, DSPINIT.

CY7C6511

5.6.2 Direct

“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encode d in the instruction. As an example, consider an ins truction that loads A with the c onte nt s of memory address
location 0x10:

• MOV A, [10h].

Normally , varia ble names ar e assigned to va riable address es using “EQU” st atements to improve the re adability of th e assembler
source code. As an example, the following code is equivalent to the example shown above:

• buttons: EQU 10h

• MOV A, [buttons].

5.6.3 Indexed

“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constan t encoded in the instru ction and the con tents of the “X” register . Norma lly , the co nstant is th e “base” address
of an array of data and the X register contains an index that indicates which element of the array is actually addressed:

• array: EQU 10h

•MOV X, 3

• MOV A, [X+array].

This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10. The fourth
element would be at address 0x13.

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6.0 Clocking

XTALOUT

(pin 1)

CY7C6501

CY7C6511

XTALIN

(pin 2)

30 pF

Figure 6-1. Clock Oscillator On-Chip Circuit

The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to
these pins. When u si ng an ex ternal crystal, kee p PC B trac es b etw ee n t he ch ip leads and cryst al as s hort as p os si ble (l ess t han
2 cm). A 6-MHz fundament al frequency p arallel resonan t crystal can be c onnected to these p ins to provide a refe rence frequency
for the internal PLL. The two int ernal 30-pF lo ad caps app ear in series to the externa l cryst al and would be equivalen t to a 15-pF
load. Therefore, the crystal must have a required load capacitance of about 15–18 pF. A ceramic resonator does not allow the
microcontroller to meet the timing specifications of full speed USB and therefore a ceramic resonator is not recommended with
these parts.

An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Grounding the XTALOUT pin when
driving XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground.

To Internal PLL

30 pF

7.0 Reset

The CY7C65x13 supports two resets: POR and WDR. Each of these resets causes:

• all registers to be restored to their default states

• the USB device addresses to be set to 0

• all interrupts to be disabl ed

• the PSP and DSP to be set to memory address 0x00.

The occurrence of a reset is recorded in the Processor Status and Control Register, as described in Section. Bits 4 and 6 are
used to record the occurrence of POR and WDR respectively. Firmware can interrogate these bits to determine the cause of a
reset.

Program execution st arts at ROM address 0x000 0 af ter a re set . Although this looks like int errup t ve cto r 0, the re is an imp ort a n t
difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware
reset handler shou ld configure the hardw are before t he “main” loop of code. Attempting to execute a R ET or RETI in the firmw are
reset handler causes unpredictable execution results.

7.1 Power-on Reset

When VCC is first applied to the c hip, th e POR si gnal is asse rted and the C Y7C65x13 enters a “sem i-susp end” st ate . Durin g the
semi-suspend st ate, which i s diff erent from the suspend sta te defined i n the USB spec ification , the osci llator and al l other bl ocks
of the part are functional, except for the CPU. This semi-suspend time ensures that both a valid V
the internal PLL has time to stabilize before full operation begins. When the V
oscillator is st able, the POR is d easserted and th e on-chip timer st arts countin g. The first 1 ms of s uspend time is no t interruptible,
and the semi-suspe nd state conti nues for an addition al 95 ms unless the count is bypasse d by a USB Bus Reset on the up stream
port. The 95 ms provides time for V

If a USB Bus Reset occurs on the upstream port during the 95 ms semi-suspend time, the semi-suspend state is aborted and
program execution begins immediately from address 0x0000. In this case, the Bus Reset interrupt is pending but not serviced
until firmware sets the USB Bus Reset Interrupt Enable bit (Bit 0, Figure 14-1) and enables interrupts with the EI command.

The POR signal is asserte d whenever V
again. Behavior is the same as described above.

Document #: 38-08002 Rev. *B Page 16 of 51

to stabilize at a valid operating voltage before the chip executes code.

CC

drops below approxim ately 2.5V , and remains ass erted until VCC rises above this level

CC

has risen above approximately 2.5V, and the

CC

level is reached and that

CC

CY7C6501

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7.2 Watchdog Reset

The WDR occurs when the internal Watchd og Tim er rolls over . W riting any value to the write -only W atchdog Rese t Clear Registe r
(Figure 7-1) clears the timer. The timer rolls ov er a nd WD R oc c urs if it is not cleared within t

23.0 for the value of t
register content s are set to 01 0X0001 by the WDR) . A Watch dog Timer Reset lasts fo r 2 ms, after which the microcontrolle r begins
execution at ROM address 0x0000.

). Bit 6 of the Processor Status and Control Register (Figure13-1) is set to record this event (the

WATCH

of the last clear (s ee Sec tion

WATCH

CY7C6511

t

WATCH

Last write to

Watchdog Timer
Register

Figure 7-1. Watchdog Reset (Address 0x26)

The USB transmitter is disabled by a Watchdog Reset because the USB Device Address Registers are cleared (see Section

17.1). Otherwise, the USB Controller would respond to all address 0 transactions.
It is possible for the WDR bit of the Processor Status and Control Register (Figure 13-1) to be set following a POR event. If a

firmware interrogates th e Processor St atus and Control Register for a set condition on the WDR bit, the WD R bit should be ignored
if the POR bit is set (Bit 3 of the Processor Status and Control Register).

No write to WDT
register, so WDR
goes HIGH

2 ms

Execution begins at
Reset Vector 0x0000

8.0 Suspend Mode

The CY7C65x13 can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register.
All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL,
as well as the free-running and Watchdog timers, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle
bus activity at a USB upstream or downstream port wakes the part out of suspend. The Run bit in the Processor Status and
Control Register must be set to resume a part out of suspend.

The clock oscillator res tarts immediately after ex it ing suspend mode. The microco ntroller returns to a fully functi on al state 1 ms
after the oscillator is st able. The microcontroller executes the instruction follow ing the I/O write that placed the device into suspend
mode before servicing any interrupt requests.

The GPIO interrupt allo ws the controller to wak e-up periodically and poll system component s while maintain ing a very low average
power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at V

This also applies to internal port pins that may not be bonded in a particular package.

Typical code for entering suspend is shown below:

... ; All GPIO set to low-power state (no floating pins)
... ; Enable GPIO interrupts if desired for wake-up
mov a, 09h ; Set suspend and run bits
iowr FFh ; Write to Status and Control Register – Enter suspend, wait for USB activity (or GPIO Interrupt)
nop ; This executes before any ISR
... ; Remaining code for exiting suspend routine.

or Gnd. Note:

CC

Document #: 38-08002 Rev. *B Page 17 of 51

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9.0 General-purpose I/O Ports

V

CY7C6501

CY7C6511

CC

Q1

14 kΩ

Q3*

Q2

*Port 0,1,2: Low I

Port 3: High I

sink

GPIO

PIN

sink

OE

Internal
Data Bus

Port Write

Port Read

Reg_Bit

STRB

(Latch is Transparent)

Interrupt
Enable

Interrupt
Controller

GPIO
CFG

Data
Out
Latch

Data
In
Latch

Data
Interrupt
Latch

mode
2-bits

Control

Control

Figure 9-1. Block Diagram of a GPIO Pin

There are up to 32 GPIO pins (P0[7:0], P1[7:4,2:0], P2[7:3], and P3[1:0]) for the hardware interface. The number of GPIO pins
depends on package type. See Se ction 3.0 for the port pi ns avai labil ity on dif fere nt pa ckage typ es. Each port can be configu red
as inputs with inte rnal pull -up s, open drain outp uts , or traditi onal C MOS outputs. Port 3 offers a higher cu rrent driv e, with t ypical
current sink capability of 12 mA. The data for each GPIO port is accessible through the data registers. Port data registers are
shown in Figure 9-2 through Figure 9-5, and are set to 1 on reset

.

Port 0 Data Address 0x00

Bit # 76543210
Bit Name P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111

Figure 9- 2. Port 0 Data

Port 1 Data Address 0x01

Bit # 76543210
Bit Name P1.7 P1.6 P1.5 P1.4 Reserved P1.2 P1.1 P1.0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111

Figure 9-3. Port1 Data

Port 2 Data Address 0x02

Bit # 76543210
Bit Name P2.7 P2.6 P2.5 P2.4 P2.3 Reserved Reserved Reserved
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111

Figure 9- 4. Port 2 Data

Document #: 38-08002 Rev. *B Page 18 of 51

CY7C6501

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Port 3 Data Address 0x03

Bit # 76543210
Bit Name Reserved Reserved Re served Reserved Reserved Reserved P3.1 P3.0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111

Figure 9- 5. Port 3 Data

Special care should be t aken w ith any unu sed GPIO dat a bit s. An unused GPIO dat a bit, eithe r a pin on the ch ip or a port bit that
is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is
left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB
Specifications. If a ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a
‘0.’ Notice that the CY7C65113 always requires that P1[7:3], P2[7:0], and P3[7:0 ] be wr itte n with a ‘0 .’ Wh en the CY7 C65013 is
used, the P1[3], P2[2:0], and P3[7:2] should be written with a ‘0.’

A read from a GPIO port always returns the present state of the voltage at the pin, independent of the settings in the Port Data
Registers. During reset, all of the GPIO pins are set to a high-impedance input state. Writing a ‘0’ to a GPIO pin drives the pin
LOW. In this state, a ‘0’ is always read on that GPIO pin unless an external source overdrives the internal pull-down device.

9.1 GPIO Configuration Port

Every GPIO port can be progra mmed as inputs w ith internal pull-u ps, outputs LO W or HIGH, or Hi-Z (floating , the pin is not driven
internally). In addition, the interrupt polarity for each port can be programmed. The Port Configuration bits (Figure 9-6) and the
Interrupt Enable bit (Figure 9-7 through Figure 9-10) determine the interrupt polarity of the port pins

.

GPIO Configuration Address 0x08

Bit # 76543210
Bit Name Port 3

Config Bit 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Port 3

Config Bit 0

Port 2

Config Bit 1

Figure 9-6. GPIO Configuration Register

Port 2

Config Bit 0

Port 1

Config Bit 1

Port 1

Config Bit 0

Config Bit 1

CY7C6511

Port 0

Port 0

Config Bit 0

As shown in Table 9-1 below, a positi ve polarity on an input pin repre sents a rising edge interrupt (LO W to HIGH), and a negative
polarity on an input pin represents a falling edge interrupt (HIGH to LOW).

The GPIO interrupt is generated when all of the following conditions are met: the Interrupt Enable bit of the associated Port
Interrupt Enable Register is enabled, the GPIO Interrupt Enable bit of the Global Interrupt Enable Register (Figure 14-1) is
enabled, the Interrup t Enable Sense (bi t 2, Figure 13-1) is set, and the GPIO pin of the po rt sees an eve nt matching th e interrupt
polarity.

The driving stat e of ea ch GPIO pin is determined by the valu e written to the pin’s Dat a Reg is ter ( Figure 9-2 through Figure 9-5)
and by its associated Port Configuration bits as shown in the GPIO Configuration Register (Figure 9-6). These ports are
configured on a per-port basis, so all pins in a given port are configured together. The possible port configurations are detailed
in Table 9-1. As shown in this table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are
disabled.

During reset, all of the bits in the GPIO Configuration Register are written with ‘0’ to select Hi-Z mode for all GPIO ports as the
default configuration.

Document #: 38-08002 Rev. *B Page 19 of 51

CY7C6501

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Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity

Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit I nterrupt Polarity

1 1 0 Output LOW 0 Disabled

1 Resistive 1 – (Falling Edge)

1 0 0 Output LOW 0 Disabled

1 Output HIGH 1 Disabled

0 1 0 Output LOW 0 Disabled

1 Hi-Z 1 – (Falling Edge)

0 0 0 Output LOW 0 Disabled

1 Hi-Z 1 + (Rising Edge)

Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-2. The available GPIO drive strength are:

• Output LOW Mode: The pin’s Data Register is set to ‘0.’
Writing ‘0’ to the pi n’s Data Regi ster puts the p in in ou tput LO W mod e, reg ardless of th e cont ents of th e Port Config urat ion

Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is driven LOW through Q3.

• Output HIGH Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘10.’
In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is pulled up through Q2. The GPIO pin is capable of sourcing... of

current.

• Resistive Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘11.’
Q2 and Q3 are O FF. Q1 is ON. The GPIO p in is p ull ed up w ith a n i nte rnal 1 4kΩ re sistor. In resistive mode, t he pin m ay s er v e

as an input. Reading the pin’s Data Register returns a logic HIGH if the pin is not driven LOW by an external source.

• Hi-Z Mode: The pin’s Data Register is set to1 and Port Configuration Bits[1:0] is set either ‘00’ or ‘01.’
Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven internally. In this mode, the pin may serve as an input. Reading the

Port Data Register returns the actual logic value on the port pins.

CY7C6511

9.2 GPIO Interrupt Enable Ports

Each GPIO pin can be individually enabled or disabled as an interrupt source. The Port 0–3 Interrupt Enable Registers provide
this feature with an Interrupt Enable bit for each GPIO pin.

During a reset, GPIO interrupts are disabled by clearing all of the GPIO Interrupt Enable bits. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in
Section 14.7

.

Port 0 Interrupt Enable Address 0x04

Bit # 76543210
Bit Name P0.7 Intr

Enable
Read/WriteWWWWWWWW
Reset 00000000

Port 1 Interrupt Enable Address 0x05

Bit # 76543210
Bit Name P1.7 Intr

Enable
Read/WriteWWWWWWWW
Reset 00000000

P0.6 Intr

Enable

P1.6 Intr

Enable

P0.5 Intr

Enable

Figure 9-7. Port 0 Interrupt Enable

P1.5 Intr

Enable

Figure 9-8. Port 1 Interrupt Enable

P0.4 Intr

Enable

P1.4 Intr

Enable

P0.3 Intr

Enable

Reserved P0.2 Intr

P0.2 Intr

Enable

Enable

P0.1 Intr

Enable

P1.1 Intr

Enable

P0.0 Intr

Enable

P1.0 Intr

Enable

Document #: 38-08002 Rev. *B Page 20 of 51

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3

Port 2 Interrupt Enable Address 0x06

Bit # 76543210
Bit Name P0.7 Intr

Enable
Read/WriteWWWWWWWW
Reset 00000000

Port 3 Interrupt Enable Address 0x07

Bit # 76543210
Bit Name Reserved Reserved Reserved Reserved Re served Reserved P3.1 Intr

Read/WriteWWWWWWWW
Reset 00000000

10.0 12-bit Free-Running Timer

The 12-bit timer operates with a 1 -µs tick, provides two interrupts (128µs and 1.02 4m s) an d all ows th e firm ware to dire ctl y time
events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower
eight bits latch es the upper four bit s into a tempora ry register . When the firmwa re reads the upper fo ur bits of the timer , it is actually
reading the count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even
when the two reads are separated in time.

Timer LSB Address 0x24

Bit # 76543210
Bit Name Timer Bit 7 TimerBit 6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0
Read/WriteRRRRRRRR
Reset 00000000

P0.6 Intr

Enable

P0.5 Intr

Enable

Figure 9-9. Port 2 Interrupt Enable

Figure 9-10. Port 3 Interrupt Enable

Figure 10-1. Timer LSB Register

P0.4 Intr

Enable

P0.3 Intr

Enable

Reserved Reserved Reserved

CY7C6511

Enable

P0.3 Intr

Enable

Bit [7:0]: Timer lower eight bits.

Timer MSB Address 0x25

Bit # 76543210
Bit Name Reserved Reserved Reserved Reserved Timer Bit 11 Timer Bit 10 Timer Bit 9 Timer Bit 8
Read/Write – – – – R R R R
Reset 00000000

Figure 10-2. Timer MSB Register

Bit [3:0]: Timer higher nibble
Bit [7:4]: Reserved.

Document #: 38-08002 Rev. *B Page 21 of 51

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3

1.024-ms interrupt

µ

s interrupt

128-

CY7C6511

10 9 7856432

1 011

1 MHz clock

L1 L0L2L3

D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

8

Figure 10-3. Timer Block Diagram

11.0 I2C Configuration Register

Internal hardware support s communi cation with extern al devices thro ugh an I2C-compatible int erface. I2C-compatibl e functio n is
discussed in det ail in Sec tion 12.0.
locations of the SCL (clock) and SDA (data) pins, either on Port 1 or Port 2 as shown in Table 11-1. These bits are cleared on
reset. When the GPIO is configu r ed for I
pull-up resistors on SCL and SDA is recommended

.

I2C Configuration Address 0x09

Bit # 76543210
Bit Name I

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Table 11-1. I2C Port Configuration

2

I

C Position (Bit7, Figure 11-1)I

2

C Position Reserved Reserved Reserved Reserved Reserved I2C Port

Don’t Care 1 I

00I
10I

[3]

The I2C Position bit (Bit 7, Figure 11-1) and I2C Port Width bit (Bit 1, Figure 11-1) select the

2

C function, the internal pull up s on the pin s are disabl ed. Ad diti on of an ex tern al w ea k

2

Figure 11-1. I

2

C Configuration Register

C Port Width (Bit1, Figure 11-1)I

To Timer Registers

Width

2

C Position

2

C on P2[1:0], 0:SCL, 1:SDA

2

C on P1[1:0], 0:SCL, 1:SDA

2

C on P2[1:0], 0:SCL, 1:SDA

Reserved

12.0 I2C-compatible Controller

The I2C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and
multi-master modes of operation. The I2C-comp atible block functi ons by handling the low-l evel signaling in hardw are, and issuing
interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the
hardware keeps the I2C-compatible bus idle if necessary.

The I2C-compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a
stop bit is detected by the slave w hen in receive mode, or when arb itratio n is lost. D etai ls of the interrupt respons es are gi ven in
Section 14.8.

2

The I2C-compatibl e interface consist s of two registers, an I
(Figure 12-2). The I2C Data Register is imp lemen ted as sep arate r ead and writ e regis ters. G eneral ly, the I2C Sta tus an d Contro l
Register should o nly be m onitored a fter the I
read misleading bit status if a transaction is underway.

Note:

2

C-compatible function must be separately enabled, as described in Section 12.0.

3. I

Document #: 38-08002 Rev. *B Page 22 of 51

2

C interrupt, as all b its are valid at th at time. Po lling thi s registe r at other t imes could

C Data Register (Figure 12-1) and an I2C St atus and Contro l Register

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3

CY7C6511

The I2C clock (SCL) is connected to bit 0 of either GPIO port 1 or GPIO port 2, and the I2C SDA data is connected to bit 1 of
either GPIO port 1 or GPIO port 2. The port selection is determined by settings in the I

2

C Port Configuration Register (Section

11.0). Once the I2C-compatible fun ctionali ty is enable d by setting the I2C Enable bit of the I2C Stat us and Control Register (bit 0,
Figure 12-2), the two LSB ([1:0]) of the correspondi ng GP IO port is pl aced in Op en D rain m ode, re gardle ss of the setti ngs of the
GPIO Configuration Register. In Open Drain mode, the GPIO pin outputs LOW if the pin’s Data Register is ‘0’, and the pin is in
Hi-Z mode if the pin’s Data Register is ‘1’. The electrical characteristics of the I
GPIO ports 1 and 2. Note that the I

All control of the I

2

C clock (SCL) and data (SDA) lines is performed by the I2C-compatible block.

(max) is 2 mA @ V

OL

= 2.0V for ports 1 and 2.

OL

2

C-compatible interface is the same as that of

I2C Data Address 0x29

Bit # 76543210

2

Bit Name I

C Data 7 I2C Data 6 I2C Data 5 I2C Data 4 I2C Data 3 I2C Data 2 I2C Data 1 I2C Data 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset XXXXXXXX

2

C Data Register

Bits [7..0] : I

2

C Data

Figure 12-1. I

Contains the 8-bit data on the I2C Bus.

2

I

C Status and Control Address 0x28

Bit # 76543210

2

Bit Name MSTR Mode Continue/BusyXmit Mode ACK Addr ARB

Lost/Restart

Received

Stop

C Enable

I

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

2

Figure 12-2. I

2

The I

C Status and Control register bits are defined in Table 12-1, with a more detailed descripti on followi ng.

Table 12-1. I

2

C Status and Control Register Bit Definitions

C Status and Control Register

Bit Name Description

2

0I

C Enable When set to ‘1’, the I2C-compatible function is enabled. When cleared, I2C GPIO pins operate

normally.

2

1 Received Stop Reads 1 only in slave rec eive mo de, whe n I

C Stop bit detec ted (unle ss firmwa re did n ot ACK the

last transaction).

2 ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.

Write to 1 in master mode to perform a restart sequence (also set Continue bit).

3 Addr Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.

Reads 0 otherwise. This bit should always be written as 0.

4 ACK In receive mode, write 1 to generate ACK, 0 for no ACK.

In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
5 Xmit Mode Write to 1 for transmit mode, 0 for receive mode.
6 Continue/Busy Write 1 to indicate ready for next transaction.

Reads 1 when I

2

C-compatible block is busy with a transaction, 0 when transaction is complete.

7 MSTR Mode Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.

Clearing from 1 to 0 generates Stop bit.

Bit 7 : MSTR Mode

2

Setting this bit to 1 causes the I

C-compatible block to initiate a master mode transaction by sending a start bit and
transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes
are initiated by setting the Continue bit, as described below.

Clearing this bit (set to 0) causes the GPIO pins to operate normally.

2

In master mode, the I

C-compatible block generates the clock (SCK), and drives the data line as required depending on
transmit or receive state. The I2C-compatible block performs any required arbitration and clock synchronization. IN the
event of a loss of arbitration, this MSTR bit is cleared, the ARB Lost bit is set, and an interrupt is generated by the

Document #: 38-08002 Rev. *B Page 23 of 51

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microcontroller. If the chip is the target of an external master that wins arbitration, then the interrupt is held off until the
transaction from the external master is completed.

2

When MSTR Mode is cleared from 1 to 0 by a firmware write, an I

Bit 6 : Continue/Busy

This bit is written by the fi rmware to ind icate that t he firmware is ready for th e next byte t ransaction to begin. In other words,
the bit has respon ded to a n interru pt reque st and has c ompleted the require d updat e or read of the d ata registe r. During a
read this bit indicates if the hardware is busy and is lo cking out additi onal writes to the I
locking allows the hardware to compl ete c ert a in op erations that may requi re an ex ten ded period of time. F oll owin g an I
interrupt, the I2C-compatible block does not return to the Busy state until firmware sets the Continue bit. This allows the
firmware to make one control register write without the need to check the Busy bit.

Bit 5 : Xmit Mode

This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clearing this bit
sets the part i n rece ive m ode. Fi rmwa re gene rally d etermi nes th e val ue of th is bit from th e R/W bi t asso ciate d wit h the I
address packet. Th e Xmit Mode bit st ate is ignored whe n initially wri ting the MSTR Mode or th e Restart bit s, as these ca ses
always cause transmit mode for the first byte.

Bit 4 : ACK

This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal

2

on the I
time. During transmits (Xmit Mode = 1), this bit should be cleared.

Bit 3 : Addr

This bit is set by the I
The Addr bit is cleared whe n the firmwa re se ts the Continue bit. This bit allows the firmware to re cogni ze w hen the mas ter
has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred.

Bit 2 : ARB Lost/Restart

This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the
Continue and MSTR Mo de bit s) to pe rform an I
to the data regist er before setting the C ontinue bit. To prevent false ARB Lost signal s, the Restart bi t is cleared by h ardware
during the restart sequence.

Bit 1 : Receive Stop

This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set if the
firmware terminates the I
e.g., in receive mode if firmware se ts the Continue bit and clears the ACK bit.

Bit 0 : I

Set this bit to overri de GPIO definition with I
these pins are free to fun ction as G PIO s. In I
of the GPIO configuration setting.

C-compatible bus. W riting a 1 to this bit genera tes an ACK (SDA LOW) on the I2C -comp atib le bus at the ACK bit

2

C-compatible block during the first byte of a slave receive transaction, after an I2C start or restart.

2

C restart sequence. The I2C target address for the restart must be written

2

C transaction by not acknowledging the previous byte transmitted on the I2C-compatible bus,

2

C Enable

2

C-compatible fu nction on the t wo I2C-compatible p ins. When this bit is cleared,

2

C-compatible m ode , the t wo pin s op era te in open drain mode, independent

C Stop bit is generated.

2

C St atus and Control register. This

CY7C6511

2

C

2

C

13.0 Processor Status and Control Register

Processor Status and Control Address 0xFF

Bit # 76543210
Bit Name IRQ

Pending

Read/Write R R/W R/W R/W R/W R R/W R/W
Reset 00010001

Bit 0: Run

This bit is manipulated by the HALT instruction. When Halt is executed, all the bits of the Processor Status and Control
Register are cleared to 0. Since the run bit is clea red, the processor stops at the end of the current in struction. The process or
remains halted until an appropriate reset occurs (power-on or Watchdog). This bit should normally be written as a ‘1.’

Bit 1: Reserved

Bit 1 is reserved and must be written as a zero.

Bit 2: Interrupt Enable Sense
Document #: 38-08002 Rev. *B Page 24 of 51

Watchdog

Reset

Figure 13-1. Processor Status and Control Register

USB Bus

Reset

Interrupt

Power-on

Reset

Suspend Interrupt

Enable

Reserved Run

Sense

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3

This bit indicates w h eth er i nter r upts are enabled or dis abl ed. Firm w are has no di rec t c ontro l o ve r thi s b it a s wr i tin g a ze ro
or one to this bit position has no effect on interrupts. A ‘0’ indicates that interrupts are masked off and a ‘1’ indicates that
the interrupts are enab led. This bit is further gated with th e bit settings of the Glob al Interrupt Enable Registe r (Figure 14-1)
and USB End Point Interrupt Enable Register (Figure14-2). Instructions DI, EI, and RETI manipulate the state of this bit.

Bit 3: Suspend

Writing a ‘1’ to the Suspend bit halts the processor and cause the microcontroller to enter the suspend mode that signifi­cantly reduces power consumption. A pending, enabled interrupt or USB bus activity causes the device to come out of
suspend. After coming out of suspend, the devic e resumes firmware ex ecution at the in struction follow ing the IOWR which
put the part into suspend. An IOWR attempting to put the part into suspend is ignored if USB bus activity is present. See
Section 8.0 for more details on suspend mode operation.

Bit 4: Power-on Reset

The Power-on Reset is set to ‘1’ during a power-on reset. The firmware can check bits 4 and 6 in the reset handler to
determine whether a res et was ca used by a power-o n condi tion or a Watchdog timeout. A PO R event m ay be fo llowed b y
a Watchdog reset before firmware begins executing, as explained below.

Bit 5: USB Bus Reset Interrupt

The USB Bus Reset Interrupt bit is set when the USB Bus Reset is detec te d on receiv in g a USB Bus Rese t sig nal on the
upstream port. The USB Bus Reset signal is a single-ended zero (SE0) that lasts from 12 to 16 µs. An SE0 is defined as
the condition in which both the D+ line and the D– line are LOW at the same time. .

Bit 6: Watchdog Reset

The Watchdog Reset is set during a reset initiated by the Watchdog Timer. This indicates the Watchdog Timer went for
more than t

Bit 7: IRQ Pending

The IRQ pending, when set, indica tes that one or more o f the interrupt s has been recogniz ed as active. An interrupt remains
pending until its interrupt enable bit is set (Figure14-1, Figure 14-2) and interrupts are globally enable d. At th at po int, the
internal interrupt handling sequence clears this bit until another interrupt is detected as pending.

During power-up, the Processor S t a tus a nd C on trol R e gis ter is s et to 00 01 000 1, w hic h in dic ate s a POR (bi t 4 s et) has occurred
and no interrupts are pending (bit 7 clear). During the 96-ms suspend at start-up (explained in Section 7.1), a Watchdog Reset
also occurs unless this suspend is aborted by an upstream SE0 before 8 ms. If a WDR occurs during the power-up suspend
interval, firmware reads 010 10001 fro m the S t atus a nd Control Regist er after po wer-up. Nor mally, the POR bit should be cleared
so a subsequent WDR can be clearl y ident ified. If an ups tream bus reset is rec eived bef ore firmw are ex amine s this regis ter, the
Bus Reset bit may also be set.

During a Watc hdog Reset, the Pro cessor S tatus an d Control Regist er is set to 01XX0001 , which indica tes a Watc hdog Reset (bit
6 set) has occurred and no in terrupt s are p ending (b it 7 clear). Th e W atchdo g Reset does no t effec t the st ate of the POR and the
Bus Reset Interrupt bits.

(8 ms minimu m) between Watchdog clears. This can occur w ith a POR event, as noted below.

WATCH

CY7C6511

14.0 Interrupts

Interrupts are generated by GPIO pins, internal timers, I2C-compatible operation, internal USB hub and USB traffic conditions.
All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a
‘1’ to a bit position enables the interrupt associated with that bit position.

Global Interrupt Enable Register Address 0X20

Bit # 76543210

2

Bit Name Reserved I

Read/Write – R/W R/W - R/W R/W R/W R/W
Reset –00X0000

Bit 0 : USB Bus RST Interrupt Enable
1 = Enable Interrupt on a USB Bus Reset; 0 = Disable interrupt on a USB Bus Reset (Refer to section 14.3).
Bit 1 :128-µs Interrupt Enable
1 = Enable Timer interrupt every 128 µs; 0 = Disab le Timer Interrupt for every 128 µs.
Bit 2 : 1.024-ms Interrupt Enable

Document #: 38-08002 Rev. *B Page 25 of 51

C Interrupt

Enable

GPIO

Interrupt

Enable

Figure 14-1. Global Interrupt Enable Register

Reserved USB Hub

Interrupt

Enable

1.024-ms
Interrupt

Enable

128-µs

Interrupt

Enable

USB Bus

RST

Interrupt

Enable

CY7C6501

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3

1 = Enable Timer interrupt every 1.024 ms ; 0 = Disable Timer Interrupt every 1.024 ms.

Bit 3 : USB Hub Interrupt Enable

1 = Enable Interrupt on a Hub status change; 0 = Disable interrupt due to hub status change. (Refer to section 14.6.)
Bit 4 : Reserved .
Bit 5 : GPIO Interrupt Enable

1 = Enable Interrupt on falli ng/ris ing edge on any G PIO; 0 = Disa ble Inte rrupt on fal ling/ri sing e dge on any GPIO (Ref er to

section 14.7, 9.1 and 9.2.).

2

Bit 6 : I

Bit 7 : Reserved.

USB Endpoint Interrupt Enable Address 0X21

Bit # 76543210
Bit Name Reserved Reserved Reserved EPB1

Read/Write – – – R/W R/W R/W R/W R/W
Reset –––00000

C Interrupt Enable

1 = Enable Interrupt on I2C related activity; 0 = Disable I2C related activity interrupt. (Refer to section 14.8.)

Interrupt

Enable

Figure 14-2. USB Endpoint Interrupt Enable Register

EPB0

Interrupt

Enable

EPA2

Interrupt

Enable

CY7C6511

EPA1

Interrupt

Enable

EPA0

Interrupt

Enable

Bit 0: EPA0 Interrupt Enable

1= Enable Interrupt on data activity through endpoint A0; 0= Disable Interrupt on data activity through endpoint A0
Bit 1: EPA1 Interrupt Enable

1= Enable Interrupt on data activity through endpoint A1; 0= Disable Interrupt on data activity through endpoint A1
Bit 2: EPA2 Interrupt Enable

1= Enable Interrupt on data activity through endpoint A2; 0= Disable Interrupt on data activity through endpoint A2.
Bit 3: EPB0 Interrupt Enable

1= Enable Interrupt on data activity through endpoint B0; 0= Disable Interrupt on data activity through endpoint B0
Bit 4: EPB1 Interrupt Enable

1= Enable Interrupt on data activity through endpoint B1; 0= Disable Interrupt on data activity through endpoint B1
Bit [7..5] : Reserved
During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared,

effectively, disabling all interrupts
The interrupt controller c ontains a sep arate flip-flo p for each interrupt. Se e Figure 14-3 for the logic block diagram of the interru pt

controller . Wh en an i nterrupt i s genera ted, it is first registere d as a pe nding i nterrupt. It stay s pend ing unti l it is serviced or a res et
occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable
registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction.

When servicing an interrupt, the hardware does the following:

1. Disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the state of this bit can be read at Bit 2 of the
Processor Status and Control Register, Figure 13-1).

2. Clears the flip-flop of the current interrupt.

3. Generates an automatic CALL instructio n to the RO M addre ss assoc iated with the int errupt bei ng serv iced (i.e., the In terrupt
Vector, see Section 14.1).

The instruction in th e interru pt ta ble is ty pica lly a JMP in struct ion to the add ress of the In terrupt Serv ice R outin e (ISR). The us er
can reenable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited
only by the available stack space.

The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction gene rated as pa rt of the in terrupt ac know ledg e process . The use r firmware is resp onsible fo r ensuri ng that th e
processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first
command in the ISR to save th e ac c um ula tor v alu e an d th e PO P A ins tru cti on s ho uld be u se d to re st ore th e ac c umu la tor v alu e
just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI
instruction is executed.

Document #: 38-08002 Rev. *B Page 26 of 51

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e

The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exits the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).

14.1 Interrupt Vectors

The Interrupt Vectors su ppo rted by t he U SB Con trol ler are listed in Table 14-1. The lowest-numbered interrupt (USB Bus Reset
interrupt) has the highest priority, and the highest-numbered interrupt (I

USB Reset Clear

1

USB Reset Int

1

AddrA ENP2 Int

I2C Int

CLR

D

Q

Enable [0]

CLK

CLR

D

CLK

CLR

1

D
CLK

(Reg 0x20)

Q

Enable [2]

(Reg 0x21)

Q

Enable [6]

(Reg 0x20)

USB Reset IRQ
128-µs CLR
128-µs IRQ

1-ms CLR
1-ms IRQ

AddrA EP0 CLR
AddrA EP0 IRQ

AddrA EP1 CLR
AddrA EP1 IRQ

AddrA EP2 CLR
AddrA EP2 IRQ

AddrB EP0 CLR
AddrB EP0 IRQ

AddrB EP1 CLR
AddrB EP1 IRQ

Hub CLR
Hub IRQ

DAC CLR
DAC IRQ

GPIO CLR
GPIO IRQ

2

C CLR

I

2

C IRQ

I

Interrupt Priority Encoder

2

C interrupt) has the lowest priority.

Interrupt

Vector

To CPU

CPU

IRQout

Global

Interrupt

Enable

Bit

CLR

Interrupt

Acknowledge

CY7C6511

IRQ Sense

IRQ

Int Enabl
Sense

Controlled by DI, EI, and
RETI Instructions

Figure 14-3. Interrupt Controller Function Diagram

Although Reset is not an interrupt, the first inst ructio n executed aft er a reset is at PRO M address 0x 0000h— which co rrespon ds
to the first entry in the Interrupt V ector T able. Because th e JMP instruction is two by tes long, the interrupt ve ctors occupy two bytes.

Table 14-1. Interrupt Vector Assignments

Interrupt Vector Number ROM Address Function

Not Applicable 0x0000 Execution after Reset begins here

1 0x0002 USB Bus Reset interrupt
2 0x0004 128-µs timer interrupt
3 0x0006 1.024-ms timer interrupt
4 0x0008 USB Address A Endpoint 0 interrupt
5 0x000A USB Address A Endpoint 1 interrupt
6 0x000C USB Address A Endpoint 2 interrupt
7 0x000E USB Address B Endpoint 0 interrupt
8 0x0010 USB Address B Endpoint 1 interrupt

9 0x0012 USB Hub interrupt
10 0x0014 DAC interrupt
11 0x0016 GPIO interrupt

2

12 0x0018 I

C interrupt

Document #: 38-08002 Rev. *B Page 27 of 51

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14.2 Interrupt Latency

Interrupt latency can be calculated from the following equation:

CY7C6501

CY7C6511

Interrupt latency =(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +

For example, if a 5-clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is
issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock periods is 20/12 MHz = 1.667 µs.

(5 clock cycles for the JMP instruction)

14.3 USB Bus Reset Interrupt

The USB Controller recogni ze s a USB R es et wh en a Sing le En ded Zero (SE0 ) co ndi tio n pe rsi st s on the u p st ream U SB por t for
12–16 µs. SE0 is defined as the condition in which both the D+ line and the D– line are LOW. A USB Bus Reset may be recognized
for an SE0 as short as 12 µs, but is always reco gn ize d for an SE0 lon ger than 16 µs. When a USB Bus Reset is detected, bit 5
of the Processor S tatus an d Control Register (Figure 13-1) is set to record this event. In addition, the contr oller clears the follo wing
registers:

SIE Section:.... USB Device Address Registers (0x10, 0x40)

Hub Section:......................Hub Ports Connect Status (0x48)

........................................................Hub Ports Enable (0x49)

........................................................Hub Ports Speed (0x4A)

....................................................Hub Ports Suspend (0x4D)

..........................................Hub Ports Resume Status (0x4E)

.................................................Hub Ports SE0 Status (0x4F)

........................................................... Hub Ports Data (0x50)

.............................................Hub Downstream Force (0x51).

A USB Bus Reset Interrupt is generat ed at the end of the USB Bus Rese t condition when th e SE0 state is deass erted. If the USB
reset occurs during the start-up delay following a POR, the delay is aborted as described in Section 7.1.

14.4 Timer Interrupt

There are two periodic timer interrupts: the 128-µs interrupt and the 1.024-ms interrupt. The user should disable both timer
interrupts befor e going into the suspen d mode to avoid possibl e conflicts between servicing the timer in terrupts first or the s uspend
request first.

14.5 USB Endpoint Interrupts

There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a
USB endpoint FIFO or afte r the USB co ntrol le r sen ds a p acket to the USB host. The inte rrupt is gen erat ed o n the las t packet of
the transaction (e.g., on the host’ s ACK on an IN t ransfer , or on th e device ACK on an OUT transfer). I f no ACK is recei ved during
an IN transaction, no interrupt is generated.

14.6 USB Hub Interrupt

A USB hub interrupt is generat ed by the hardware af ter a conn ect/di sconnec t chang e, babbl e, or a resume event is de tected by
the USB repeater hardware. The babble and resume events are additionally gated by the corresponding bits of the Hub Port
Enable Register (Figure 16-3). The connect/disconnect event on a port does not generate an interrupt if the SIE does not drive
the port (i.e., the port is being forced).

14.7 GPIO Interrupt

Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as
part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read
theGPIO ports with e nable d in terrupt s to determi ne whic h pin o r pins cause d an in terrupt. A block diagra m of the G PIO int errupt
logic is shown in Figure 14-4

Document #: 38-08002 Rev. *B Page 28 of 51

3
3

.

GPIO
Pin

Port

Configuration

Register

M
U
X

CY7C6501

OR Gate

(1 input per

GPIO pin)

GPIO Interrupt
Flip Flop

1

D

CLR

Q

Interrupt

CY7C6511

Priority

Encoder

IRQout

Interrupt

Vector

1 = Enable
0 = Disable

IRA

Port Interrupt
Enable Register

1 = Enable
0 = Disable

Global

GPIO Interrupt

Enable

(Bit 5, Register 0x20)

Figure 14-4. GPIO Interrupt Structure

Refer to Sections 9.1 and 9.2 for more information of setting GPIO interrupt polarity and enabling individual GPIO interrupts. If
one port pin has triggere d an interrupt, no other port pins can cause a GPIO interrupt unti l that port pin ha s returned to it s inactive
(non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority
to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.

14.8 I2C Interrupt

The I2C interrupt occurs after vario us events on the I2C-compatible bus to signal the nee d for firmware interaction. T his generally
involves reading the I

2

C Data Register as appropriate, and finally writing the Processor Status and Control Register (Figure 13-1) to initiate the

I
subsequent transacti on. The interru pt indi cates that st atus bi ts are st able an d it is sa fe to read an d write the I
to Section 12.0 for details on the I

When enabled, th e I
bits are in th e I

1. In slave receive mode, after the slave receives a by te of data: The Addr bit is set, if this is th e first byte sinc e a start or restart
signal was sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit
MODE, and Continue/Busy bits appropriately for the next byte.

2. In sla ve receive mode, after a stop bit is detected: The Received Stop bit is s et, if the stop bit follows a slave receive transactio n
where the ACK bit was cleared to 0, no stop bit detection occurs.

3. In slave transmit mode, after the slave trans mi t s a byte of data: The ACK bit indicates if the master that requ ested the byte
acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the
Xmit MODE and Continue/Busy bits as required.

4. In master transmit mode, after the master sends a byte of data. Firmware should load the Data Register if necessary, and
set the Xmit MODE, MSTR MODE, and Continue/Busy bits approp ria tely. Clearing the MSTR MODE bit issues a stop signal

2

to the I

C-compatible bus and return to the idle state.

5. In master receive mode, after the master receives a byte of data: Firmware should read the data and set the ACK and
Continue/Busy bits appropriately for the next byte. Clearing the MSTR MODE bit at the same time causes the master state
machine to issue a stop signal to the I

6. When the master loses arbitration: This c ond iti on c le ars the MSTR MODE bit and sets the ARB Lost/Restart bi t im me dia tel y
and then waits for a stop signal on the I

The Continue/Busy bit is cleared by hard ware prior to inte rrupt conditions 1 to 4. Once th e Data Regi ster has been read or written,
firmware should c onfigure the other control bits and set the Continue/Busy bit for subs equent transa ctions. Foll owing an inte rrupt
from master mode, firmware should perform only one write to the Status and Control Register that sets the Continue/Busy bit,
without checking the value of the Continue/Busy bit. The Busy bit may otherwise be active and I
changed by the hardware during the transaction, until the I

2

C Status and Control Register (Figure 12-2) to determine the cause of the interrupt, loading/reading the

2

2

C registers.

2

C-compatible s tate machines generate interrupt s o n completi on of the follow ing cond itions. T he referenced

2

C Status and Control Register.

2

C-compatible bus and leave the I2C-compatible hardware in the idle state.

2

C-compatible bus to generate the interrupt.

2

2

C interrupt occurs.

C register contents may be

C registers. Refer

Document #: 38-08002 Rev. *B Page 29 of 51

CY7C6501

3
3

15.0 USB Overview

The USB hardware includes a U SB Hub repeater w ith one upstre am and up to se ven downstre am ports. The USB Hub repeater
interfaces to the microcontroller through a full-speed serial interface engine (SIE). An external series resistor of R
placed in series with all upstream and downstr eam USB outputs in order to meet the USB driver requirements of the USB
specification. The CY7C65x13 microcontroller can provide the functionali t y of a co mp oun d dev ic e co ns is ting of a USB hu b and
permanent ly attached f unctions.

15.1 USB Serial Interface Engine (SIE)

The SIE allows the C Y7C65x 13 mi croco ntrolle r to com municat e wi th the USB hos t throu gh th e USB rep eater p ortion of th e hub.
The SIE simplifies th e inte rface betwe en th e microc ontrol ler an d USB by inc orporati ng ha rdware th at ha ndles the f ollowin g US B
bus activity independen tly of the micro con trol le r:

• Bit stuffing/unstuffing

• Checksum genera tion / ch ec ki ng

• ACK/NAK/STALL

• Token type identifi ca tio n

• Address checking.

Firmware is required to handle the following USB interface tasks:

• Coordinate enumeration by responding to SETUP packets

• Fill and empty the FIFOs

• Suspend/Resume coordination

• Verify and select DATA toggle values.

CY7C6511

must be

ext

15.2 USB Enumeration

The internal hub and any compound device functio n are enumerated under firmware c ontrol. The hub is enumerate d first, followed
by any integrated compound function. After the hub is enumerated, the USB host can read hub connection status to determine
which (if any) of the downstream ports need to be enumerated. The following is a brief summary of the typical enumeration
process of the CY7C6 5x13 by the USB host. For a det ailed description of the enumeration proc ess, refer to the USB specifi cation.

In this description, ‘Firmware’ refers to embedded firmware in the CY7C65x13 controller.

1. The host compu ter sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor.

2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables.

3. The host computer performs a control read seq uence and Firmw are responds by s ending the Devic e descriptor over the USB
bus, via the on-chip FIFOs.

4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB
address to the device.

5. Firmware stores the new address in its USB Device Address Register (for example, as Address B) after the no-data control
sequence complete s.

6. The host sends a request for the Device descriptor using the new USB address.

7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.

8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus.

9. The host generates control reads from the device to request the Configuration and Report descriptors.

10.Once the device receives a Set Configuration request, its functions may now be used.

11.Following enumeration as a hub, Firmware can optionally indicate to the host that a compound device exists (for example, the
keyboard in a keyboard/hub device).

12.The host carries out the enumeration process with this ad ditional function as though it were attached downst ream from the hub.

13.When the host assigns an address to this device, it is stored as the other USB address (for example, Address A).

Document #: 38-08002 Rev. *B Page 30 of 51

CY7C6501

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3

16.0 USB Hub

A USB hub is required to support:

• Connectivity beh avi or: se rvi ce co nnect/disconnect detect ion

• Bus fault detection and recovery

• Full-/Low-speed devic e sup port

These features are mappe d onto a hub repeate r and a hub controller . T he hub controller is sup ported by the proces sor integrated
into the CY7C65x13 microcontrollers. The hardware in the hub repeater detects whether a USB device is connected to a
downstream port. The con nec tio n to a do wns trea m p ort i s th roug h a d ifferential signal pai r (D + an d D–) . Eac h do w nst rea m port
provided by the hub requires external R
device connected, the hub reads a LOW (zero) on both D+ and D–. This condition is used to identify the “no connect” state.

The hub must have a resistor R
The hub generates an EOP at EOF1, in accordance with the USB 1.1 Specification (section 11.2.2, page 234) as well as USB

2.0 specification (section 11.2.5, page 304).

connected between its upstream D+ line and V

UUP

16.1 Connecting/Disconnecting a USB Device

A low-speed (1.5 Mbp s) USB de vice has a p ull-up resistor o n the D– p in. At co nnect time, th e bias resist ors set th e sign al lev els
on the D+ and D– lines. When a low-speed device is connected to a hub port, the hub sees a LOW on D+ and a HIGH on D–.
This causes the hub repeater to set a connect bit in the Hub Ports Connect Status register for the downstream port (see
Figure 16-1). Then the hub repeater generates a Hub Interrupt to notify the microcontroller that there has been a change in the
Hub downstream status. The firmware sets the speed of this port in the Hub Ports Speed Register (see Figure 16-2).

A full-speed (12 Mbps) USB device has a pu ll-u p re sis to r from the D + pi n, s o th e h ub s ee s a HI GH o n D + a nd a LO W o n D–. In
this case, the hub repeater sets a connect bit in the Hub Ports Connect Status register and generates a Hub Interrupt to notify
the microcontroller of the change in Hub status. The firmware sets the speed of this port in the Hub Ports Speed Register (see
Figure 16-2)

Connects are recorded by the time a non-SE0 state lasts for more than 2.5 µs on a downstream port.
When a USB device is disco nnected from th e Hub, the downstream s ignal p air eventual ly floats to a sing le-ended ze ro state. The

hub repeater recognizes a disconnect once the SE0 state on a downstream port lasts from 2.0 to 2.5 µs. On a disconnect, the
corresponding bit in the Hub Ports Connect Status register is cleared, and the Hub Interrupt is generated

.

Hub Ports Connect Status Address 0x48

Bit # 76543210
Bit Name Reserved Port 7

Connect

Status
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

resistors from each signal line to ground, so that when a downstream port has no

UDN

to indicate it is a full speed USB device.

REG

Port 6

Connect

Status

Figure 16-1. Hub Ports Connect Status

Port 5

Connect

Status

Port 4

Connect

Status

Port 3

Connect

Status

CY7C6511

Port 2

Connect

Status

Port 1

Connect

Status

Bit [0..6] : Port x Connect Status (where x = 1..7).

When set to 1, Port x is connected; When set to 0, Port x is disconnected.

Bit 7 : Reserved.

Set to 0.

The Hub Ports Con nect S tatus register is cl eared to zero by reset or USB bus reset, then set to matc h the hardware configuration
by the hub repeater hardware. The Reserved bit [7] should always read as ‘0’ to indicate no connection

.

Hub Ports Speed Address 0x4A

Bit # 76543210
Bit Name Rese rved Port 7

Speed
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Document #: 38-08002 Rev. *B Page 31 of 51

Port 6

Speed

Figure 16-2. Hub Ports Speed

Port 5

Speed

Speed

Port 4

Port 3

Speed

Port 2

Speed

Port 1
Speed

CY7C6501

3
3

Bit [0..6] : Port x Speed (where x = 1..7).

Set to 1 if the device plugged in to Port x is Low Speed; Set to 0 if the device plugged in to Port x is Full Speed.

Bit 7 : Reserved.

Set to 0.

The Hub Ports Speed register is cleared to zero by reset or bus reset. This must be set by the firmware on issuing a port reset.
The Reserved bit [7] should always read as ‘0.’

16.2 Enabling/Disabling a USB Device

After a USB device connection has been detected, firmware must update status change bits in the hub status change data
structure that is polled periodically by the USB host. The host responds by sending a packet that instructs the hub to reset and
enable the downstre am po rt. Firmwa re then set s the bit in the H ub Port s Ena ble reg ister (Figure 16-3), for the downstream por t.
The hub repeater h ardware respond s to an enable bit in the Hu b Ports Ena ble register (Figure 16-3) by enabling the downstre am
port, so that USB traffic can flow to and from that port.

If a port is marked enabled and is not suspended, it receives all USB traffic from the upstream port, and USB traffic from the
downstream port is passed to the upstream port (unless babble is detected). Low-speed ports do not receive full-speed traffic
from the upstream port.

When firmware writes to the Hu b Ports Enabl e register (Figure16-3) to enable a po rt, the port is n ot ena bled until th e end of a ny
packet currently being transmitted. If there is no USB traffic, the port is enabled immediately.

When a USB device di sconn ectio n has b een detec ted, firm ware mu st upd ate sta tus bi ts i n the hu b cha nge st a tus da ta s tructu re
that is polled period icall y by th e USB hos t. In su spend ed mod e, a co nnect or disc onnec t even t gener ates an interru pt (if the hu b
interrupt is enabled) even if the port is disabled

.

Hub Ports Enable Register Address 0x49

Bit # 76543210
Bit Name Re served Port 7

Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Port 6

Enable

Figure 16-3. Hub Ports Enable Register

Port 5

Enable

Port 4

Enable

Port 3

Enable

CY7C6511

Port 2

Enable

Port 1

Enable

Bit [0..6] : Port x Enable (where x = 1..7)

Set to 1 if Port x is enabled; Set to 0 if Port x is disabled

Bit 7 : Reserved.

Set to 0.

The Hub Ports Enable register is cleared to zero by reset or bus reset to disable all downstream ports as the default condition.
A port is also disabled by internal hub hardware (enable bit cleared) if babble is detected on that downstream port. Babble is
defined as:

• Any non-idle downstream traffic on an enabled downstream port at EOF2.

• Any downstream port with upstream connectivity established at EOF2 (i.e., no EOP received by EOF2).

16.3 Hub Downstream Ports Status and Control

Data transfer on hub down stream port s is contro lled ac cordi ng to the bit setting s of the H ub Dow nstream Po rt s Contro l Regis ter
(Figure 16-4). Each downstre am port is controlled by two bits, as defined in Table 16-1 below. The Hub Downstream Port s Control
Register is cleared upon reset or bus reset, and the reset state is the state for normal USB traffic. Any downstream port being
forced must be marked as disabled (Figure 16-3) for proper operation of the hub repeater.

Firmware should use t his register for driving bus reset and resume signaling to downstrea m ports. Controlling the port pins through
this register uses standard USB edge rate control according to the speed of the port, set in the Hub Port Speed Register.

The downstream USB ports are designed for connection of USB devices, but can also serve as output ports under firmware
control. This all ows unus ed USB port s to be used for f unctions such as d riving LE Ds or pro viding a dditional i nput sign als. Pull ing
up these pins to voltages above V

This register is not reset by USB bus reset. These bits must be cleared before going into suspend.

may cause current flow into the pin.

REF

Document #: 38-08002 Rev. *B Page 32 of 51

CY7C6501

3
3

Hub Downstream Ports Control Register Address 0 x4B

Bit # 76543210
Bit Name Port 4

Control Bit 1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Table 16-1. Control Bit Definition for Downstream Ports

Control Bits

0 0 Not Forcing (Normal USB Function)
0 1 Force Differential ‘1’ (D+ HIGH, D– LOW)
1 0 Force Differential ‘0’ (D+ LOW, D– HIGH)
1 1 Force SE0 state

An alternate means of forcing the downstream ports is through the Hub Ports Force Low Register (Figure 16-5) and Hub Ports
Force High Register (Figure16-6). With these registers the pins of th e d owns tre am po rts can be indivi dua ll y forc ed L OW, or left
unforced. Unlike the Hub Downstream Ports Control Register, above, the Force Low Register does not produce standard USB
edge rate control on the fo rced pins. Howev er, this register allow s downstream port pins to be held LOW in suspend. This regis ter
can be used to drive SE0 on all downstream ports when unconfigured, as required in the USB 1.1 specification

.

Hub Ports Force Low Address 0x51

Bit # 76543210
Bit Name Force Low

D+[4]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Port 4

Control Bit 0

Figure 16-4. Hub Downstream Ports Control Register

Control ActionBit1 Bit 0

Force Low

D-[4]

Port 3

Control Bit 1

Force Low

D+[3]

Figure 16-5. Hub Ports Force Low Register

Port 3

Control Bit 0

Force Low

D–[3]

Port 2

Control Bit 1

Force Low

D+[2]

Port 2

Control Bit 0

Force Low

D–[2]

Control Bit 1

CY7C6511

Port 1

Force Low

D+[1]

Port 1

Control Bit

0

Force Low

D–[1]

Hub Ports Force Low Address 0x52

Bit # 76543210
Bit Name Reserved Reserved Force Low

D+[7]
Read/Write – – R/W R/W R/W R/W R/W R/W
Reset ––000000

Figure 16-6. Hub Ports Force Low Register

The data state of downstream ports can be read through the HUB Ports SE0 Status Register (Figure 16-7) and the Hub Ports
Data Register (Figure 16-8). The data read from the Hub Ports Data Register is the differential data only and is independent of
the settings of the Hub Ports Speed Register (Figure 16-2). When the SE0 condition is sensed on a downstream port, the
corresponding bits of the Hub Ports Data Register hold the last differential data state before the SE0. Hub Ports SE0 Status
Register and Hub Ports Data Register are cleared upon reset or bus reset

.

Hub Ports SE0 Status Address 0x4F

Bit # 76543210
Bit Name Reserved Port 7

SE0 Status
Read/WriteRRRRRRRR
Reset 00000000

Document #: 38-08002 Rev. *B Page 33 of 51

Port 6

SE0 Status

Figure 16-7. Hub Ports SE0 Status Register

Force Low

D–[7]

Port 5

SE0 Status

Force Low

D+[6]

Port 4

SE0 Status

Force Low

D–[6]

Port 3

SE0 Status

Force Low

D+[5]

Port 2

SE0 Status

Force Low

D–[5]

Port 1

SE0 Status

CY7C6501

3
3

Bit [0..6]: Port x SE0 Status (where x = 1..7).

Set to 1 if a SE0 is output on the Port x bus; Set to 0 if a Non-SE0 is output on the Port x bus.

Bit 7: Reserved.

Set to 0
.

Hub Ports Data ADDRESS 0x50

Bit # 76543210
Bit Name Reserved Port 7 Diff.

Read/WriteRRRRRRRR
Reset 00000000

Bit [0..6] : Port x Diff Data (where x = 1..7).

Set to 1 if D+ > D- (force d dif fere ntial 1, if sig nal is dif fere ntial, i.e. n ot a SE0 or SE1). Set to 0 if D- > D+ (forced di ff erential
0, if signal is differential, i.e. not a SE0 or SE1).

Bit 7 : Reserved.

Set to 0.

Data

16.4 Downstream Port Suspend and Resume

The Hub Ports Suspend R egister (Figure 16-9) and Hub Ports Resume S tat us Regist er (Figure16-10) indicate the sus pend and
resume conditions on downstream ports. The suspend register must be set by firmware for any ports that are selectively
suspended. Also, this register is only valid for ports that are selectively suspended.

If a port is marked as selectively suspended, normal USB traffic is not sent to that port. Resume traffic is also prevented from
going to that port , un le ss the R es um e co me s f r om the s ele ct ively suspended port. I f a resume condition is d ete cted on the port,
hardware reflects a Resume back to the port, sets the Resume bit in the Hub Ports Resume Register, and generates a hub
interrupt.

If a disconnect occurs on a port marked as selectively suspended, the suspend bit is cleared.
The Device Remote Wakeup bi t (bit 7) of the Hub Ports Suspend Regi ster controls whet her or not the resume signal is propag ated

by the hub after a connect or a disconnect event. If the Device Remote Wakeup bit is set, the hub will automatically propagate
the resume signal after a con nect or a di scon nect ev ent. If the Dev ice Remo te Wakeup bit is cleared, th e hub will no t prop ag ate
the resume signal. The setting of the Device Remote Wakeup flag has no impact on the propagation of the resume signal after
a downstream remote wakeup event. The hub will automatically propagate the resume signal after a remote wakeup event,
regardless of the st ate of the De vice Remote w akeup bit. The state o f this bit has no impac t on the genera tion of the hub interrupt.

A resume bit is set automa tic all y w he n ha rdw are dete cts a resume condition on a se lec ti vel y s us pen ded downstream port. The
resume condition is a differential ‘1’ for a low-speed device and a differential ‘0’ for a full-speed device.

These registers are cleared on reset or USB bus reset
.

Hub Ports Suspend Address 0x4D

Bit # 76543210
Bit Name Device

Remote

Wakeup
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Port 7
Selective
Suspend

Port 6 Diff.

Data

Figure 16-8. Hub Ports Data Register

Port 6

Selective

Suspend

Figure 16-9. Hub Ports Suspend Register

Port 5 Diff.

Data

Port 5
Selective
Suspend

Port 4 Diff.

Data

Port 4

Selective

Suspend

Port 3 Diff.

Data

Port 3

Selective

Suspend

CY7C6511

Port 2 Diff.

Data

Port 2

Selective

Suspend

Port 1 Diff.

Data

Port 1
Selective
Suspend

Bit [0..6] : Port x Selective Suspend (where x = 1..7).

Set to 1 if Port x is Selectively Suspended; Set to 0 if Port x Do not suspend.

Bit 7 : Device Remote Wake up .

When set to 1, Enable hardware upstream resume signaling for connect/disconnect events during global resume.
When set to 0, Disable hardware upstream resume signaling for connect/disconnect events during global resume.

Document #: 38-08002 Rev. *B Page 34 of 51

CY7C6501

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3

Hub Ports Resume Address 0x4E

Bit # 76543210
Bit Name Reserved Resume 7 Resume 6 Resume 5 Resume 4 Resume 3 Resume 2 Resume 1
Read/Write- RRRRRRR
Reset 00000000

Figure 16-10. Hub Ports Resume Status Register

Bit [0..6] : Resume x (where x = 1..7).

When set to 1 Port x requesting to be resumed (set by hardware); default state is 0.

Bit 7 : Reserved.

Set to 0.

Resume from a selectively suspended port, with the hub not in suspend, typically involves the following actions:

1. Hardware detects the Resume , dri ves a K to the port, and generates the hub interrupt. The correspond ing bi t in the R es ume
Status Register (0x4E) reads ‘1’ in this case.

2. Firmware responds to hub interrupt, and reads register 0x4E to determine the source of the Resume.

3. Firmware begins driving K on the port for 10 ms or more through register 0x4B.

4. Firmware clears the Selective Suspend bit for the port (0x4D), which clears the Resume bit (0x 4E). This ends the hardware-driv­en Resume, but the firm ware- driv en R es ume c onti nu es. To prevent traffic bei ng f ed b y t he hub repeater to the port duri ng or
just after the Resume, firmware should disable this port.

5. Firmware drives a timed SE0 on the port for two low-speed b it tim es as a ppropriate. Firmware must dis ab le int errup t s during
this SE0 so the SE0 pulse isn’t inadvertently lengthened, and appear as a bus reset to the downstream device.

6. Firmware drives a J on the port for one low-speed bit time, then it idles the port.

7. Firmware re-enables the port.

Resume when the hub is suspended typically involves these actions:

1. Hardware detects the Resume, drives a K on the upstream (which is then reflected to all downstream enabled ports), and
generates the hub interrupt.

2. The part comes out of suspend and the clocks start.

3. Once the clocks are stable, firm ware ex ec uti on resumes. An internal cou nte r en sures that this takes at least 1 ms. Firmwa re
should check for Resume from any selectively suspended ports. If found, the Selective Suspend bit for the port should be
cleared; no other action is necessary.

4. The Resume ends when the host stops sending K from upstream. Firmware should check for changes to the Enable and
Connect Registers. If a port has become disabled but is still connected, an SE0 has been detec ted on the port. The port should
be treated as having been reset, and should be reported to the host as newly connected.

Firmware can choose to clear the Device Remote Wake-up bit (if set) to implement firmware timed states for port changes. All
allowed port changes wake the part. Then, the part can use internal timing to determine whether to take action or return to
suspend. If Device Remote Wake-up is set, automatic hardware assertions take place on Resume events.

CY7C6511

16.5 USB Upstream Port Status and Control

USB status and co ntrol is re gulated by th e USB S t atus and Control Re gister, as shown in Figure 16-11. All bits in the register are
cleared during reset

.

USB Status and Control Address 0x1F

Bit # 76543210
Bit Name Endpoint

Size

Read/Write R/W R/W R R R/W R/W R/W R/W
Reset 00000000

Bits[2..0]: Control Action

Set to control action as pe r table 16-2.Th e three control b its allow the upstream p ort to be driven manua lly by firmware . For
normal USB operation, all of these bits must be cleared. Table 16-2 shows how the control bits affect the upstream port.

Document #: 38-08002 Rev. *B Page 35 of 51

Endpoint

Mode

D+

Upstream

Figure 16-11. USB Status and Control Register

D–

Upstream

Bus Activity Control

Action

Bit 2

Control

Action

Bit 1

Control

Action

Bit 0

CY7C6501

3
3

Table 16-2. Control Bit Definition for Upstream Port

Control Bits Control Action

000 Not Forcing (SIE Controls Driver)
001 Force D+[0] HIGH, D–[0] LOW
010 Force D+[0] LOW, D–[0] HIGH
011 Force SE0; D+[0] LOW, D–[0] LOW
100 Force D+[0] LOW, D–[0] LOW
101 Force D+[0] HiZ, D–[0] LOW
110 Force D+[0] LOW, D–[0] HiZ
111 Force D+[0] HiZ, D–[0] HiZ

Bit 3: Bus Activity.

This is a “sticky” bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware should
check and clear th is bit periodic ally to detect any loss of bus a ctivity . W riting a ‘0’ to the Bus Activity bi t clears it, whil e writing
a ‘1’ preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.

Bits 4 and 5: D– Upstream and D+ Upstream.

These bits give the state of each upstream port pin individually: 1 = HIGH, 0 = LOW.

Bit 6: Endpoint Mode.

This bit used to configure the number of USB endpoints. See Section 17.2 for a detailed description.

Bit 7: Endpoint Size.

This bit used to configure the number of USB endpoints. See Section 17.2 for a detailed description.

The hub generates an EOP at EOF1 in accordance with the USB 1.1 Specification, Section 11.2.2.

CY7C6511

17.0 USB Serial Interface Engine Operation

The CY7C65x13 SIE supports operation as a single device or a compound device. This section describes the two device
addresses, the configurable endpoints, and the endpoint function.

17.1 USB Device Addresses

The USB Controller provi des two USB Devic e Address Regi sters: A (addres sed at 0x 10)and B (addre ssed at 0x40). U pon re set
and under default con ditions, Device A h as three e ndpoint s and Dev ice B has two endpoint s. The USB Device Ad dress R egister
contents are cleared du ring a reset , setting th e USB device addresses to zero and disabling these addre sses. Figure 17-1 shows
the format of the USB Address Registers.

USB Device Address (Device A, B) Addresses 0x10(A) and 0x40(B)

Bit # 76543210
Bit Name Device

Address

Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Bits[6..0]: Device Address.

Firmware writes this bits during the USB enumeration process to the non-zero address assigned by the USB host.

Bit 7: Device Address Enable.

Must be set by firmware before the SIE can respond to USB traffic to the Device Address.

17.2 USB Device Endpoints

The CY7C65x13 c on trol ler su pports up to two a ddre sses an d five endpoints f or c om m uni ca tion w i th the ho st. The configuration
of these endpoints , and associa ted FIFOs, is cont rolled by bit s [7,6] of the USB S tatus and Control Re gister (Figure 16-11). Bit 7
controls the size of the endpoints and bit 6 controls the number of addresses. These configuration options are detailed in
Table 17-1. Endpoint FIFOs are part of user RAM (as shown in Section 5.4.1).

Device

Address

Bit 6

Device

Address

Bit 5

Figure 17-1. USB Device Address Registers

Device

Address

Bit 4

Device

Address

Bit 3

Device

Address

Bit 2

Device

Address

Bit 1

Device

Address

Bit 0

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Table 17-1. Memory Allocation for Endpoints

USB Status And Control Register (0x1F) Bits [7, 6]

[0,0] [1,0] [0,1] [1,1]

Two USB Addresses:

A (3 Endpoints) and

B (2 Endpoints)

Label

EPB1 0xD8 8 EPB0 0xA8 8 EPA4 0xD8 8 EPA3 0xA8 8
EPB0 0xE0 8 EPB1 0xB0 8 EPA3 0xE0 8 EPA4 0xB0 8
EPA2 0xE8 8 EPA0 0xB8 8 EPA2 0xE8 8 EPA0 0xB8 8
EPA1 0xF0 8 EPA1 0xC0 32 EPA1 0xF0 8 EPA1 0xC0 32
EPA0 0xF8 8 EPA2 0xE0 32 EPA0 0xF8 8 EPA2 0xE0 32

When the SIE writes data to a FIFO, the internal data bus is driven by the SIE; not the CPU. This causes a short delay in the
CPU operation. The delay is three clock cycles per byte. For example, an 8-byte data write by the SIE to the FIFO generates a
delay of 2 µs (3 cycles/byte * 83.33 ns/cycle * 8 bytes).

Start

Address Size Label

17.3 USB Control Endpoint Mode Registers

All USB devices are required to have a control endpoint 0 (EPA0 and EPB0) that is used to initialize and control each USB
address. Endpoint 0 provides access t o the device con figuration information and allows generi c USB status and control accesses .
Endpoint 0 is bidirectional to both receive and transmit data. The other endpoints are unidirectional, but selectable by the user
as IN or OUT endpoints.

The endpoint mode registers are cleared durin g reset. Whe n USB Status And Control Regis ter Bits [6,7] are set to [0,0] or [1,0] ,
the endpoint zero EPA0 and EPB0 mode registers use the format shown in Figure 17-2.

Two USB Addresses:

A (3 Endpoints) and

B (2 Endpoints)

Start

Address Size Label

One USB Address:

A (5 Endpoints)

Start

Address Size Label

CY7C6511

One USB Address:

A (5 Endpoints)

Start

Address Size

USB Device Endpoint Zero Mod e (A0, B0) Addresses 0x12(A0) and 0x42(B0)

Bit # 7 6543210
Bit Name Endpoint 0

SETUP

Received

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0000000

Bits[3..0]: Mode.

These sets the mode which control how the control endpoint responds to traffic.

Bit 4: ACK.

This bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.

Bit 5: Endpoint 0 OUT Received.

1= Token received is an O UT token . 0= Token received is not an OUT toke n. This bit is set by the SIE to re port the ty pe of
token received by the corresponding device address is an OUT token. The bit must be cleared by firmware as part of the
USB processing.

Bit 6: Endpoint 0 IN Received.

1= Token received is an IN token. 0= Token received is not an IN token. This bit is set by the SIE to report the type o f token
received by the corresponding device address is an IN token. The bit must be cleared by firmware as part of the USB
processing.

Bit 7: Endpoint 0 SETUP Received.

1 = Token received is a SETUP to ken . 0= Token received is not a SETUP token. Th is bit i s se t O NLY by the SIE to report
the type of token received by the corresponding device address is a SETUP token. Any write to this bit by the CPU will
clear it (set it to 0). The bit is forced HIGH from the start of the dat a p ac ke t phase of the SETUP transaction until the s t art
of the ACK packet returned by the SIE. The CPU should not clear this bit during this interval, and subsequently, until the
CPU first does an IORD to this endpoint 0 mode register. The bit must be cleared by firmware as part of the USB
processing.

[4]

Endpoint 0

IN

Received

Figure 17-2. USB Device Endpoint Zero Mode Registers

Endpoint 0

OUT

Received

ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0

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Bits[6:0] of the endp oint 0 mode regis ter are lock ed from CPU write op erat ions wh eneve r the SIE has update d one of the se bi ts ,
which the SIE does only at the end of the tok en phase of a transact ion (SETUP... Data... ACK, OUT... Data... ACK, or IN... Data...
ACK). The CPU can unlock these bits by doing a subsequent read of this register. Only endpoint 0 mode registers are locked
when updated. The locking mechanism does not apply to the mode registers of other endpoints.

Because of these hard ware locking features, fi rmware must perform an IORD afte r an IOWR to an endpoint 0 register. This verifies
that the contents have changed as desired, and that the SIE has not updated these values.

While the SETUP b it is set, the CP U cannot write to the endpoint zero FIFOs. This prevent s firmware from ov erwriting an inc oming
SETUP transaction before firmw are has a chance to read the SETU P data. Refer to Table 17-1 for the appropriate endpoint zero
memory locatio ns.

The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in Table 18-1.
Additional information on the mode bits can be found in Table 18-2 and Table 18-3.

17.4 USB Non-control Endpoint Mode Registers

The format of the non-control endpoint mode registers is shown in Figure17-3.

USB Non-control Device Endpoint Mode Addresses 0x14, 0x16, 0x44

Bit # 76543210
Bit Name STALL Reserved Reserved ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Figure 17-3. USB Non-control Device Endpoint Mode Registers

[5]

CY7C6511

Bits[3..0] : Mode.

These sets the mode which control how the control endpoint responds to traffic. The mode bit encoding is shown in
Table 18-1.

Bit 4 : ACK.

This bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.

Bits[6..5]: Reserved.

Must be written zero during register writes.

Bit 7: STALL.

If this STALL is set, the SIE stalls an OUT packet if the mode bits are set to ACK-IN, and the SIE stalls an IN packet if the
mode bits are set to ACK-OUT. For all other modes, the STALL bit must be a LOW.

17.5 USB Endpoint Counter Registers

There are five Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byte co unt information for USB transactions , as well as bit s for data p acket status . The format of these registers is shown
in Figure 17-4.

USB Endpoint Counter Addresses 0x1 1, 0x13, 0x15, 0x41, 0x43

Bit # 76543210
Bit Name Data 0/1

Toggle
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000

Data Valid Byte Count

Bit 5

Figure 17-4. USB Endpoint Counter Registers

Byte Count

Bit 4

Byte Count

Bit 3

Byte Count

Bit 2

Byte Count

Bit 1

Byte Count

Bit 0

Bits[5..0]: Byte Count.

Notes:

4. In 5-endpoint mode (USB Status And Control Register Bits [7,6] are set to [0,1] or [1,1]), Register 0x42 serves as non-control endpoint 3, and has the format for
non-control endpoints shown in Figure 17-3.

5. The SIE offers an “Ack out – Status in” mode and not an “Ack out – Nak in” mode. Therefore, if following the status stage of a Control Write transfer a USB host
were to immediately start the next transfer, the new Setup packet could override the data payload of the data stage of the previous Control Write.

These counter bits indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with
the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 32, inclusive. For OUT or

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SETUP transactions, the c ount is u pdated by hardware to the num ber of dat a byt es rece ived, pl us two for th e CRC byte s.
Valid values are 2 to 34, inclusive.

Bit 6: Data Valid.

This bit is set on receiving a proper CRC wh en the endpoint FI FO buf fer is loaded wi th data during tran sactions. This bit is
used OUT and SETUP tokens only. If the CRC is not correct, the endpoint interrupt occurs, but Data Valid is cleared to a
zero.

Bit 7: Data 0/1 Toggle.

This bit selects th e DAT A p acket’ s toggle state: 0 for DAT A0, 1 for DAT A1. F or IN transacti ons, firmwa re must set this bit to
the desired state. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.

Whenever the count updates from a SETUP or OUT transa ction on en dpo int 0, the counter regist er l oc ks a nd ca nnot be written
by the CPU. Reading the re gister unlocks i t. This prevents firmware from overw riting a status update on incoming SETU P or OUT
transactions before firmware has a chance to re ad the dat a. Only endpoi nt 0 counter r egister is loc ked when upda ted. The locki ng
mechanism does not apply to the count registers of other endpoints.

17.6 Endpoint Mode/Count Registers Upd ate and Locking Mechanism

The contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in Figure 17-5. Two
time points, SETUP and UPDATE, are shown in the same figure. The following activities occur at each time point:

SETUP:
The SETUP bit of the endpoint 0 mo de register is forced HIGH at this time. Thi s bit is force d HIGH by the SIE unti l the end of the

data phase of a control write transfer. The SETUP bit can not be cleared by firmware during this time.
The affected mode and counter registers of e ndp oint 0 are locked from any C PU write s o nc e th ey are upd ated . Th es e re gis ters

can be unlocked by a CPU read, only if the read operation occurs after the UPDATE. The firmware needs to perform a register
read as a part of the endpoint ISR processing to unlock the effected registers. The locking mechanism on mode and counter
registers ensures that the firmware recognizes the changes that the SIE might have made since the previous IO read of that
register.

UPDATE:

1. Endpoint Mode Register – All the bits are updated (except the SETUP bit of the endpoint 0 mode register).

2. Counter Registers – All bits are updated.

3. Interrupt – If an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpoint is

set at this time. For details on what conditions are required to generate an endpoint interrupt, refer to Table 18-2.

4. The contents of the updated en dpoint 0 mode and c ounter reg isters are locked, except the SET UP bit of the endpo int 0 mod e

register which was locked earlier.

CY7C6511

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1. IN Token

CY7C6511

H
O
S

T

Host To Device Device To Host

S

Y
N
C

S

Y
N
C

A

D

IN

D
R

Token Packet Data Pa c k et

Host To Device

A

D

IN

D
R

Token Packet

C

E

R

N

C

D

5

P

C

E

R

N

C

D

5

P

UPDATE

D

S

A

Y

T

N

A

C

1/0

Device To Host

S
Y

NAK/STALL

N
C

Data Packet

Data

2. OUT or SETUP Token without CRC error

Host To Device

Host To Device

C
R
C

16

Host To Device

S

A

Y

C

N

K

C

Hand

Shake

Packet

UPDATE

Device To Host

D
E
V

I

C

S

Y
N
C

O

A

U

D

T

D

/

R

Set

up

Token Packet

C

E

R

N

C

D

5

P

SETUP

S
Y
N
C

D
A

Data

T

A

1/0

Data Packet

3. OUT or SETUP Token with CRC error

Host To Device

O

U

S

T

Y

/

N

Set

C

up

Token Packet

A
D
D
R

Figure 17-5. Token/Data Packet Flow Diagram

C

E

R

N

C

D

5

P

Host To Device

D

S

A

Y

T

N

A

C

1/0

Data

Data Packet

C
R
C

16

UPDATE

C
R
C

16

UPDATE only if FIFO is

S
Y
N
C

written

ACK,
NAK,
STAL

Hand

Shake

Packet

E

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18.0 USB Mode Tables

Table 18-1. USB Register Mode Encoding

Moder

Disable 0000 ignore ignore ignore Ignore all USB traffic to this endpoint
Nak In/Out 0001 accept NAK NAK Forced from Setup on Control end po int, from mo des other than 000 0
Status Out Only 0010 accept stall check For Control endpoints
Stall In/Out 0011 accept stall stall For Control endpoints
Ignore In/Out 0100 accept ignore ignore For Control endpoints
Isochronous Out 0101 ignore ignore alwaysFor Isochronous endpoints

Mode

Bits SETUP IN OUT Comments

CY7C6511

Status In Only 0110 accept TX 0

Isochronous In 0111 ignore TX Count ignore For Isochronous endpoints
Nak Out 1000 ignore ignore NAK Is set by SIE on an ACK from mode 1001 (Ack Out)

[6]

1001

Ack Out(ST ALL
Ack Out(STAL L

Nak Out - Status In 1010 accept TX 0

Ack Out - Status In 1011 accept TX 0

Nak In 1100 ignore NAK ignore Is set by SIE on an ACK from mode 1101 (Ack In)
Ack IN(STALL

Ack IN(STALL
Nak In - Status Out 1110 accept NAK check Is set by SIE on an ACK from mode 1111 (Ack In – Status Out)
Ack In - Status Out 1 111 accept TX Count check On issuance of an ACK this mode is c hanged by SIE to 1110 (NAK In

Mode

This lists the mn emoni c giv en to the di ff eren t mod es tha t can be se t in t he Endp oin t Mod e Regis ter by writ ing to the l ower nibb le
(bits 0..3). The bit settings for different modes are covered in the column marked “Mode Bits”. The Status IN and Status OUT
represent the Status stage in the IN or OUT transfer involving the control endpoint.

Mode Bits

These column lists the encoding for different modes by setting Bits[3..0] of the Endpoint Mode register. This modes represents
how the SIE responds to different tokens sent by the host to an endpoint. For instance, if the mode bits are set to “0001” (NAK
IN/OUT), the SIE will respond with an

• ACK on receiving a SETUP token from the host.

• NAK on receiving an OUT token from the host.

• NAK on receiving an IN token from the host.

Refer to section 13.0 for more information on the SIE functioning.

SETUP, IN, and OUT

These columns shows the SIE’s response to the host on receiving a SETUP, IN and OUT token depending on the mode set in
the Endpoint Mode Register.

=0)

[6]

=1)

1001

[6]

=0)

[6]

=1)

1101
1101

ignore
ignore

ignore
ignore

BYte

ignore
ignore

BYte

BYte

TX Count

stall

stall For Control Endpoints

ACK

On issuance of an ACK this mode is changed by SIE to 1000 (NAK

stall

Out)

NAK Is set by SIE on an ACK from mode 1011 (Ack Out – Status In)

ACK On issuance of an ACK this mode is changed by SIE to 1010 (NAK

Out – Status In)

ignore

On issuance of an ACK this mode is changed by SIE to 1 100 (NAK In)

ignore

– Status Out)

A “Check” on the OUT token column, implies that on receiving an OUT token the SIE checks to see whether the OUT packet is
of zero length and h as a Dat a Toggle (DTOG) set to ‘1.’ If the DT OG bit is se t and th e re ceived O UT Pack et has zero le ngt h, the
OUT is ACKed to comp lete th e transac tion. If either o f th is co nditio n is not m et the SI E will respond w ith a STALLL or just ignore
the transaction.

A “TX Count” entry in the IN colu mn impli es that the SIE tr ansmit the number of bytes specifi ed in the Byte Count (bit s 3..0 of th e
Endpoint Count Register) to the host in response to the IN token received.

Note:

6. STALL bit is bit 7 of the USB Non-control Device Endpoint Mode registers. For more information, refer to Section 17.4.

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A “TX0 Byte” entry in the IN column implies that th e SI E tra nsm it a zero length byte p ac ket in res po nse to th e IN token received
from the host.

An “Ignore” in any of the columns means that the device will not send any handshake tokens (no ACK) to the host.
An “Accept” in any of the columns means that the device will respond with an ACK to a valid SETUP transaction tot he host.

Comments

Some Mode Bits are automatically changed by the SIE in response to certain USB transactions. For example, if the Mode Bits
[3:0] are set to '1111' which is ACK IN-Status OUT mode as shown in Table 18-1, the SIE wil l change the endpoint Mode Bi ts [3:0]
to NAK IN-Status OUT mode (1110) after ACK’ing a valid status stage OUT token. The firmware needs to update the mode for
the SIE to respond appropriat ely . See Table 18-1 for more det ails on what modes w ill be changed by the SIE . A disabled endpoi nt
will remain disab led unt il cha nged b y firmwa re, and all end points reset to the disabl ed mod e (0000 ). Firmw are n ormall y enables
the endpoint mode after a SetConfiguration request.

Any SETUP packet to an enabled endpoint with mode set to accept SETUPs will be changed by the SIE to 0001 (NAKing INs
and OUTs). Any mode set to accept a SETUP will send an ACK handshake to a valid SETUP token.

The control endpoint has three sta tus bit s for ident ifying the toke n typ e received (SETUP, IN, or OUT), but the endpoint m ust be
placed in the correct mode to function as such. Non-control endpoints should not be placed into modes that accept SETUPs.
Note that most modes that contro l transactions inv olving an ending ACK, are ch anged by the SIE to a correspon ding mode which
NAKs subsequent packets following the ACK. Exceptions are modes 1010 and 1110

.

Table 18-2. Decode table for Table 18-3: “Details of Modes for Differing Traffic Conditions”

CY7C6511

Properties of Incoming

Packets

3 2 1 0

Endpoint Mode
encoding

Legend: TX : transmit UC : unchanged

Token count buffer dval DTOG DVAL COUNT Setup In Out ACK 3 2 1 0 Response Int

Received Token
(SETUP/IN/OUT)

The validity of the received data

The quality status of the DMA buffer

The number of received bytes Acknowledge phase completed

RX : receive TX0 :Transmit 0 length packet

available for Control endpoint only

x: don’t care

Changes to the Internal Register made by the SIE on receiving an incoming packet

Byte Count (bits 0..5, Figure 17-4)

Data Valid (bit 6, Figure 17-4)

Data0/1 (bit7 Figure 1 7-4)

from the host Interrupt

PID Status Bits

(Bit[7..5], Figure 17-2)

Endpoint Mode bits

Changed by the SIE

SIE’s Response
to the Host

The response of the SIE can be summarized as follows:

1. The SIE will only respond to valid transactions, and will ignore non-valid ones.

2. The SIE will generate an interrupt when a valid transaction i s completed or when the FIFO is corrupted. FIFO co rruption occurs
during an OUT or SETUP transaction to a valid internal address, that ends with a non-valid CRC.

3. An incoming Data packet is valid if the count is <

Endpoint Size + 2 (includes CRC) and passes all error checking;

4. An IN will be ignored by an OUT configured endpoint and visa versa.

5. The IN and OUT PID status is updated at the end of a transaction.

6. The SETUP PID status is updated at the beginning of the Data packet phase.

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7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that
endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of the register, which should be
done by the firmware only afte r the trans action is comple te. This repre sent s abou t a 1-µs wi ndow in w hich the CPU is lo cked
from register writes to these USB registers. Normally the firmware should perform a register read at the beginning of the
Endpoint ISRs to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that
the firmware recogniz es the chan ges that the SIE migh t have mad e during the pre vious transa ction. Note that the set up bit of
the mode register is NOT locked. This means that before writing to the mode register, firmware must first read the register to
make sure that the setup b it is not s et (which indicates a setup wa s received , while pro cessing th e current USB request ). This
read will of course unlock the register. So care must be taken not to overwrite the register elsewhere

.

Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2 for the decode legend)

SETUP (if accepting SETUPs)
Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr

See Table 18-1 Setup <= 10 data valid updates 1 updates 1 UC UC 1 0 001ACK yes
See Table 18-1 Setup > 10 junk x updates updates updates 1 UC UC UC NoChange ignore yes
See Table 18-1 Setup x junk invalid updates 0 updates 1 UC UC UC NoChange ignore yes

Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr

DISABLED
0 0 0 0 x x UC x UC UC UC UC UC UC UC NoChange ignore no
Nak In/Out
0 0 0 1 Out x UC x UC UC UC UC UC 1 UC NoChange NAK yes
0 0 0 1 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Ignore In/Out
0 1 0 0 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 0 0 In x UC x UC UC UC UC UC UC UC NoChange ignore no
Stall In/Out
0 0 1 1 Out x UC x UC UC UC UC UC 1 UC NoChange Stall yes
0 0 1 1 In x UC x UC UC UC UC 1 UC UC NoChange Stall yes

CONTROL WRITE
Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr

Normal Out/premature status In
1 0 1 1 Out <= 10 data valid updates 1 updates UC UC 1 1 1 010ACK yes
1 0 1 1 Out > 10 junk x updates up dates updates UC UC 1 UC NoChange ignore yes
1 0 1 1 Out x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes
1 0 1 1 In x UC x UC UC UC UC 1 UC 1 NoChange TX 0 yes
NAK Out/premature status In
1 0 1 0 Out <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 0 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 0 1 0 In x UC x UC UC UC UC 1 UC 1 NoChange TX 0 yes
Status In/extra Out
0 1 1 0 Out <= 10 UC valid UC UC UC UC UC 1 UC 0 011Stall yes
0 1 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
0 1 1 0 In x UC x UC UC UC UC 1 UC 1 NoChange TX 0 yes

CONTROL READ
Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr

Normal In/premature status Out
1 1 1 1 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
1 1 1 1 Out 2 UC valid 0 1 updates UC UC 1 UC 0 011Stall yes
1 1 1 1 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 011Stall yes
1 1 1 1 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 1 1 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 1 1 1 In x UC x UC UC UC UC 1 UC 1 1 110ACK (back) yes

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Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2 for the decode legend) (continued)

Nak In/premature status Out
1 1 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
1 1 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC 0 011Stall yes
1 1 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 011Stall yes
1 1 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 1 1 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Status Out/extra In
0 0 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
0 0 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC 0 011Stall yes
0 0 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 011Stall yes
0 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
0 0 1 0 Out x UC invalid UC UC UC UC 1 UC UC NoChange ignore no
0 0 1 0 In x UC x UC UC UC UC 1 UC UC 0 011Stall yes

OUT ENDPOINT
Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr

Normal Out/erroneous In
1 0 0 1 Out <= 10 data valid updates 1 updates UC UC 1 1 1 000ACK yes
1 0 0 1 Out > 10 junk x updates up dates updates UC UC 1 UC NoChange ignore yes
1 0 0 1 Out x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes
1 0 0 1 In x UC x UC UC UC UC UC UC UC NoChange ignore no

1 0 0 1 In x UC x UC UC UC UC UC UC UC NoChange Stall no

NAK Out/erroneous In
1 0 0 0 Out <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 0 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 0 0 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 0 0 0 In x UC x UC UC UC UC UC UC UC NoChange ignore no
Isochronous endpoint (Out)
0 1 0 1 Out x updates updates updates updates updates UC UC 1 1 NoChange RX yes
0 1 0 1 In x UC x UC UC UC UC UC UC UC NoChange ignore no

IN ENDPOINT
Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr

Normal In/erroneous Out
1 1 0 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore no

1 1 0 1 Out x UC x UC UC UC UC UC UC UC NoChange stall no

1 1 0 1 In x UC x UC UC UC UC 1 UC 1 1 100ACK (back) yes
NAK In/erroneous Out
1 1 0 0 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 0 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Isochronous endpoint (In)
0 1 1 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 1 1 In x UC x UC UC UC UC 1 UC UC NoChange TX yes

CY7C6511

[6]

= 0)

(STALL

[6]

= 1)

(STALL

[6]

= 0)

(STALL

[6]

(STALL

= 1)

Document #: 38-08002 Rev. *B Page 44 of 51

CY7C6501

3
3

19.0 Register Summary

Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write/B

0x00 Port 0 Data P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 BBBBBBBB 11111111
0x01 Port 1 Data P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
0x02 Port 2 Data P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 BBBBBBBB 11111111
0x03 Port 3 Data P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
0x04 Port 0 Interrupt Enable P0.7 Intr

0x05 Port 1 Interrupt Enable P1.7 Intr

0x06 Port 2 Interrupt Enable P2.7 Intr

0x07 Port 3 Interrupt Enable Reserved Reserved Reserved Reserved Reserved Reserved P3.1 Intr

0x08 GPIO Configuration Port 3

GPIO CONFIGURATION PORTS 0, 1, 2 AND 3

0x09 HAPI/I2C Configuration I2C Position Reserved Reserved Reserved Reserved Reserved I2C Port

C

2

I

HAPI

0x10 USB Device Address A Device

0x11 EP A0 Counter

Register

0x12 EP A0 Mode Register Endpoint0

0x13 EP A1 Counter

Register
0x14 EP A1 Mode Register STALL - - ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
0x15 EP A2 Counter

Register
0x16 EP A2 Mode Register STALL - - ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 BBBBBBBB 00000000

Enable

Enable

Enable

Config Bit 1

Address A

Enable

Data 0/1

Toggle

SETUP

Received

Data 0/1

Toggle

Data 0/1

Toggle

P0.6 Intr

Enable

P1.6 Intr

Enable

P2.6 Intr

Enable

Port 3

Config Bit 0

Device

Address A

Bit 6

Data Valid Byte Count

Endpoint0
Received

Data Valid Byte Count

Data Valid Byte Count

P0.5 Intr

Enable

P1.5 Intr

Enable

P2.5 Intr

Enable

Port 2

Config Bit 1

Device

Address A

Bit 5

Bit 5

Endpoint0

IN

OUT

Received

Bit 5

Bit 5

P0.4 Intr

Enable

P1.4 Intr

Enable

P2.4 Intr

Enable

Port 2

Config Bit 0

Device

Address A

Bit 4

Byte Count

Bit 4
ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0

Byte Count

Bit 4

Byte Count

Bit 4

P0.3 Intr

Enable

Reserved P1.2 Intr

P2.3 Intr

Enable

Port 1

Config Bit 1

Device

Address A

Bit 3

Byte Count

Bit 3

Byte Count

Bit 3

Byte Count

Bit 3

P0.2 Intr

Enable

Enable

Reserved Reserved Reserved

Port 1

Config Bit 0

Device

Address A

Bit 2

Byte Count

Bit 2

Byte Count

Bit 2

Byte Count

Bit 2

P0.1 Intr

Enable

P1.1 Intr

Enable

Enable

Port 0

Config Bit 1

Width

Device

Address A

Bit 1

Byte Count

Bit 1

Byte Count

Bit 1

Byte Count

Bit 1

P0.0 Intr

P1.0 Intr

P3.0 Intr

Config Bit 0

Reserved BBBBBBBB 00000000

Address A

Byte Count

Byte Count

Byte Count

Enable

Enable

Enable

Device

CY7C6511

Port 0

Bit 0

Bit 0

Bit 0

Bit 0

oth/–[7]

BBBBBBBB 11111111

BBBBBBBB 11111111

WWWWWWWW 00000000

WWWWWWWW 00000000

WWWWWWWW 00000000

WWWWWWWW 00000000

BBBBBBBB 00000000

BBBBBBBB 00000000

BBBBBBBB 00000000

BBBBBBBB 00000000

BBBBBBBB 00000000

BBBBBBBB 00000000
BBBBBBBB 00000000

Default/

Reset

ENDPOINT A0, AI AND A2 CONFIGURATION

0x1F USB Status and Control Endpoint

CS

USB-

0x20 Global Interrupt Enable Reserved I2C

0x21 Endpoint Interrupt

INTERRUPT

TIMER

C

2

I

ENDPOINT B0, B1 CONFIGURATION

Enable

0x24 Timer (LSB) Timer Bit 7 Timer Bit 6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0 RRRRRRRR 00000000
0x25 Timer (MSB) Reserved Reserved Reserved Reserved Timer Bit 11 Timer Bit 10 Time Bit 9 Timer Bit 8 ----rrrr ----0000

0x28 I2C Control and Status MSTR

0x29 I2C Data I2C Data 7 I2C Data 6 I2C Data 5 I2C Data 4 I2C Data 3 I2C Data 2 I2C Data 1 I2C Data 0 BBBBBBBB XXXXXXXX
0x40 USB Device Address B Device

0x41 EP B0 Counter Register Data 0/1

0x42 EP B0 Mode Register Endpoint 0

0x43 EP B1 Counter Register Data 0/1

0x44 EP B1 Mode Register STALL - - ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 BBBBBBBB 00000000

Size

Reserved Reserved Reserved EPB1

Mode

Address B

Enable

Toggle

SETUP

Received

Toggle

Endpoint

ModeD+UpstreamD–Upstream

Interrupt

Enable

Continue/

Busy

Device

Address B

Bit 6

Data Valid Byte Count

Endpoint 0

IN

Received
Data Valid Byte Count

GPIO

Interrupt

Enable

Xmit

Mode

Device

Address B

Bit 5

Bit 5

Endpoint 0

OUT

Received

Bit 5

Reserved USB Hub

Interrupt

Enable

Device

Address B

Byte Count

Byte Count

Bus Activity Control

Interrupt

Enable

EPB0

Interrupt

Enable

ACK Addr ARB Lost/

Device

Bit 4

Bit 4
ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 BBBBBBBB 00000000

Bit 4

Address B

Bit 3

Byte Count

Bit 3

Byte Count

Bit 3

Bit 2

1.024-ms
Interrupt

Enable

EPA2

Interrupt

Enable

Restart

Device

Address B

Bit 2

Byte Count

Bit 2

Byte Count

Bit 2

Control

Bit 1

128-µs

Interrupt

Enable

EPA1

Interrupt

Enable

Received

Stop

Device

Address B

Bit 1

Byte Count

Bit 1

Byte Count

Bit 1

Control

Bit 0

USB Bus

RESET

Interrupt

Enable

EPA0

Interrupt

Enable

I2C

Enable

Device

Address B

Bit 0

Byte Count

Bit 0

Byte Count

Bit 0

BBRRBBBB -0xx0000

-BBBBBBB -0000000

---

BBBBB ---00000

BBBBBBBB 00000000

BBBBBBBB 00000000

BBBBBBBB 00000000

BBBBBBBB 00000000

Note:

7. B: Read and Write; W: Write; R: Read.

Document #: 38-08002 Rev. *B Page 45 of 51

3
3

19.0 Register Summary (continued)

Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write/B

0x48 Hub Port Connect Status Reserved Port 7

0x49 Hub Port Enable Reserved Port 7

0x4A Hub Port Speed Reserved Port 7

0x4B Hub Port Control (Ports

4:1)

0x4C Hub Port Control (Ports

7:5)

0x4D Hub Port Suspend Device

0x4E Hub Port Resume Status Reserved Resume 7 Resume 6 Resume 5 Resume 4 Resume 3 Resume 2 Resume 1 ­0x4F Hub Port SE0 Status Reserved Port 7

0x50 Hub Ports Data Reserved Port 7

0x51 Hub Port Force Low

(Ports 4:1)

0x52 Hub Port Force Low

(Ports 7:5)

HUB PORT CONTROL, STATUS, SUSPEND RESUME, SE0, FORCE LOW

0xFF Process Status & Control IRQ

Port 4

Control Bi t 1

Reserved Reserved Port 7

Remote

Wakeup

Force Low

D+[4]

Reserved Reserved Force Low

Pending

Connect

Status

Enable

Speed

Port 4

Control Bit 0

Port 7
Selective
Suspend

SE0 Status

Diff. Data

Force Low

D–[4]

Watchdog

Reset

Port 6

Connect

Status
Port 6

Enable

Port 6

Speed

Port 3

Control Bit 1

Control Bit 1

Port 6
Selective
Suspend

Port 6

SE0 Status

Port 6

Diff. Data

Force Low

D+[3]

D+[7]

USB Bus

Reset

Interrupt

Port 5

Connect

Status

Port 5

Enable

Port 5

Speed

Port 3

Control Bit 0

Port 7

Control Bit 0

Port 5

Selective

Suspend

Port 5

SE0 Status

Port 5

Diff. Data

Force Low

D–[3]

Force Low

D–[7]

Power-on

Reset

Port 4

Connect

Status
Port 4

Enable

Port 4

Speed

Port 2

Control Bit 1

Port 6

Control Bit 1

Port 4

Selective

Suspend

Port 4

SE0 Status

Port 4

Diff. Data

Force Low

D+[2]

Force Low

D+[6]

Suspend Interrupt

Port 3

Connect

Status
Port 3

Enable

Port 3

Speed

Port 2

Control Bit 0

Port 6

Control Bit 0

Port 3

Selective

Suspend

Port 3

SE0 Status

Port 3

Diff. Data

Force Low

D–[2]

Force Low

D–[6]

Enable

Sense

Port 2

Connect

Status
Port 2

Enable

Port 2

Speed

Port 1

Control Bit 1

Port 5

Control Bit 1

Port 2
Selective
Suspend

Port 2

SE0 Status

Port 2
Diff. Data

Force Low

D+[1]

Force Low

D+[5]

Reserved Run RBBBBRBB 00010001

Port 1

Connect

Status

Port 1

Enable

Port 1

Speed

Port 1

Control Bit 0

Port 5

Control Bit 0

Port 1

Selective

Suspend

Port 1

SE0 Status

Port 1

Diff. Data

Force Low

D–[1]

Force Low

D–[5]

CY7C6501

CY7C6511

oth/–[7]

BBBBBBBB 00000000

BBBBBBBB 00000000

BBBBBBBB 00000000

BBBBBBBB 00000000

--BBBBBB --000000

BBBBBBBB 00000000

RRRRRRR 00000000

RRRRRRRR 00000000

RRRRRRRR 00000000

BBBBBBBB 00000000

--BBBBBB 00000000

Default/

Reset

Document #: 38-08002 Rev. *B Page 46 of 51

3
3

20.0 Sample Schematic

3.3v Regulator
IN

22x2(R

6.000 MHz

USB-B

Vbus

D­D+

GND

SHELL

Optional

2.2 uF

Vref

1.5K
(R

4.7nF

250 V A C

10M

UUP

)

Vbus

GND

ext

OUT

)

D0­D0+

XTALO

XTALI

GND
GND

Vpp

.01 uF

Vcc

Vref

2.2 uF

.01 uF

Vref

D1­D1+
D2-

D2+
D3-

D3+
D4-

D4+

22x8(R

15K(x8)
(R

UDN

CY7C6501

CY7C6511

USB-A

Vbus
D­D+
GND

USB-A

)

ext

)

Vbus
D­D+
GND

USB-A

Vbus

D­D+
GND

USB-A

POWER

MANAGEMENT

Vbus

D­D+
GND

21.0 Absolute Maximum Ratings

Storage Temperature ...................................................................................................................................–65°C to +150°C

Ambient Temperature with Power Applied..........................................................................................................0°C to +70°C

Supply voltage on V

DC Input Voltage................................................................................................................................... –0.5V to +V

DC Voltage applied to Outputs in High Z State..................................................................................... –0.5V to +V

relative to VSS..............................................................................................................–0.5V to +7.0V

CC

CC
CC

+ 0.5V

+ 0.5V

Power Dissipation.......................................................................................................................................................500 mW

Static Discharge Voltage ............................................................................................................................................> 2000V

Latch-up Current ..................................................................................................................................................... > 200 mA

Max Output Sink Current into Port 0, 1, 2, 3 ................................................................................................................ 60 mA

Max Output Sink Current into DAC[7:2] Pins................................................................................................................ 10 mA

Max Output Source Current from Port 1, 2, 3, 4, 5, 6, 7 .............................................................................................. 30 mA

Document #: 38-08002 Rev. *B Page 47 of 51

CY7C6501

3
3

22.0 Electrical Characteristics

f

= 6 MHz; Operating Temperature = 0 to 70°C, VCC = 4.0V to 5.25V

OSC

Parameter Description Conditions Min. Max. Unit

General

V
V
I

CC

I

SB1

I

ref

I

il

V
V
V
C
I

lo

R
R
R

t

vccs

V
V
Z

R
V
V
V

V

REF
pp

di
cm
se
in

ext
UUP
UDN

UOH
UOL

O

up
ITH
H
OL

OH

Reference Voltage 3.3V ±5% 3.15 3.45 V
Programming Voltage (disabled) –0.4 0.4 V
VCC Operating Current No GPIO source current 50 mA
Supply Current—Suspend Mode 50 µA
V

Operating Current No USB Traffic

REF

[8]

Input Leakage Current Any pin 1 µA

USB Interface

Differential Input Sensitivity | (D+)–(D–) | 0.2 V
Differential Input Common Mode Range 0.8 2.5 V
Single Ended Receiver Threshold 0.8 2.0 V
Transceiver Capacitance 20 pF
Hi-Z State Data Line Leakage 0V < V

< 3.3V –10 10 µA

in

External USB Series Resistor In series with each USB pin 19 21 Ω
External Upstream USB Pull-up Resistor 1.5 kΩ ±5%, D+ to V

REG

External Downstream Pull-down Resis tors 15 kΩ ±5%, downstream USB pins 14.25 15.75 kΩ

Power-on Reset

VCC Ramp Rate Linear ramp 0V to V

CC

[9]

USB Upstream/Downstream Port

Static Output High 15 kΩ ±5% to Gnd 2.8 3.6 V
Static Output Low 1.5 kΩ ±5% to V
USB Driver Output Impedance Including R

REF

Resistor 28 44 Ω

ext

General Purpose I/O (GPIO)

Pull-up Res istance (typical 14 kΩ) 8.0 24.0 k Ω
Input Threshold Voltage All ports, low-to-high edge 20% 40% V
Input Hysteresis Voltage All ports, high-to-low edge 2% 8% V
Port 0,1,2,3 Output Low Voltage IOL = 3 mA

= 8 mA

I

OL

Output High V ol t ag e IOH = 1.9 mA (all ports 0,1,2,3) 2.4 V

CY7C6511

10 mA

1.425 1.575 kΩ

0100ms

0.3 V

0.4

2.0

CC
CC

V
V

23.0 Switching Characteristics (f

= 6.0 MHz)

OSC

Parameter Description Min. Max. Unit

Clock Source

f

OSC

t

cyc

t

CH

t

CL

t

rfs

t

ffs

t

rfmfs

Notes:

8. Add 18 mA per driven USB cable (upstream or downstream. This is based on transitions every 2 full-speed bit times on average.

9. Power-on Reset occurs whenever the voltage on V

10. Per Table 7-6 of revision 1.1 of USB specification.

Clock Rate 6 ±0.25% MHz
Clock Period 166.25 167.08 ns
Clock HIGH time 0.45 t
Clock LOW time 0.45 t

USB Full-speed Signaling

[10]

CYC
CYC

ns
ns

Transition Rise Time 4 20 ns
Transition Fall Time 4 20 ns
Rise/Fall Time Matching; (tr/tf) 90 111 %

is below approximately 2.5V.

CC

Document #: 38-08002 Rev. *B Page 48 of 51

CY7C6501

3
3

48-lead Shrunk Small Outline Package O48

CY7C6511

23.0 Switching Characteristics (f

t

dratefs

Full Speed Date Rate 12 ±0.25% Mb/s

= 6.0 MHz) (continued)

OSC

Timer Signals

t

watch

Watchdog Timer Period 8.192 14.336 ms

t

CYC

t

CH

CLOCK

t

CL

t

r

10%

D+

D−

10%

t

r

90%

90%

24.0 Ordering Information

Ordering Code PROM Size Package Name Package Type Operating Range

CY7C65013-PVC 8 KB O48 48-pin (300-Mil) SSOP Commercial
CY7C65113-SC 8 KB S21 28-pin SOIC Commercial
CY7C65013-PC 8 KB P25 48-pin (600 Mil) PDIP Commercial
CY7C65113-PC 8 KB P21 28-pin (300-Mil) PDIP Commercial

25.0 Package Diagrams

51-85061-*C

Document #: 38-08002 Rev. *B Page 49 of 51

3
3

25.0 Package Diagrams (continued)

28-lead (300-Mil) Molded DIP P21

48-lead (600-Mil) Molded DIP P25

CY7C6501

51-85014-*B

CY7C6511

51-85020-*A

28-lead (300-Mil) Molded SOIC S21

51-85026-*A

Purchase of I2C components from Cypress, o r one of its s ublicensed Associated Com panies, c onveys a lic ense under the Philips
I2C Patent Rights to u se these component s in an I2C system, provided th at the system con forms to the I2C St andard Specifica tion
as defined by Philip s. All product and comp any names menti oned in this document are the trademarks of their resp ective holders.

Document #: 38-08002 Rev. *B Page 50 of 51

© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other ri ghts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C6501

3
3

Document History Page

Document Title: CY7C65013/CY7C65113 USB Hub with Microcontroller
Document Number: 38-08002

REV. ECN NO. Issue Date

** 109965 02/22/02 SZV Change from Spec number: 38-00590 to 38-08002

*A 120372 12/17/02 MON Added register bit definitions.

*B 124522 03/13/03 MON Fixed the figure on page 42 regarding the update of mode registers. The

Orig. of

Change Description of Change

Added default bit state of each regi ster.
Corrected the Schematic (location of the pull-up on D+).
Corrected the Logical Diagram (removed the extra GPIO Port 1).
Added register summary.
Modified Figure 17-5, more labeling.
Removed information on the availability of the part in PDIP package.
Modified Table 18-1 and provided more explanation regarding
locking/unlocking mechanism of the mode register.
Removed any inform ation regar ding the spe ed detect b it in Hub Port Speed
register being set by hardware.

arrows in the figure were misplaced and the figure was unreadable. This is
an important figure for understanding mode register functioning.

CY7C6511

Document #: 38-08002 Rev. *B Page 51 of 51