Datasheet CY7C65013, CY7C65113 Datasheet (CYPRESS)

1July 6,
200100CY7C65013

CY7C65013
CY7C65113

CY7C65013
CY7C65113
USB Hub with Microcontroller

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

July 6, 2001

CY7C65013
CY7C65113

TABLE OF CONTENTS

1.0 FEATURES .............................................. .............................. ........................... ..............................5

2.0 FUNCTIONAL OVERVIEW ....................................... .. ...................................... ..............................6

3.0 PIN CONFIGURATIONS ... ........................... .. .. ........................... .. .. .. ........................... ...................8

4.0 PRODUCT SUMMARY TABLES ............... .. .... ................................. ................................ .. .. .. .. .. ....9

4.1 Pin Assignme n ts ...... .. ............... ... ............... .. ................ ............... .. ................ .. .............................9

4.2 I/O Registe r Summary ........... ................ .. ............... ................ .. ............... ................ .. ....................9

4.3 Instruction Set Summary ............................................................................................................ 11

5.0 PROGRAMM I N G M OD E L ....... .. ................ .. ............... ... ............... ................ .. ............... .. ..............12

5.1 14-Bit Program Counter (PC) ......................................................................................................12

5.1.1 Program Memory Organization .........................................................................................................13

5.2 8-Bit Accumulator (A) ..................................................................................................................14

5.3 8-Bit Temporary Register (X) ......................................................................................................14

5.4 8-Bit Program Stack Pointer (PSP) ............................................................................................14

5.4.1 Data Memory Organization ................................................................................................................14

5.5 8-Bit Data Stack Pointer (DSP) ...................................................................................................15

5.6 Address Modes ............................................................................................................................15

5.6.1 Data (Immediate) .................................................................................................................................15

5.6.2 Direct ...................................................................................................................................................15

5.6.3 Indexed ................................................................................................................................................15

6.0 CLOCKING ....................................................................................................................................16

7.0 RESET .................................. .. .......................... ......................... .. .. ................................................16

7.1 Power-On Reset (POR) ................................................................................................................16

7.2 Watch Dog Reset (WDR) .............................................................................................................17

8.0 SUSPEND MODE ............................ .. .. .. .................................. .. .. .. .. ..............................................17

9.0 GENERAL-PURPOSE I/O (GPIO) PORTS ............................................................ .. .....................18

9.1 GPIO Configuration Port .............................................................................................................19

9.2 GPIO Interrupt Enable Ports ............................. ................... .......................................................20

10.0 12-BIT FREE-RUNNING TIMER ......................... .. ............................................... .. .....................20

10.1 Timer (LSB ) ............. ............... .. ................ .. ................ ............... .. ................ .. .............................20

10.2 Timer (MSB) ...... ................ .. ............... ................ .. ............... ... ............... .. ................ ....................20

2

11.0 I

12.0 I

C CONFIGURATION REGISTER ..............................................................................................21

2

C COMPATIB L E CO N T R O L L ER ........... .. .. ................ ............... .. ................ .. ................ .. .........21

13.0 PROCESSOR STATUS AND CONTROL REGISTER ............................ ...................................23

14.0 INTERRUPTS .................................... .. ..................................................... ...................................24

14.1 Interrup t V e c to r s ............................. .. ................ .. ............... ................ .. ................ .. ....................24

14.2 Interrupt Latency .......................................................................................................................26

14.3 USB Bus Reset Interrupt ...........................................................................................................26

14.4 Timer Inter rupt .............. ... ............... ................ .. ............... .. ................ ............... ... ......................26

14.5 USB Endpoint Interrupts ...........................................................................................................26

14.6 USB Hub Interrupt .....................................................................................................................26

14.7 GPIO Interrupt ............................................................................................................................27

2

14.8 I

C Interrupt ............... ............... ................ .. ................ ............... .. ................ ............... .. . .............27

15.0 USB OVERVIEW .........................................................................................................................28

2

CY7C65013
CY7C65113

15.1 USB Serial Interface Engine (SIE) ........................ .................. .. .................. .. ............................28

15.2 USB Enumeration ......................................................................................................................28

16.0 USB HUB ....................................................................................................................................29

16.1 Connecting/Disconnecting a USB Device .......................................................... .....................29

16.2 Enabling/Disabling a USB Device ............................................................................................29

16.3 Hub Downstream Ports Status and Control .................................................... ........................30

16.4 Downstream Port Suspend and Resume .......... .. .. ....................... .. .........................................31

16.5 USB Upstream Port Status and Control .............................................................................. ....32

17.0 USB SERIAL INTERFACE ENGINE OPERATION ....................................................................33

17.1 USB Device Addresses .............................................................................................................33

17.2 USB Device Endpoints ..............................................................................................................33

17.3 USB Control Endpoint Mode Registers ...................................................................................34

17.4 USB Non-Control Endpoint Mode Registers ............................. ..............................................34

17.5 USB Endpoint Counter Registers ............................................................................................35

17.6 Endpoint Mode/Count Registers update and Locking Mechanism ......................................35

18.0 USB MODE TABLES ..................................................................................................................37

19.0 SAMPLE SCHEMATIC ................................................................................................................41

20.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................42

21.0 ELECTRICAL CHARACTERISTICS ................... .. .. .. ........................... ........................... ............42

22.0 SWITCHING CHARACTERISTICS ............................................. .. .. ............................. .. .............43

23.0 ORDERING INFORMATION .......................................................................................................43

24.0 PACKAGE DIAGRAMS ........................... .. .. .. ........................... .. .. ........................... ...................44

LIST OF FIGURES

Figure 5-1. Program Memory Space with Interrupt Vector Table .................. .................... ............13

Figure 6-1. Clock Oscillator On-Chip Circuit ................. .................... ...................................... ........16

Figure 7-1. Watch Dog Reset (WDR) ................................... .................. ...........................................17

Figure 9-1. Block Diagram of a GPIO Pin ...................................................... ...................... .. ..........18

Figure 9-2. Port 0 Data 0x00 (read/write) ................................ .. .......................................................18

Figure 9-3. Port 1 Data 0x01 (read/write) ................................ .. .......................................................18

Figure 9-4. Port 2 Data 0x02 (read/write) ................................ .. .......................................................18

Figure 9-5. Port 3 Data 0x03 (read/write) ................................ .. .......................................................18

Figure 9-6. GPIO Configuration Register 0x08 (read/write) .................... .................... ...................19

Figure 9-7. Port 0 Interrupt Enable 0x04 (read/write) .............. .................... .................. .. ...............20

Figure 9-8. Port 1 Interrupt Enable 0x05 (read/write) .............. .................... .................. .. ...............20

Figure 9-9. Port 2 Interrupt Enable 0x06 (read/write) .............. .................... .................. .. ...............20

Figure 9-10. Port 3 Interrupt Enable 0x07 (read/write) ............. ......................................................20

Figure 10-1. Timer Register 0x24 (read only) .................................. .................... .................... .. ......20

Figure 10-2. Timer Register 0x25 (read only) .................................. .................... .................... .. ......20

Figure 10-3. Timer Block Diagram .............................. ...................... .. ...................... ........................21

Figure 11-1. I
Figure 12-1. I
Figure 12-2. I

2

C Configuration Register 0x09 (read/write) .............................................................21

2

C Data Register 0x29 (separate read/write registers) ................................ .............22

2

C Status and Control Register 0x28 (read/write) ....................................................22

Figure 13-1. Processor Status and Control Register 0xFF ............................................................23

Figure 14-1. Global Interrupt Enable Register 0x20 (read/write) ...................................................24

Figure 14-2. USB Endpoint Interrupt Enable Register 0x21 (read/write) ......................................24

3

CY7C65013
CY7C65113

Figure 14-3. Interrupt Controller Functional Diagram ....................................................................25

Figure 14-4. Interrupt Vector Register 0x23 (read only) .................................................................26

Figure 14-5. GPIO Interrupt Structure ..............................................................................................27

Figure 16-1. Hub Ports Connect Status 0x48 (read/write), 1 = connect, 0 = disconnect .............29

Figure 16-2. Hub Ports Speed 0x4A (read/write), 1 = Low-Speed, 0 = Full-Speed ........... ............29

Figure 16-3. Hub Ports Enable Register 0x49 (read/write), 1 = Enabled, 0 = Disabled ................30

Figure 16-4. Hub Downstream Ports Control Register 0x4B (read/write) ................ .....................30

Figure 16-5. Hub Ports Force Low Register (read/write) 0x51, 1 = Force Low, 0 = no force ......31

Figure 16-6. Hub Ports Force High Register (read/write) 0x52, 1=For ce High, 0=no force .........31

Figure 16-7. Hub Ports SE0 Status Register 0x4F (read only), 1 = SE0, 0 = non-SE0 .................31

Figure 16-8. Hub Ports Data Register 0x50 (read only), 1 = (D+ > D–), 0 = (D+ < D–) ..................31

Figure 16-9. Hub Ports Suspend Register 0x4D (read/write),

1 = Port is Selectively Suspended ............................. ..................................................... ...................31

Figure 16-10. Hub Ports Resume Status Register 0x4E (read only),

1 = Port is in Resume State ............... ................................................................................................. 32

Figure 16-11. USB Status and Control Register 0x1F (read/write) ................ .. ...................... .. ......32

Figure 17-1. USB Device Address Registers 0x10, 0x40 (read/write) ...................... .................... .33

Figure 17-2. USB Device Endpoint Zero Mode Registers 0x12 and 0x42, (read/write) ...............34

Figure 17-3. USB Non-Control Device Endpoint Mode Registers

0x14, 0x16, 0x44, (read/write) ............................... ................................................... ..........................35

Figure 17-4. USB Endpoint Counter Registers 0x11, 0x13, 0x15, 0x41, 0x43 (read/wri te) ..........35

Figure 17-5. Token/Data Packet Flow Diagram ................................... .................... .................... .. ..36

Figure 22-1. Clock Timing .................................... ...................... .......................................................43

Figure 22-2. USB Data Signal Timing ............................................. .................... .. .................... ........43

LIST OF TABLES

Table 4-1. Pin Assignments ............. .................... ........................................ .................... .. .................9

Table 4-2. I/O Register Summary ............................................................................ ............................9

Table 4-3. Instruction Set Summary .............................................................. ...................................11

Table 9-1. Port Configurations .................................................. ................ .......................................19

Table 11-1. I
Table 12-1. I

2

C Port Config u r a tio n .... .. ............... ................ .. ............... ... ............... .. ................ .........21

2

C Status and Control Register Bit Definitions ..........................................................22

Table 14-1. Interrupt Vector Assignments ................................. ................................... ...................25

Table 16-1. Control Bit Definition for Downstream Ports ....................... .......................................30

Table 16-2. Control Bit Definition for Upstream Port ................. ....................................... .............33

Table 17-1. Memory Allocation for Endpoints ........................................... .. .................... ...............34

Table 18-1. USB Register Mode Encoding ............................................................ .. ........................37

Table 18-2. Decode table for

Table 18-3

: “Details of Modes for Differing Traffic Conditions” ...38

Table 18-3. Details of Modes for Differing Traffic Conditions ..................................................... ..39

4

CY7C65013
CY7C65113

1.0 Features

• USB Hub with an integrated microcontroller

• 8-bit USB Optimized Microcontroller
—Harvard architecture

—6-MHz external clock source
—12-MHz internal CPU clock
—48-MHz internal Hub clock

• Internal memory
—256 bytes of RAM
—8 KB of PROM

• Integrated Master/Slave I

•I/O ports
—Three GPIO ports (Port 0 to 2) capable of sinking 7 mA per pin (typical)

—An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs
—Higher current drive achievable by connecting multiple GPIO pins together to drive a common output
—Each GPIO port can be configure d as inputs with internal pull-ups or open drain outputs o r traditional CMOS outputs
—Maskable interrupts on all I/O pins

• 12-bit free-running timer with one microsecond clock ticks

• Watch Dog Timer (WDT)

• Internal Power-On Reset (POR)

• USB Specification Compliance
—Conforms to USB Specification, Version 1.1

—Conforms to USB HID Specification, Version 1.1
—Supports one or two device addresses with up to 5 user-configured endpoints

Up to two 8-byte control endpoints
Up to four 8-byte data endpoints

Up to two 32-byte data endpoints
—Integrated USB transceivers
—Supports 7 (CY7C65013) or 4 (CY7C65113) Downstream USB ports
—GPIO pins can provide individual power control outputs for each Downstream USB port
—GPIO pins can provide individual port over current inputs for each Downstream USB port

• Improved output drivers to reduce EMI

• Operating voltage from 4.0V to 5.5V DC

• Operating temperature from 0 to 70 degrees Celsius

• CY7C65013 available in 48-pin PDIP (-PC) or 48-pin SSOP (-PVC) packages

• CY7C65113 available in 28-pin SOIC (-SC) or 28-pin PDIP (-PC) packages

• Industry standard programmer support

2

C compatible Controller (100 kHz) enabled through General-Purpose I/O (GPIO) pins

5

CY7C65013
CY7C65113

2.0 Functional Overview

The CY7C65x13 devices are One Time Programmable 8-bit microcontrollers with a built-in 12-Mbps USB hub that supports up
to seven downstre am ports. The mi cro con trol ler instruction set has be en optimized speci fic al ly for USB opera tio ns, although the
microcontrollers can be used for a variety of non-USB embedded applications.

The CY7C65013 f eature s 22 GPIO pi ns to sup port USB and other applica tions . The I/O pins are gro uped into f o ur ports (P0[7:0],
P1[7:4,2:0], P2[7:3], P3[1:0]) where eac h port can be configured as inputs with internal pull-ups, ope n drain outputs , or trad itional
CMOS outputs. Ports 0 to 2 are rated at 7 mA per pin (typical) sink current. Port 3 pins are rated at 12 mA per pin (typical) sink
current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more
drive current cap ac ity. Additionally, each I/O pin can be used to gener a te a G PIO in terrupt to th e m ic roc ontro ll er. All of the GPIO
interrupts all share the same “GPIO” interrupt vector.

The CY7C65113 has 11 GPIO pins (P0[7:0], P1[2:0]), both rated at 7 mA per pin (typical) sink current. Multiple GPIO pins can
be connected together to drive a single output for more drive current capacity.

The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal PLL-based
clock generator . This technolog y allows the custom er application to use an inexpensive 6-MHz fu nda me ntal c rystal that r edu ces
the clock-related noise emissions (EMI). A PLL clock generator provides the 6-, 12-, and 48-MHz clock signals for distribution
within the microcontroller.

The CY7C65013 and the CY7C65113 are offered with 8 KB of PROM.
These parts include power-on reset logic, a watch dog timer, and a 12-bit free-running timer. The Power-On Reset (POR) logic

detects when po wer is app lied to the de vice , resets the logic to a k nown state , and beg ins ex ecutin g instructions at PROM add ress
0x0000. The watch dog timer is used to ensure the microcon troller reco vers aft er a period of inactivity. The firmware may becom e
inactive f or a va riety of reasons, inclu ding errors in the co de or a hardware f ailure such as waiting f or an interrupt that n ev er occurs.

2

The microcontroller can communicate with external electronics through the GPIO pins. An I
dates a 100-kHz serial link with an external device.

The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-µs and 1.024-ms. The timer can be used to
measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is
complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of
the timer are latched into an in ternal register when the firmware rea ds the low er eight bits . A read from the upper f our bits actually
reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if
the upper four bits increment immediately after the lower eight bits are read.

The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus
Reset interrupt, the 12 8-µs (bi t 6) an d 1.0 24-ms (bit 9 ) outpu ts from the free-runn ing ti mer, five USB endpoints, the USB hu b, the
GPIO ports, and the I
from LOW ‘0’ to HIGH ‘1’. The USB endpo ints interrupt after the USB host has written data to th e endpoint FIFO or after the USB
controller sends a packet to the USB host. The GPIO ports also have a level of masking to select which GPIO inputs can cause
a GPIO interrupt. Input tra nsi tio n po larity c an be programmed f o r eac h GP IO port as part of the port configuration. The in terrupt
polarity can be rising edge (‘0’ to ‘1’) or falling edge (‘1’ to ‘0’).

The CY7C65013 and CY7C65113 include an integrated USB Serial Interface Engine (SIE) that supports the integrated periph­erals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the
hub (two endpoint s) and a de vice address f or a compound device (three endpoints ). The SIE allow s the USB host to com municate
with the hub and funct ions integrate d into the microcontro ller. T he CY7C65113 part includes a 1 :4 hub repeater with one u pstream
port and four dow nstream ports, while the CY7C65013 pa rt includes a 1:7 hub repeater . The USB Hub allows po wer manage ment
control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the
downstream ports together with a singl e pair of po wer manag ement pins , or prov iding po wer mana gement f or eac h port with four
(CY7C65113) or seven (CY7C65013) pairs of power management pins.

2

C compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles

C compatible in terface acc ommo-

6

.

Logic Block Diagram

CY7C65013
CY7C65113

6-MHz crys tal

PLL

48 MHz

Clock

Divider

12 MHz

6 MHz

12-MHz

8-bit

CPU

PROM

8 KB

RAM

256 byte

12-bit
Timer

8-bit Bus

USB

SIE

Interrupt

Controller

GPIO

PORT 0

USB

Transceiver

Repeater

P0[0]

P0[7]

D+[0]

Upstream
USB Port

D–[0]

Downstream USB Ports

USB

Transceiver

USB

Transceiver

USB

Transceiver

USB

Transceiver

CY7C65013 only

Power management under firmware
control using GPIO pins

D+[1]
D–[1]

D+[4]
D–[4]

D+[5]
D–[5]

D+[7]
D–[7]

Watch Dog

Timer

Power-On

Reset

GPIO

PORT 1

GPIO

PORT 1

GPIO

PORT 2

GPIO

PORT 3

I2C comp.
Interface

2

C Compatible interface enabled by firmware through

*I

P2[1:0] or P1[1:0]

P1[0]

P1[2]

P1[7:4]

P2[7]

P2[3]

High Current

P3[1]

Outputs

P3[0]

CY7C65013 only

SCLK
SDATA

7

3.0 Pin Configurations

XTALOUT

XTALIN

CY7C65013

48-pin SSOP/48 PDIP

1

48

2

47
46

GND

REF

GND

3
4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25

45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

P1[1]
P1[5]
P1[7]
P3[1]
D+[0]
D–[0]

D+[1]
D–[1]
V
D+[2]
D–[2]
P2[3]

P2[5]
D+[7]
D–[7]
P2[7]
P0[7]
P0[5]
P0[3]
P0[1]

TOP VIEW

V

CC

P1[0]
P1[2]
P1[4]
P1[6]
P3[0]
D–[3]
D+[3]

GND
D–[4]
D+[4]
V

REF

D–[5]
D+[5]
GND
P2[4]
D–[6]
D+[6]
P2[6]
V

PP

P0[0]
P0[2]
P0[4]
P0[6]

CY7C65113

28-pin SOIC/PDIP

XTALOUT

XTALIN

V

REF

GND
D+[0]
D–[0]
D+[1]
D–[1]
D+[2]
D–[2]
P0[7]
P0[5]
P0[3]
P0[1]

CY7C65013
CY7C65113

1

28

V
2
3
4

5
6
7
8
9
10
11
12
13
14

CC

27

P1[1]

26

P1[0]

P1[2]

25

D–[3]

24

D+[3]

23

D–[4]

22

D+[4]

21

GND

20
19

V

PP

18

P0[0]

17

P0[2]

P0[4]

16
15

P0[6]

8

4.0 Product Summary Tables

4.1 Pin Assignments

Table 4-1. Pin Assignments

Name I/O 48-Pin 28-Pin Description

D+[0], D–[0] I/O 7, 8 5, 6 Upstream port, USB differential data.
D+[1], D–[1] I/O 10, 11 7, 8 Downstream Port 1, USB differential data.
D+[2], D–[2] I/O 13, 14 9, 10 Downstream Port 2, USB differential data.
D+[3], D–[3] I/O 41, 42 23, 24 Downstream Port 3, USB differential data.
D+[4], D–[4] I/O 38, 39 21, 22 Downstream Port 4, USB differential data.
D+[5], D–[5] I/O 35, 36 Downstream Port 5, USB differential data.
D+[6], D–[6] I/O 31, 32 Downstream Port 6, USB differential data.
D+[7], D–[7] I/O 18, 19 Downstream Port 7, USB differential data.
P0 I/O P1[7:0]

P1 I/O P1[7:4,2:0]

P2 I/O P2[7:3]

P3 I/O P3[1:0]

XTAL

IN

XTAL

OUT

V

PP

V

CC

GND 9, 16, 34, 40 4, 20 Ground.
V

REF

OUT 1 1 6-MHz crystal out.

21, 25, 22, 26,
23, 27, 24, 28

5, 44, 4, 45;

46, 3, 47

20, 30, 17,

33, 15

6, 43

IN 2 2 6-MHz crystal or external clock input.

29 19 Programming v oltage sup ply, tie to ground during no rmal operatio n.
48 28 V olta ge su ppl y.

IN 12, 37 3 External 3.3V supply voltage for the downstream differential data

P1[7:0]

11, 15, 12, 16,

13, 17, 14, 18

P1[2:0]

25, 27, 26

GPIO Port 0 capable of sinking 7 mA (typical).

GPIO Port 1 capable of sinking 7 mA (typical).

GPIO Port 2 capable of sinking 12 mA (typical).

GPIO Port 3, capable of sinking 12 mA (typical).

output buffers and the D+ pull up.

CY7C65013
CY7C65113

4.2 I/O Register Summary

I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IO WX) instructio ns. IORD reads data from the selected
port into the accumulator. IOWR performs the reverse; it writes da ta from the ac cum ulato r to the selec ted po rt. Indexed I/O Write
(IOWX) adds the contents of X t o the address in the instructi on to form the port address and writes data from the accumulat or to
the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X.

All undefined registers are reserved. Do not write to reserved registers as this may cause an undefined operation or increased
current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with ‘0.’

Table 4-2. I/O Register Summary

Register Name I/O Address Read/Write Function Page

Port 0 Data 0x00 R/W GPIO Port 0 Data 18
Port 1 Data 0x01 R/W GPIO Port 1 Data 18
Port 2 Data 0x02 R/W GPIO Port 2 Data 18
Port 3 Data 0x03 R/W GPIO Port 3 Data 18
Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 20
Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 20
Port 2 Interrupt Enable 0x06 W Interrupt Enable for Pins in Port 2 20

9

CY7C65013
CY7C65113

Table 4-2. I/O Register Summary (continued)

Register Name I/O Address Read/Write Function Page

Port 3 Interrupt Enable 0x07 W Interrupt Enable for Pins in Port 3 20
GPIO Configuration 0x08 R/W GPIO Port Configurations 19

2

C Configuration 0x09 R/W I2C Positi on Configuration 21

I
USB Device Address A 0x10 R/W USB Device Address A 33
EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 Counter 35
EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 Configuration 34
EP A1 Counter Register 0x13 R/W USB Address A, Endpoint 1 Counter 35
EP A1 Mode Register 0x14 R/W USB Address A, Endpoint 1 Configuration 35
EP A2 Counter Register 0x15 R/W USB Address A, Endpoint 2 Counter 35
EP A2 Mode Register 0x16 R/W USB Address A, Endpoint 2 Configuration 35
USB Status & Control 0x1F R/W USB Upstream Port Traffic Status and Control 32
Global Interrupt Enable 0x20 R/W Global Interrupt Enable 24
Endpoint Interrupt Enable 0x21 R/W USB Endpoint Interrupt Enables 24
Interrupt Vector 0x23 R Pending Interrupt Vector Read/Clear 25
Timer (LSB) 0x24 R Lower 8 Bits of Free-running Timer (1 MHz) 20
Timer (MSB) 0x25 R Upper 4 Bits of Free-running Timer 20
WDT Clear 0x26 W Watch Dog Timer Clear 17

2

C Control & Status 0x28 R/W I2C Status and C ontrol 22

I

2

C Data 0x29 R/W I2C Data 22

I

Reserved 0x30 Reserved
Reserved 0x31 Reserved
Reserved 0x32 Reserved
Reserved 0x38-0x3F Reserved

USB Device Address B 0x40 R/W USB Device Add r es s B (no t us ed in 5-endpoint mode) 33
EP B0 Counter Register 0x41 R/W USB Address B, Endpoint 0 Counter 35
EP B0 Mode Register 0x42 R/W USB Address B, Endpoint 0 Configuration, or

EP B1 Counter Register 0x43 R/W USB Address B, Endpoint 1 Counter 35
EP B1 Mode Register 0x44 R/W USB Address B, Endpoint 1 Configuration, or

Hub Port Connect Status 0x48 R/W Hub Downstream Port Connect Status 29
Hub Port Enable 0x49 R/W Hub Downstream Ports Enable 30
Hub Port Speed 0x4A R/W Hub Downstream Ports Speed 29
Hub Port Control (Ports [4:1]) 0x4B R/W Hub Downstream Ports Control (Ports [4:1]) 30
Hub Port Control (Ports [7:5]) 0x4C R/W Hub Downstream Ports Control (Ports [7:5]) 30
Hub Port Suspend 0x4D R/W Hub Downstream Port Suspend Control 31
Hub Port Resume Status 0x4E R Hub Downstream Ports Resume Status 32
Hub Ports SE0 Status 0x4F R Hub Downstream Ports SE0 Status 31
Hub Ports Data 0x50 R Hub Downstream Ports Differential Data 31
Hub Downstream Force Low 0x51 R/W Hub Downstream Ports Force LOW (Ports [1:4]) 31
Hub Downstream Force High 0x52 R/W Hub Downstream Ports Force HIGH (Ports [5:7]) 31
Processor Status & Control 0xFF R/W Microprocessor Status and Control Register 23

USB Address A, Endpoint 3 in 5-endpoint mode

USB Address A, Endpoint 4 in 5-endpoint mode

34

35

10

CY7C65013
CY7C65113

4.3 Instruction Set Summary

Refer to the CYASM Assembler User’s Guide for more details.

Table 4-3. Instruction Set Summary

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles

HALT 00 7 NOP 20 4
ADD A,expr data 01 4 INC A acc 21 4
ADD A,[expr] direct 02 6 INC X x 22 4
ADD A,[X+expr] index 03 7 INC [expr] direct 23 7
ADC A,expr data 04 4 INC [X+expr] index 24 8
ADC A,[expr] direct 05 6 DEC A acc 25 4
ADC A,[X+expr] index 06 7 DEC X x 26 4
SUB A,expr data 07 4 DEC [expr] direct 27 7
SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8
SUB A,[X+expr] index 09 7 IORD expr address 29 5
SBB A,expr data 0A 4 IOWR expr address 2A 5
SBB A,[expr] direct 0B 6 POP A 2B 4
SBB A,[X+expr] index 0C 7 POP X 2C 4
OR A,expr data 0D 4 PUSH A 2D 5
OR A,[expr] direct 0E 6 PUSH X 2E 5
OR A,[X+expr] index 0F 7 SWAP A,X 2F 5
AND A,expr data 10 4 SWAP A,DSP 30 5
AND A,[expr] direct 11 6 MOV [expr],A direct 31 5
AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6
XOR A,expr data 13 4 OR [expr],A direct 33 7
XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8
XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7
CMP A,expr data 16 5 AND [X+expr],A index 36 8
CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7
CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8
MOV A,expr data 19 4 IOWX [X+expr] index 39 6
MOV A,[expr] direct 1A 5 CPL 3A 4
MOV A,[X+expr] index 1B 6 ASL 3B 4
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[expr] direct 1D 5 RLC 3D 4
reserved 1E RRC 3E 4
XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50-5F 10 JC addr C0-CF 5
JMP addr 80-8F 5 JNC addr D0-DF 5
CALL addr 90-9F 10 JACC addr E0-EF 7
JZ addr A0-AF 5 INDEX addr F0-FF 14
JNZ addr B0-BF 5

11

CY7C65013
CY7C65113

5.0 Programming Model

5.1 14-Bit Program Counter (PC)

The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C65x13 architecture. The top
32 bytes of the R O M in th e 8K part are reserved for testing purposes. T he pr ogr am c ounter is cle ared du ring reset, s uch that th e
first instruction executed after a reset is at address 0x0000h. Typically, this is a jump instruction to a reset handler that initializes
the application (see Interrupt Vectors on page 24).

The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the
program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte
“page” of sequential code sh ould be an XPAGE instruction. The assemb ler di rective “XPAGEON” causes the asse mb l er to insert
XPAGE instructions automatically. Because instructions can be either one or two bytes long, the assembler may occasionally
need to inse rt a NOP followed by an XPAGE to execute cor rectly.

The address of the next instructio n t o b e exec ute d, the c arry flag, a nd the zero flag are s aved as two bytes o n t he program stack
during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the
program stack during a RETI in struction. Only the program counter is restored during a RET instruction.

The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from
location 0x00 and up.

12

5.1.1 Program Memory Organization

after reset Address

14-bit PC 0x0000 Program execution begins here after a reset

CY7C65013
CY7C65113

0x0002 USB Bus Reset interrupt vector

0x0004 128-µs timer interrupt vector

0x0006 1.024-ms timer interrupt vector

0x0008 USB address A endpoint 0 interrupt vector

0x000A USB address A endpoint 1 interrupt vector

0x000C USB address A endpoint 2 interrupt vector

0x000E USB address B endpoint 0 interrupt vector

0x0010 USB address B endpoint 1 interrupt vector

0x0012 Hub interrupt vector

0x0014 Reserved

0x0016 GPIO interrupt vector

0x0018

0x001A

I2C interrupt vector

Program Memory begins here

0x1FDF

Figure 5-1. Program Memory Space with Interrupt Vector Table

8 KB (-32) PROM ends here (CY7C65013, CY7C65113)

13

CY7C65013
CY7C65113

5.2 8-Bit Accumulator (A)

The accumulator is the general-purpose register for the microcontroller.

5.3 8-Bit Temporary Register (X)

The “X” register i s av ailable t o the firmware f or temp orary storage of intermediate resul ts. The mi crocontroller c an perf orm indexed
operations based on the value in X. Refer to Section 5.6.3 for additional information.

5.4 8-Bit Program Stack Pointer (PSP)

During a reset, the Program Stack Pointer (PSP) is set to 0x00 and “grows” upward from this address. The PSP may be set by
firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and
RETI instructions under firmware control. The PSP is not readable by the firmware.

During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as
two bytes of data memory. The first byte is st ored in the memory addressed b y the PSP, then the PSP is incre mented. The sec ond
byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program
counter and flags on the program “stack” and increment the PSP by two.

The Return From Interrupt (RETI) instruction decrements the PSP, then restores the second byte from memory addressed by the
PSP. The PSP is decremented again and the first b yte is restored fro m memory addressed b y the PSP. After the program counter
and flags ha v e been res tored from stac k, the interrupts are e nab led. Th e ov er all eff ec t is to res tore the p rogr am cou nter and flags
from the program stack, decrement the PSP by two, and re-enable interrupts.

The Call Subroutine (CALL) instruction st ores the program counter and flags on the program stack an d increments the PSP by two .
The Return From Subroutine (RET) instruction restores the program counter but not the flags from the program stack and

decrements the PSP by two.

5.4.1 Data Memory Organization

The CY7C65x13 microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program
stack, user v ariab le s, da ta stac k, and U SB endpo int FIFOs . The f ollowi ng is on e e xampl e of wher e the prog ram stac k, data stac k,
and user variables areas could be located.

After reset Address

8-bit DSP 8-bit PSP 0x00

(Move DSP

8-bit DSP

Notes:

1. Refer to Section 5.5 for a description of DSP.

2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Tabl e 17 -1.

[1]

)

user selected

User variables

USB FIFO space for up to two Ad dresses and five endpo ints

0xFF

Program Stack Growth

Data Stack Growth

[2]

14

CY7C65013
CY7C65113

5.5 8-Bit Data Stack Pointer (DSP)

The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
instructi on pre -decrem ents th e DSP, then writ es dat a to the memor y loc ation ad dressed by the DS P. A POP in struc tion rea ds
data from the memory location addressed by the DSP, then post-increments the DSP.

During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM
(address 0xFF). This writes data to the memory area reserved for USB endpoint FIFOs. Therefore, the DSP should be indexed
at an appropriate memory location that does not compromise the Program Stack, user-defined memory (variables), or the USB
endpoint FIFOs.

For USB appli cations , the fi rmware should set the DSP to an appropriate location to a vo id a memory conflict w ith RAM de dicated
to USB FIFOs. The memory requirements for the USB endpoints are described in Se ction 17.2. Example assembly instructions
to do this with two device addresses (FIFOs begin at 0xD8) are shown below:

MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less)
SWAP A,DSP ; swap accumulator value into DSP register

5.6 Address Modes

The CY7C65013 and CY7C6 511 3 mi crocontrollers support three addressing mode s for instructions that req uire data operands:
data, direct, and indexed.

5.6.1 Data (Immediate)

“Data” address mode ref ers to a da ta oper and that is actual ly a c onstant e ncode d in the instructi on. As a n example, c onsid er the
instruction that loads A with the constant 0xD8:

• MOV A,0D8h

This instruction requi res two bytes o f code where the first b yte identifies the “MOV A” i nstruction with a data op erand as the second
byte. The sec ond by te of the instructio n is the constan t “0xD8.” A con stant ma y be ref e rred to by nam e if a prior “EQU” state ment
assigns the constant value to the name. For example, the following code is equivalent to the example shown above:

• DSPINIT: EQU 0D8h

• MOV A,DSPINIT

5.6.2 Direct

“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address
location 0x10:

• MOV A,[10h]

Normally , variab le names are as signed to v ariable addresses using “EQU” stateme nts to impro ve the readability of th e assembl er
source code. As an example, the following code is equivalent to the example shown above:

• buttons: EQU 10h

• MOV A,[buttons]

5.6.3 Indexed

“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constant e ncoded in the instruction an d the conte nts of the “X” re gister. Normally, the constant is the “base” address
of an array of data and the X register contains an index that indicates which element of the array is actually addressed:

•array: EQU 10h

•MOV X,3

•MOV A,[X+array]

This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10. The fourth
element would be at address 0x13.

15

6.0 Clocking

XTALOUT

(pin 1)

CY7C65013
CY7C65113

XTALIN

(pin 2)

30 pF

Figure 6-1. Clock Oscillator On-Chip Circuit

The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to
these pins. When usi ng an external crystal, keep PCB traces between the chip leads and c rystal as short as possible (les s tha n
2 cm). A 6-MHz fundamen tal frequency parallel re sonant crystal can be connected to these pins to provide a refere nce frequenc y
for the inte rnal PLL. The tw o i nternal 30-pF lo ad cap s appe ar in se ries to the external crystal and woul d be eq uiv al ent to a 15-pF
load. Therefore, the crystal must have a required load capacitance of about 15–18 pF. A ceramic resonator does not allow the
microcontroller to meet the timing specifications of full speed USB and therefore a ceramic resonator is not recommended with
these parts.

An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Grounding the XTALOUT pin when
driving XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground.

to internal PLL

30 pF

7.0 Reset

The CY7C65x13 supports two resets: Power-On Reset (POR) and a Watch Dog Reset (WDR). Each of these resets causes:

• all registers to be restored to their default states,

• the USB Device Addresses to be set to 0,

• all interrupts to be disabled,

• the PSP and Data Stack Pointer (DSP) to be set to memory address 0x00.

The occurrence of a reset is recorded in the Processor Status and Control Register, as described in Section 13.0. Bits 4 and 6
are used to reco rd the oc c urren ce of POR and WDR resp ec tively. Firmware can interrogate thes e b its to d ete rmine the ca us e of
a reset.

Program execution starts at ROM address 0x0000 after a reset. Although this looks like interrupt vector 0, there is an important
difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware
reset handler sho uld configu re the hardware bef ore the “main ” loop of code. Attemptin g to e x ecut e a RET o r RETI in the firmware
reset handler causes unpredictable execution results.

7.1 Power-On Reset (POR)

When VCC is first applied to the chip , the P ow er-On Reset (POR) signal is asse rted and the CY7C65x13 enters a “sem i-suspend”
state. During the semi-suspend state, which is different from the suspend state defined in the USB specification, the oscillator
and all other blocks of the part are functional, ex ce pt for the CPU. This semi-suspen d tim e ensure s that both a valid V
reached and that the internal PLL has ti me to stab iliz e bef ore full operati on begins . W hen the V

2.5V, and the oscillator is stable, the POR is deasserted and the on-chip timer starts counting. The first 1 ms of suspend time is
not interruptible , and the semi -suspend stat e continues for an a dditional 95 ms unless the co unt is byp assed by a USB Bus Reset
on the upstream port. The 95 ms provides time for V

If a USB Bus Reset occurs on the upstream port during the 95 ms semi-suspend time, the semi-suspend state is aborted and
program execution begins immediately from address 0x0000. In this case, the Bus Reset interrupt is pending but not serviced
until firmware sets the USB Bus Reset Interrupt Enable bit (bit 0 of register 0x20) and enables interrupts with the EI command.

The POR signal is ass erted whenev er V
again. Behavior is the same as described above.

drops below appro xim ately 2.5V, and remains asserted until VCC rises abov e this l ev el

CC

to stabilize at a valid operating voltage before the chip executes code.

CC

16

has risen above approximately

CC

level is

CC

CY7C65013
CY7C65113

7.2 Watch Dog Reset (WDR)

The Watch Dog Timer Reset (WDR) occurs when the internal Watch Dog Timer rolls over. Writing any value to the write-only
Watch Dog Restart Register at ad dress 0x26 c lears the timer . T he timer rolls o ver and WDR occurs if it is no t cleared within t
(8 ms minimum) of the last cl ear. Bit 6 of the Processor Status and Contro l Register is set to record this e vent (the register contents
are set to 010X0001 by the WDR). A Watch Dog Timer Reset lasts for 2 ms, after which the microcontroller begins execution at
ROM address 0x0000.

WATCH

t

WATCH

Last write to

Watch Dog Timer
Register

The USB transmitter is disabled by a Watch Dog Reset because the USB Device Address Registers are cleared (see Section

17.1). Otherwise, the USB Controller would respond to all address 0 transactions.
It is possible for the WDR bit of the Processor Status and Control Register (0xFF) to be set following a POR event. If a firmware

interrogates the Processor Status and Control Register for a set condition on the WDR bit, the WDR bit should be ignored if the
POR (bit 3 of register 0xFF) bit is set.

No write to WDT

register, so WDR
goes HIGH

Figure 7-1. Watch Dog Reset (WDR)

2 ms

Execution begins at

Reset Vector 0x0000

8.0 Suspend Mode

The CY7C65xxx can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register.
All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL,
as well as the free-running and watch dog timers, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle
bus activity at a USB upstream or downstream port wakes the part out of suspend. The Run bit in the Processor Status and
Control Register must be set to resume a part out of suspend.

The clock oscillator restarts immediately after exiting suspend mode. The microcontroller returns to a fully functional state 1 ms
after the oscilla tor is stable . The microc ontroller e xecute s the instruction f ollo wing the I/O write th at placed the d evice into suspend
mode before servicing an y inte rrupt reques ts.

The GPIO interrupt allo ws the controller to w ake-up periodic ally and poll system c omponents while mai ntaining a very low aver age
power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at V

This also applies to internal port pins that may not be bonded in a particular package.

Typical code for entering suspend is shown below:

... ; All GPIO set to low-power state (no floa tin g pins )
... ; Enable GPIO interrupts if desired for wake-up
mov a, 09h ; Set suspend and run bits
iowr FFh ; Write to Status and Control Register - Enter suspend, wait for USB activity (or GPIO Interrupt)
nop ; This executes before any ISR
... ; Remaining code for exiting suspend routine

or Gnd. Note:

CC

17

9.0 General-Purpose I/O (GPIO) Ports

GPIO
CFG

OE

mode
2-bits

Q1

CY7C65013
CY7C65113

V

CC

Q2

Internal
Data Bus

Port Write

Port Read

Reg_Bit

STRB

(Latch is Transparent)

Interrupt
Enable

Interrupt
Controller

Data
Out
Latch

Data
In
Latch

Data
Interrupt
Latch

Control

Control

14 kΩ

Q3*

*Port 0,1,2: Low I

Port 3: High I

sink

GPIO

PIN

sink

Figure 9- 1. Block Diagram of a GPIO Pin

There are up to 32 GPIO pins (P0[7:0], P1[7:4,2:0], P2[7:3], and P3[1:0]) for the hardware interface. The number of GPIO pins
changes based on the pac kag e type of the chi p . Each port can be configured as inputs with internal pull-ups , open dr ain outp uts,
or traditional CMOS outputs. Port 3 offers a higher current drive, with typical current sink capability of 12 mA. The data for each
GPIO port is accessible through the data registers. Port data registers are shown in Figure 9-2 through Figure 9-5, and are set
to 1 on reset.

7 6 5 4 3 2 1 0

P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]

Figure 9-2. Port 0 Data 0x00 (read/write)

7 6 5 4 3 2 1 0

P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]

Figure 9-3. Port 1 Data 0x01 (read/write)

7 6 5 4 3 2 1 0

P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0]

Figure 9-4. Port 2 Data 0x02 (read/write)

7 6 5 4 3 2 1 0

P3[7]

P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0]

(see text)

Figure 9-5. Port 3 Data 0x03 (read/write)

18

CY7C65013
CY7C65113

Special care should be taken with any un used GPIO data bits . An unu sed G PIO da ta bit, either a pin o n the chi p or a p ort bit that
is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is
left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB
Specifications. If a ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a
‘0.’ Notice that the CY7C65113 always requires that P1[7:3], P2[7:0], and P3[7:0] be written with a ‘0.’ When the CY7C65013 is
used, the P1[3], P2[2:0], and P3[7:2] should be written with a ‘0.’

A read from a GPIO port always returns the present state of the voltage at the pin, independent of the settings in the Port Data
Registers. During reset, all of the GPIO pins are set to a high-impedance input state (‘1’ in open drain mode). Writing a ‘0’ to a
GPIO pin drives the pin LOW . In this state, a ‘0’ is always read on that GPIO pin unless an external source overdrives the internal
pull-down device.

9.1 GPIO Configuration Port

Every GPIO port can be programmed as inputs with internal pull-ups, open drain outputs, and traditional CMOS outputs. In
addition, the interrupt polarity for each port can be programmed. With positive interrupt polarity, a rising edge (‘0’ to ‘1’) on an
input pin causes an int errupt. With negati v e pol arity, a falling edge (‘1’ to ‘0 ’) on an i nput pin cause s an inte rrupt. As sho wn in the
table below , whe n a G PIO po rt is configu r ed with C MOS o utp uts, interrupts from that port are disabled. T he GPI O C onfi gur a tio n
Port register provides two bits per port to program these features. The possible port configurations are detailed in Table 9-1.

Table 9-1. Port Configurations

Port Configuration bits Pin Interrupt Bit Driver Mode Interrupt Polarity

11 0 Resistive Disabled

1Resistive–

10 0 CMOS Output Disabled

1 Open Drain Disabled

01 0 Open Drain Disabled

1 Open Drain –

00

(Reset Stat e)

0 Open Drain Disabled (Default Condition)
1 Open Drain +

In “Resistive” mod e, a 14-kΩ pull -up resis tor is c ondition ally en able d f or all pins o f a GPIO p ort. An I/O pin is driv en HIGH th rough
a 14-kΩ pull-up resisto r when a ‘ 1’ has be en written to the pin. The o utp ut p in is driven LOW w ith the pu ll-u p d is abled when a ‘0’
has been written to the pin. An I/O pin that has been w ritten as a ‘1’ can be used as an input p in with the in tegra ted 14-k Ω pull-up
resistor. Resistive mode selects a negative (falling edge) interrupt polarity on all pins that have the GPIO interrupt enabled.

In “CMOS” mode, all pins of the GPIO port are outputs that are activ ely driven. A CMOS port is not a possible sourc e for interrupts.
In “Open Drain” mode, the internal pull-up resistor and CMOS driver (HIGH) are both disabled. An open drain I/O pin that has

been written as a ‘1’ can be used as an input or an open drain output. An I/O pin that has been written as a ‘0’ drives the output
low. The interrupt polarity for an open drain GPIO port can be selected as positive (rising edge) or negative (falling edge).

During reset, all of the bits in the GPIO Configura tio n Re gis ter are written wit h ‘0’ to selec t Open Dr ai n outpu t for all GPIO ports
as the default configuration.

7 6 5 4 3 2 1 0

Port 3

Config Bit 1

Port 3

Config Bit 0

Port 2

Config Bit 1

Figure 9-6. GPIO Configuration Register 0x08 (read/write)

Port 2

Config Bit 0

Port 1

Config Bit 1

Port 1

Config Bit 0

Port 0

Config Bit 1

Port 0

Config Bit 0

19

CY7C65013
CY7C65113

9.2 GPIO Interrupt Enable Ports

Each GPIO pin can be individually enabled or disabled as an interrupt source. The Port 0–3 Interrupt Enable registers provide
this feature with an interrupt enable bit for each GPIO pin.

During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in
Section 14.7.

7 6 5 4 3 2 1 0

P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]

Figure 9-7. Port 0 Interrupt Enable 0x04 (write only)

7 6 5 4 3 2 1 0

P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]

Figure 9-8. Port 1 Interrupt Enable 0x05 (write only)

7 6 5 4 3 2 1 0

P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0]

Figure 9-9. Port 2 Interrupt Enable 0x06 (write only)

7 6 5 4 3 2 1 0

reserved ­set to zero

P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0]

Figure 9-10. Port 3 Interrupt Enable 0x07 (write only)

10.0 12-Bit Free-Running Timer

The 12-bit timer provides two interrupts (128-µs and 1.024-ms) and allows the firmware to directly time events that are up to 4
ms in duration. The lower 8 bits of the timer can be read directly by the firmware. Reading the lower 8 bits latches the upper 4
bits into a temporary register. When the firmware reads the upper 4 bits of the timer, it is accessing the count stored in the
temporary register. The effect of this logic is to ensure a stable 12-bit timer value can be read, even when the two reads are
separated in time.

10.1 Timer (LSB)

7 6 5 4 3 2 1 0

Timer

Bit 7

10.2 Timer (MSB)

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Timer

Timer

Bit 6

Timer

Bit 5

Figure 10-1. Timer Register 0x24 (read only)

Figure 10-2. Timer Register 0x25 (read only)

Timer

Bit 4

Timer

Bit 3

Bit 11

Timer

Bit 2

Timer
Bit 10

Timer

Bit 1

Timer

Bit 9

Timer

Bit 0

Timer

Bit 8

20

CY7C65013
CY7C65113

1.024-ms Interrupt

µ

s Interrupt

128-

10 9 7856432

1 011

1-MHz Clock

L1 L0L2L3

D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

To Timer Register

8

Figure 10-3. Timer Block Diagram

11.0 I2C Configuration Register

Internal hardware suppo rts communic ati on wi th external de vi ce s th rou gh an I2C compatible in terface. I2C compatib le f unc tio n is
discussed in detail in Section 12.0. Bit 7 of I
This bit is cleared on reset.

7 6 5 4 3 2 1 0

R/W

I2C Position Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Figure 11-1. I2C Configuration Register 0x09 (read/write)

2

Note: I

C compatible function must be separately enabled as described in Section 12.0.

2

C Configuration Register selects I2C compatible functionality on Por t 1 or Port 2.

Table 11-1. I

2

C Port Configuration

2

I

C Position

Bit[7]

X1I
00I
10I

Port Width

Bit[1] I2C Position

2

C on P2[1:0], 0:SCL, 1:SDA

2

C on P1[1:0], 0:SCL, 1:SDA

2

C on P2[1:0], 0:SCL, 1:SDA

12.0 I2C Compatible Controller

The I2C compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and
multi-master mode s of oper ation. Th e I
interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the
hardware keep s the I

2

C compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a

The I

2

C compatible bus idle if necessary.

stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in
Section 14.8.

2

C compatible interface consists of two registers, an I2C Data Register (Figure 12-1) and an I2C Status and Control Reg ister

The I
(Figure 12-2). The Data Register is implemented as separate read and write registers. Generally, the I
Register should o nly be moni tored a fter the I
read bit misleading bit status if a transaction is underway.

2

C SCL clock is connected to bit 0 of GPIO port 1 or GPIO port 2, and the I2C SDA data is conn ec ted to bi t 1 of GPIO port

The I
1 or GPIO port 2. Refer to Sec tion 11. 0 for the bit defin itio ns and fun cti ona li ty o f the I2C Configuration R egi st er, which is used to
set the locations of the configurable I

2

C compatible b loc k func tions b y handling the low -le v el sign aling in ha rdware , and iss uing

2

2

C interrupt, as all bits are v a lid at that ti me . Polling this register at other times could

2

C compatible pins. Once the I2C compatible functionality is enabled by setting bit 0 of the

C Status and Control

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2

I

C Status & Control Register, the two LSB ([1:0]) of the corresponding GPIO port is placed in Open Drain mode, regardless of
the settings of the GPIO Configuration Register.The electrical characteristics of the I
of GPIO ports 1 and 2. Note that the I

2

All control of the I

C clock and data lines is performed by the I2C compatible block.

(max) is 2 mA @ V

OL

= 2.0V for ports 1 and 2.

OL

7 6 5 4 3 2 1 0

I2C Data 7 I2C Data 6 I2C Data 5 I2C Data 4 I2C Data 3 I2C Data 2 I2C Data 1 I2C Data 0

Figure 12-1. I2C Data Register 0x29 (separate read/write registers)

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/W

MSTR

Mode

Continue/

Busy

Xmit

Mode

ACK Addr ARB Lost/

Figure 12-2. I2C Status and Control Register 0x28 (read/write)

The I2C Status and Control register bits are defined in Table 12-1, with a more detailed description following.

2

C compatible interface is the same as that

Received St op I2C

Restart

Enable

Table 12-1. I

2

C Status and Control Register Bit Definitions

Bit Name Description

0I

2

C Enable Write to 1 to enable I2C compatible function. When cleared, I2C GPIO pins operate

normally.

2

1 Received Stop Reads 1 only in slav e receiv e mode , when I

C Stop bit detected (unle ss firmware did not

ACK the last transaction).

2 ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.

Write to 1 in master mode to perform a restart sequence (also set Continue bit).

3 Addr Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.

Reads 0 otherwise. This bit should always be written as 0.

4 ACK In receive mode, write 1 to generate ACK, 0 for no ACK.

In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
5 Xmit Mode Write to 1 for transmit mode, 0 for receive mode.
6 Continue/Busy Write 1 to indicate ready for next transaction.

Reads 1 when I

2

C compatible block is busy with a transaction, 0 when transaction is

complete.
7 MSTR Mode Write to 1 f or master mod e, 0 f or slav e mode . This bit i s cleared if mas ter loses arbitration.

Clearing from 1 to 0 ge nerates Stop bit.

2

MSTR Mode: Setting this bit causes the I

C compatible block to initiate a master mode transaction by sending a start bit and
transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes are
initiated by setting the Continue bit, as described below.

2

In master mode, the I
or receive state. The I

C compatible b lock generates the clock (SCK), and drives the data line as re quired de pendi ng on tr ansm it

2

C compatible block performs any required arbitration and clock synchronization. The loss of arbitration
results in the clearing of this bit, the setting of the ARB Lost bit, and the generation of an interrupt to the microcontroller. If the
chip is the target of an external master that wins arbitration, then the interrupt is held off until the transaction from the external
master is completed.

2

When MSTR Mode is cleared from 1 to 0 by a firmware write, an I

C Stop bit is generated.

Continue / Busy: This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin.
In other words, the bit has respon ded to an i nterrupt reques t and has complete d the requi red updat e or read of the data register.
During a read this bit indicates if the hardware is busy and is locking out additional writes to the I
This locking allows the hardware to complete certain operations that may require an extended period of time. Following an I2C
interrupt, the I

2

C compatible b loc k does n ot retu rn to the Busy st ate until firmware se ts the Contin ue b it. Thi s all ows the fi rmware

2

C Status and Control register.

to make one control register write without the need to check the Busy bit.

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Xmit Mode: This bit is set b y firmware t o ente r tr ansmit mo de and perf o rm a data tr ansm it in m aster or sla ve mode . Clear t his b it

for receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I
The Xmit Mode bit state is ignored w hen initially writing the MSTR Mo de or the Restart bits, as these cases alw ays ca use transmit
mode for the first byte.

ACK: This bit is set or cle ar ed by fi r mwar e du ri ng r ece ive operat ion to ind icat e i f the har dware shou ld ge nera te a n ACK sig nal

2

on the I
During transmits (Xmit Mode = 1), this bit should be cleared.

Addr: This bit is set by the I
The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master has
lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred.

ARB Lost/Restart: This bit is vali d as a statu s bit (ARB Lo st) aft er mas ter mo de tr ansac tions . I n mas ter mo de , set t his bi t (alon g
with the Continue and MST R Mode bits) to perf orm an I
to the data register bef ore setting t he Continue b it. To prevent f alse ARB Lost si gnals, the Restart bit is cleare d by hardw are during
the restart sequence.

Receive Stop: This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set
if the firmware terminates th e I
in receive mode if firmware sets the Continue bit and clears the ACK bit.

I2C Enable: Set this bit to override GPIO definition with I
cleared, these pins are free to functi on as GPIO s. In I2C compatibl e mode , the tw o pi ns oper ate in o pen dr ain mo de, i ndepende nt
of the GPIO configuration setting.

C compatible bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I2C compatible bus at the ACK bit time.

2

C compatible block during the first byte of a slave receive transaction, after an I2C start or restart.

2

C restart sequence. The I2C target address f or the restart must be written

2

C transaction b y not a c kno w ledgin g the pre v ious byte transm itted on the I2C compatible b us , e . g.

2

C compatible function on the two I2C compatible pins. When this bit is

2

C address packet.

13.0 Processor Status and Control Register

7 6 5 4 3 2 1 0

R R/W R/W R/W R/W R R/W

IRQ

Pending

Watch Dog

Reset

USB Bus Re-

set Interrupt

Power-On

Reset

Suspend Interrupt

Enable Sense

reserved Run

Figure 13-1. Processor Status and Control Register 0xFF

The Run bit, bit 0, is manipul ated b y the HALT instruction. When Halt is e x ecuted, all the bits of the Proc essor Statu s and Control
Register are cleared to 0. Since the run bit is cleared, the processor stops at the end of the current instruction. The processor
remains halted until an appropriate reset occurs (power-on or Watch Dog). This bit should normally be written as a ‘1.’

Bit 1 is reserved and must be written as a zero.
The Interrupt Enable Sen se (bit 2) sho ws w hether in terrupts are en ab led or di sab led . Firmware has no di rect con trol o v er th is bit

as writing a zero or one to this bit position has no effect on interrupts. A ‘0’ indicates that interrupts are masked off and a ‘1’
indicates that the interrupts are enab led. This bit is further gated with the bit settings of the Global I nterrupt Enab le Register (0x20)
and USB End Point Interrupt Enable Register (0x21). Instructions DI, EI, and RETI manipulate the state of this bit.

Writing a ‘1’ to the Suspend bit (bit 3) halts the processor and cause the microcontroller to enter the suspend mode that signifi­cantly reduces power consump tio n. A pending, enab le d inte rrupt or USB bus activi ty causes the device to co me ou t of suspend.
After coming out of susp end, the de vic e resumes firmw are e x ecution at the instruction follow ing the IO WR wh ich put the part into
suspend. An IO WR a ttem pt ing to p ut th e part into suspend is ignored if non-i dle USB bus activity is pres en t. See Sec tio n 8. 0 for
more details on suspend mode operation.

The Power-On Reset (bit 4) is set to ‘1’ during a power-on reset. The firmware can check bits 4 and 6 in the reset handler to
determine whether a reset was c aused by a power-on condition or a w atch dog timeou t. A POR ev ent ma y be f ollo wed by a watch
dog reset before firmware begins executing, as explained below.

The USB Bus Reset Interrupt (bit 5) occurs when a USB Bus Reset is received on the upstream port. The USB Bus Reset is a
single-ended z ero (SE0) that lasts from 12 to 1 6 µs . An SE0 is defined as the condi tion in w hich bo th the D+ line an d the D– lin e
are LOW at the same time. When the SIE detects that this SE0 condition is removed, the USB Bus Reset interrupt bit is set in
the Processor Status and Control Register and a USB Bus Reset interrupt is generated.

The Wa tch D og Res et (bit 6) is set during a res et ini tia ted by the Watch Dog Timer. This indicates the Watch Dog Timer went for
more than t

The IRQ pending (bit 7), when set , indicates that one or more of the inte rrupts has been recognized as active. An interrupt rem ains
pending until its interrupt enable bit is set (registers 0x20 or 0x21) and interrupts are globally enabled. At that point, the internal
interrupt handling sequence clears this bit until another interrupt is detected as pending.

During power-up, the Processor Status an d Cont rol R eg is ter is set to 00 01 000 1, w hic h in dic ate s a POR (bit 4 se t) has occurre d
and no interrupts are pending (bit 7 clear) . During the 96 ms suspe nd at start-up (explained in Section 7.1), a Watch Dog Reset
also occurs unless this suspend is aborted by an upstream SE0 before 8 ms. If a WDR occurs during the power-up suspend

(8 ms minimum) between Watch Dog clears. This can occur with a POR event, as noted below.

WATCH

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interval, firmware reads 0101 0001 from th e Statu s and Control Reg ister a fter po w er-up. Normally, the POR bit should be cleare d
so a subsequent WDR can be clearly identi fie d. If an ups tre am bus reset is receiv ed before firmware examines this regist er, the
Bus Reset bit may also be set.

During a Watch Dog Reset, the Processor Status and Control Register is set to 01XX0001, which indicates a Watch Dog Reset
(bit 6 set) has occurred and no interrupts are pending (bit 7 clear). The Watch Dog Reset does not effect the state of the POR
and the Bus Reset Interrupt bits.

14.0 Interrupts

Interrupts are generated by the GPIO pi ns, the int ernal timers, I2C compatible o peratio n, the internal USB hub , or on v arious USB
traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable
Register. Writing a ‘1’ to a bit position enables the interrupt associated with that bit position. During a reset, the contents the
Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared, effectively disabling all interrupts.

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W

Reserved I2C

Interrupt

Enable

GPIO

Interrupt

Enable

Figure 14-1. Global Interrupt Enable Register 0x20 (read/write)

Reserved USB Hub

Interrupt

Enable

1.024-ms
Interrupt

Enable

128-µs

Interrupt

Enable

USB Bus RST

Interrupt

Enable

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W

Reserved Reserved Reserved EPB1

Interrupt

Enable

Figure 14-2. USB Endpoint Interrupt Enable Register 0x21 (read/write)

The interrupt controll er co ntains a s epar ate fl ip-flop for each i nterrupt. See Figur e 14-3 f or the logi c bloc k di agram of the interrupt
controller . Whe n an interrupt is generat ed, it is firs t registere d as a pend ing interrupt. It s ta ys pending u ntil it is serviced or a reset
occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable
registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction.

When servicing an interrupt, the hardware first disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the
state of this bit can be re ad at Bi t 2 o f th e Pro ces s or Sta tus an d Con trol R egi st er). Se co nd, the fli p-fl op o f th e curren t in terrupt i s
cleared. This is f o llo wed b y an autom atic CA LL ins truction to the R OM ad dress ass ociate d with the in terrupt being serviced (i.e .,
the Interrupt Vector, see Section 14.1). The instruction in the interrupt table is typically a JMP instruction to the address of the
Interrupt Service Routine (ISR). The user can re-enable int errupts in the interrupt service routine by executing an E I instruction.
Interrupts can be nested to a level limited only by the available stack space.

The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction gener a ted as pa rt of the interrupt ac kn o w l edg e pro ce ss. The user firmware is resp ons ible for en su ring that th e
processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value
just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI
instruction is executed.

The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exists the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).

EPB0

Interrupt

Enable

EPA2

Interrupt

Enable

EPA1

Interrupt

Enable

EPA0

Interrupt

Enable

14.1 Interrupt Vectors

The Interrupt Vectors supported by the USB Controller are listed in Table 14-1. The lowest-numbered interrupt (USB Bus Reset
interrupt) has the highest priority, and the highest-numbe red interrupt (I2C interrupt) has the low est priority. Although Reset is not
an interrupt, the first instruction execu ted after a reset is at PRO M address 0x0000h—which cor r esponds to the first entry in the
Interrupt Vector Table. Because the JMP instruction is 2 bytes long, the interrupt vectors occupy 2 bytes.

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USB Reset Clear

CLR

D

CLK

CLR

D

CLK

CLR

D

CLK

Q

Enable [0]

(Reg 0x20)

Q

Enable [2]

(Reg 0x21)

Q

Enable [6]
(Reg 0x20)

USB Reset IRQ
128-µµµµs CLR

128-µµµµs IRQ
1-ms CLR

1-ms IRQ
AddA EP0 CLR

AddA EP0 IRQ
AddA EP1 CLR

AddA EP1 IRQ
AddA EP2 CLR

AddA EP2 IRQ
AddB EP0 CLR

AddB EP0 IRQ
AddB EP1 CLR

AddB EP1 IRQ
Hub CLR

Hub IRQ
DAC CLR

DAC IRQ
GPIO CLR

GPIO IRQ

2

I

C CLR

2

C IRQ

I

Interrupt

Priority

Encoder

1

USB

Reset

Int

1

AddA
ENP2
Int

1

2

C

I
Int

Interrupt

Vector

IRQout

To CPU

CPU

Global

Interrupt

Enable

Bit

CLR

Interrupt

Acknowledge

IRQ Sense

IRQ

Int Enable
Sense

Controlled by DI, EI, and
RETI Instructions

Figure 14-3. Interrupt Controller Functional Diagram

Table 14-1. Interrupt Vector Assignments

Interrupt Vector Number ROM Address Function

Not Applicable 0x0000 Execution after Reset begins here

1 0x0002 USB Bus Reset interrupt
2 0x0004 128-µs timer interrupt
3 0x0006 1.024-ms timer interrupt
4 0x0008 USB Address A Endpoint 0 interrupt
5 0x000A USB Address A Endpoint 1 interrupt
6 0x000C USB Address A Endpoint 2 interrupt
7 0x000E USB Address B Endpoint 0 interrupt
8 0x0010 USB Address B Endpoint 1 interrupt

9 0x0012 USB Hub interrupt
10 0x0014 DAC interr upt
11 0x0016 GPIO interrupt
12 0x0018 I2C interrupt

A pending address can be read from the Interrupt Vector Register (Figure 14-4). The value read from this register is only valid if
the Global Interrupt bit has been disab led, b y e xec uting the DI inst ruction or in an I nterrupt Service Routine bef ore in terrupts hav e
been re-enab led. T he v a lue re ad from this regis ter is the i nterrupt vector address; f or example, a 0 x12 ind icates the hub in terrupt
is the highest priority pending interrupt.

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7 6 5 4 3 2 1 0

R R R R R

Reserved Reserved Reserved Interrupt

Vector Bit 4

Figure 14-4. Interrupt Vector Register 0x23 (read only)

14.2 Interrupt Latency

Interrupt latency can be calculated from the following equation:
Interrupt latency = (Numb er of c lo ck cycles remaining i n th e current instruction) + (10 clock cycles for the CALL instruction) +

(5 clock cycles for the JMP instruction)

For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is
issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock periods is 20 / 12 MHz = 1.667 µs.

14.3 USB Bus Reset Interrupt

The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists on the upstream USB port for
12–16 µs (the Reset may be recognized for an SE0 as short as 12 µs, but is always recognized for an SE0 longer than 16 µs).
SE0 is defined as the conditio n in which both the D+ line and the D – line are LOW. Bit 5 of the Status and Control Register is set
to record this event. The interrupt is asserted at the end of the Bus Reset. If the USB reset occurs during the start-up delay
follo wing a POR, t he delay is aborted as described in Se ction 7.1 . The USB Bu s Reset Int errupt is ge nerated when the SE0 s tate
is deasserted.

A USB Bus Reset clears the following registers:

SIE Section: USB Device Address Registers (0x10, 0x40)
Hub Section: Hub Ports Connect Status (0x48)

Hub Ports Enable (0x49)
Hub Ports Speed (0x4A)
Hub Ports Suspend (0x4D)
Hub Ports Resume Status (0x4E)
Hub Ports SE0 Status (0x4F)
Hub Ports Data (0x50)
Hub Downstream Force (0x51)

Interrupt

Vector Bit 3

Interrupt

Vector Bit 2

Interrupt

Vector Bit 1

Reads ‘0’

14.4 Timer Interrupt

There are two periodic timer interrupts: the 128-µs interrupt and the 1.024-ms interrupt. The user should disable both timer
interrupts bef ore going into the suspend mode to avoid possible c onflicts betwee n servicing the timer interrupt s first or the suspend
request first.

14.5 USB Endpoint Interrupts

There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a
USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet of
the transaction (e.g., on the host’s ACK during an IN, or on the device ACK during on OUT). If no ACK is received during an IN
transaction, no interrupt is generated.

14.6 USB Hub Interrupt

A USB hub interrupt is generated by the hardware after a connect/disconnect change, babble, or a resume event is detected by
the USB repeater hardware. The babble and resume events are additionally gated by the corresponding bits of the Hub Port
Enable Register (Figure 16-3). The connect/disconnect event on a port does not generate an interrupt if the SIE does not drive
the port (i.e., the port is being forced).

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14.7 GPIO Interrupt

Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as
part of the GPIO configuration. All of the GPIO pins sha re a s ing le i nte rrupt vector, which means the fi rmware ne eds to re ad th e
GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt
logic is shown in Figure 14-5. Refer to Sections 9.1 and 9.2 for more information of setting GPIO interrupt polarity and enabling
individual GPIO interrupts.

If one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its
inactive (non -trigger) s tate or its correspondin g p ort interrupt enab le bit is cleared. The USB Co ntro lle r do es not assign interrupt
priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.

Port

GPIO
Pin

Configuration

Register

M
U
X

OR Gate

(1 input per

GPIO pin)

GPIO Interrupt
Flip Flop

D

1

CLR

Q

Interrupt

Priority

Encoder

IRQout

Interrupt

Vector

1 = Enable
0 = Disable

IRA

Port Interrupt
Enable Register

1 = Enable
0 = Disable

Global

GPIO Interrupt

Enable

(Bit 5, Register 0x20)

Figure 14-5. GPIO Interrupt Structure

14.8 I2C Interrupt

The I2C interrupt occurs after various events on the I2C compatible b us to si gnal t he nee d f o r fi rmware inte r action . This gener all y
involves reading the I2C Status and Control Register (Figure 12-2) to determine the cause of the interrupt, loading/reading the

2

C Data Register as appropriate, and finally writing the Status and Control Register to initiate the subsequent transaction. The

I
interrupt indicates that st atu s bi ts are stable and it is sa fe to read and write the I
the I2C registers.

2

When enable d, the I

C compatible s tate m ach in es generate interrupts o n c om pl eti on of t he followi ng con di t ion s. The ref eren ce d

bits are in the I2C Status and Control Register.

1. In slave receiv e mo de, after the slave receive s a byte of data. The Addr bit is se t if thi s is the firs t byte since a start or restart
signal was sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit
Mode, and Continue bits appropriately for the next byte.

2. In slave receiv e mode , after a stop b it is detected. Th e Receiv ed Stop bit i s set. If the stop bit f ollows a slav e receive transaction
where the ACK bit was cleared to 0, no stop bit detection occurs.

3. In slave transmit mode, after the slave transmits a byte of data. The ACK bit indicates if the master that requested the byte
acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the
Xmit Mode and Continue bits as requir ed.

4. In master transmit mode, after the master se nds a byte of data . Firmware shou ld load the Data Reg ister if necessa ry, and set
the Xmit Mode, MSTR Mode, and Continue/Busy bits appropriately. Clearing the MSTR Mode bit issues a stop signal to the

2

C compatible bus and return to the idle state.

I

5. In master receive mode, after the master receives a byte of data. Firmware should read the data and set the Ack and Contin­ue/Busy bits appropriately for the ne xt by te. Clearing the Mas ter bit at the same tim e causes the master st ate machine to is sue
a stop signal to the I

6. When the master loses arbitration. This condition clears the Master bit and sets the Arbitration Lost bit immediately and then
waits for a stop signal on the I

2

C compatible bus and leave the I2C compatible hardware in the idle state.

2

C compatible bus to generate the interrupt.

2

C registers. Refer to Section 12.0 f or de tai ls on

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The Continue/Busy bit is cleared by hardware prior to interrupt co nditions 1 to 4. Once the Dat a Register has bee n read or written,
firmware should configure the other control bits and set the Continue bit for subsequent transactions.

Follo wing an interrupt from master mo de, firmw are should perf orm only one write to the St atus and Contro l Register tha t sets th e
Continue bit, without checking the value of the Busy bit. The Busy bit may otherwise be active and I
changed by the hardware during the transaction, until the I2C interrupt occurs.

15.0 USB Overview

The USB hardware include s a USB Hub repe ater wi th one upstrea m and up to s e v e n do wnst ream ports. The USB Hub repeat er
interfaces to the microcontroller through a full-speed serial interface engine (SIE). An external series resistor of R
placed in series with all upstream and downstream USB outputs in order to meet the USB driver requirements of the USB
specification. The CY7C65x13 microcontroller can provide the functionality of a compound device consisting of a USB hub and
permanently attached functions.

15.1 USB Serial Interface Engine (SIE)

The SIE allows the CY 7C6 5x 13 mi cro co ntro lle r to c ommunicate with th e USB ho st through the USB repe ate r p ortion of the h ub.
The SIE simplifies the in terface betwee n th e mi cro co ntro lle r and U SB by incorporating hardw are th at h and les the followin g USB
bus activity independently of the microcontroller:

• Bit stuffing/unstuffing

• Checksum generation/checking

• ACK/NAK/STALL

• Token type identification

• Address checking

Firmware is required to handle the following USB interface tasks:

• Coordinate enumeration by responding to SETUP packets

• Fill and empty the FIFOs

• Suspend/Resume coordination

• Verify and select DATA toggle values

2

C register contents may be

must be

ext

15.2 USB Enumeration

The internal hub and a ny compound device function are e numerated under firmware cont rol. The hub is enumera ted first, f ollowe d
by any integrated compound function. After the hub is enumerated, the USB host can read hub connection status to determine
which (if any) of the downstream ports need to be enumerated. The following is a brief summary of the typical enumeration process
of the CY7C65x13 by the USB host. For a detailed description of the enumeration process, refer to the USB specification.

In this description, ‘Firmware’ refers to embedded firmware in the CY7C65x13 controller.

1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor.

2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables.

3. The host computer performs a control re ad seque nce and Firmware re sponds by sending the De vi ce desc riptor ov er t he USB
bus, via the on-chip FIFOs.

4. After receiving the descriptor, the host se nds a SET UP packet followed by a DAT A packet to a ddre ss 0 assigning a ne w U SB
address to the device.

5. Firmware stores the new address in its USB Device Address Register (for example, as Address B) after the no-data control
sequence complete s.

6. The host sends a request for the Device descriptor using the new USB address.

7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.

8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus.

9. The host generates control reads from the device to request the Configuration and Report descriptors.

10.Once the device receives a Set Configuration request, its functions may now be used.

11.Follo wing en umer ation as a hub, Firmware can optionall y indica te to the ho st tha t a compound de vice e x ists (f or e xample , the
keyboard in a keyboard/hub device).

12.The host carries out t he enumeratio n process with this addit ional function as th ough it were attache d downstream fr om the hub.

13.When the host assigns an address to this device, it is stored as the other USB address (for example, Address A).

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16.0 USB Hub

A USB hub is required to support:

• Connectivity behavior: service connect/disconnect detection

• Bus fault detection and recovery

• Full-/Low-speed device support

These feat ures are mapped onto a hub repeater and a hub controller. The hub controller is supported by the processor integrate d
into the CY7C65x13 microcontrollers. The hardware in the hub repeater detects whether a USB device is connected to a down­stream port and the interface speed of the downstream device. The connection to a downstream port is through a differential
signal pair (D+ and D–). Each downstream port provided by the hub requires external R
ground, so that whe n a downstre am port has no device c onnected, the hub re ads a LOW (z ero) on both D + and D–. This condi tion
is used to identify the “no connect” state.

The hub must have a resistor R
The hub generates an EOP at EOF1, in accordance with the USB 1.1 Specification.

connected between its upstream D+ line and V

UUP

REG

16.1 Connecting/Disconnect ing a USB Device

A low-speed (1.5 Mb ps ) USB d evice has a pull-up res is tor on the D – p in. At con nec t ti me, the bias resistors se t the sig na l levels
on the D+ and D– lines. When a low-speed device is connected to a hub port, the hub sees a LOW on D+ and a HIGH on D–.
This causes the hub repeater to set a connect bit in the Hub Ports Connect Status register for the downstream port. The hub
repeater also sets a b it in the Hu b Ports Speed register to i ndicate th is port is low-speed (see Figure 16-1 and F igure 16-2). The n
the hub repeater generates a Hub Interrupt to notify the microcontroller that there has been a change in the Hub downstream
status.

A full-speed (12 Mbps) USB device has a pull-up resistor from the D+ pin, so the hub sees a HIGH on D+ and a LOW on D–. In
this case, the hub repeater sets a con nect bit in the Hu b Po rts Connect Status register , clears a bit in the Hub P orts Speed register
(for full-speed), and generates a Hub Interrupt to notify the microcontroller of the change in Hub status.

Connects are recorded by the time a non-SE0 state lasts for more than 2.5 µs on a downstream port.
When a USB dev ice is di sconnected from the Hub, the downstream signal pair e ve ntually f loats to a s ingle-ended z ero s tate. Th e

hub repeater recognizes a disconnect once the SE0 state on a downstream port lasts from 2.0 to 2.5 µs. On a disconnect, the
corresponding bit in the Hub Ports Connect Status register is cleared, and the Hub Interrupt is generated.

resistors from each signal line to

UDN

to indicate it is a full speed USB device.

7 6 5 4 3 2 1 0

Reserved Port 7

Connect

Status

Figure 16-1. Hub Ports Connect Status 0x48 (read/write), 1 = Connect, 0 = Disconnect

The Hub Ports Connect Status register is cleared to zero by reset or bus reset, then set to match the hardware configuration by
the hub repeater hardware. The Reserved bit [7] should always read as ‘0’ to indicate no connection.

7 6 5 4 3 2 1 0

Reserved Port 7

Speed

Figure 16-2. Hub Ports Speed 0x4A (read/write), 1 = Low-Speed, 0 = Full-Speed

The Hub P orts Speed register is cl ear ed to z e ro by reset or bus reset, then set to ma tch the hardware configura tion whenever a
connect occurs. F irmware may write this register if des ired, to allow f or firmware de bouncing of the spee d detection. The Res erved
bit [7] should always read as ‘0.’

Port 6

Connect

Status

Port 6

Speed

Port 5

Connect

Status

Port 5

Speed

Port 4

Connect

Status

Port 4

Speed

Port 3

Connect

Status

Port 3

Speed

Port 2

Connect

Status

Port 2

Speed

Port 1

Connect

Status

Port 1

Speed

16.2 Enabling/Disabling a USB Device

After a USB device connection has been detected, firmware must update status change bits in the hub status change data
structure that is polled periodically by the USB host. The host responds by sending a packet that instructs the hub to reset and
enable the downstream port. Firmware then sets the bit in the Hub Ports Enable register, Figure 16-3, for the downstream port.
The hub repeater hard w are res pon ds to a n en able bit in the Hub Ports Enable regis ter by enabling the downstream port, so that
USB traffic can flow to and from that port.

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If a port is marked enabled and is not suspended, it receives all USB traffic from the upstream port, and USB traffic from the
downstream port is passed to the upstream port (unless babble is detected). Low-speed ports do not receive full-speed traffic
from the upstream port.

When firmware writes to the Hub P orts Enable register to en able a port, the port is not enabled until the end of any pack et currently
being transmitted. If there is no USB traffic, the port is enabled immediately.

When a USB device disconnec tio n h as be en d ete cte d, firmware must upd ate st atus b its in the hub change status d ata stru ctu re
that is polled pe riodic all y by the USB host. I n s us pen d, a c onn ec t or dis co nn ect event gen erates an interrupt (if the hub interrupt
is enabled) even if the port is disabled.

7 6 5 4 3 2 1 0

Reserved Port 7

Enable

Figure 16-3. Hub Ports Enable Registe r 0x49 (read/write), 1 = Enabled, 0 = Disabled

The Hub P orts Enable register is cleared to zero b y reset or b us reset to disab le all dow nstream ports as the defaul t condition . A
port is also disabled by internal hub hardware (enab le bit cleare d) if babbl e is detected on that do wnstream port. Babble is defined
as:

• Any non-idle downstream traffic on an enabled downstream port at EOF2

• Any downstream port with upstream connectivity established at EOF2 (i.e., no EOP received by EOF2)

Port 6

Enable

Port 5

Enable

Port 4

Enable

Port 3

Enable

Port 2

Enable

Port 1

Enable

16.3 Hub Downstream Ports Status and Control

Data transfer on hub downs trea m p orts is controll ed ac c ordi ng to the bit settings of the Hub Do w ns tre am Ports Control Register
(Figure 16-4). Each do wnstream po rt is controlled b y two bi ts, as def ined in Table 16-1 below . The Hub Do wnstream P orts Control
Register is cleared upon reset or bus reset, and the reset state is the state for normal USB traffic. Any downstream port being
forced mu st be ma rk ed as dis abled (Figure 16-3) for proper operation of the hub repeater.

Firmware should use this register for driving bus reset and resume signaling to downstream ports. Controlling the port pins
through this register u ses stan dard USB edge rate control acco rding to the speed of the port, set in the Hu b Port Speed Register.

The downstream USB ports are designed for connection of USB devices, but can also serve as output ports under firmware
control. This al lo ws un used USB p orts to be used f or fu nctio ns su ch as driving LEDs or pro vi ding a dditio nal i nput s ignals . Pulling
up these pins to voltages above V

This register is not reset by bus reset. These bits must be cleared before going into suspend.

7 6 5 4 3 2 1 0

Port 4

Control Bit 1

Table 16-1. Control Bit Definition for Downstream Ports

Control Bits:

Bit1 Bit 0 Control Action

0 0 Not Forcing (Normal USB Function)
0 1 Force Differential ‘1’ (D+ HIGH, D– LOW)
1 0 Force Differential ‘0’ (D+ LOW, D– HIGH)
1 1 Force SE0 state

Port 4

Control Bit 0

Figure 16-4. Hub Downstream Ports Control Register 0x4B (read/write)

may cause current flow into the pin.

REF

Port 3

Control Bit 1

Port 3

Control Bit 0

Port 2

Control Bit 1

Port 2

Control Bit 0

Port 1

Control Bit 1

Port 1

Control Bit 0

An alternate means of forcing the downstream ports is through the Hub Ports Force Low Register (Figure 16-5) and Hub Ports
Force High Register (Figure 16-6). With these registers the pins of the downstream ports can be individually forced LOW, or left
unforced. Unlike the Hub Downstream Por ts Control Register, above, the Force Low Register does not produce standard USB
edge rate con trol on t he f orced pins . How e v er , this reg ister all ows d ownstre am port pins to b e held LO W in sus pend. Thi s regist er
can be used to drive SE0 on all downstream ports when unconfigured, as required in the USB 1.1 specification.

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7 6 5 4 3 2 1 0

Force Lo w

DD4 D+

7 6 5 4 3 2 1 0

Reserved Reserved Force High

The data state of downstream ports can be read through the HUB Ports SE0 Status Register (Figure 16-7) and the Hub Ports
Data Register (Figure 16-8). The data read from the Hub Ports Data Register is the differential data only and is not dependent
on the settings of the Hub Ports Speed Register (Figure 16-2). When the SE0 condition is sensed on a downstream port, the
correspondi ng bits of t he Hub Ports D ata Registe r hold the las t differential data state be fore the SE0. Hu b Ports SE0 Sta tus
Register and Hub Ports Data Register are cleared upon reset or bus reset.

7 6 5 4 3 2 1 0

Reserved Port 7

Force Low

DD4 D–

Figure 16-5. Hub Ports Force Low Register (read/write) 0x51, 1 = Force Low, 0 = No Force

Figure 16-6. Hub Ports Force High Register (read/write) 0x52, 1 = Force High, 0 = No Force

SE0 Status

Figure 16-7. Hub Ports SE0 Status Register 0x4F (read only), 1 = SE0, 0 = Non-SE0

Force Low

DD3 D+

DD7 D+

Port 6

SE0 Status

Force Low

DD3 D–

Force High

DD7 D–

Port 5

SE0 Status

Force Low

DD2 D+

Force High

DD6 D+

Port 4

SE0 Status

Force Low

DD2 D–

Force High

DD6 D–

Port 3

SE0 Status

Force Low

DD1 D+

Force High

DD5 D+

Port 2

SE0 Status

Force Low

DD1 D–

Force High

DD5 D–

Port 1

SE0 Status

7 6 5 4 3 2 1 0

Reserved Port 7

Diff. Data

Figure 16-8. Hub Ports Data Register 0x50 (read only), 1 = (D+ > D–), 0 = (D+ < D–)

Port 6

Diff. Data

Port 5

Diff. Data

Port 4

Diff. Data

Port 3

Diff. Data

Port 2

Diff. Data

Port 1

Diff. Data

16.4 Downstream Port Suspend and Resume

The Hub P orts Suspend Regis ter (Figur e 16 -9) and Hub Ports Resume Status Regis ter (F igure 16 -10) indic ate the s uspend an d
resume conditions on downstream ports. The suspend register must be set by firmware for any ports that are selectively sus­pended. Also, this register is only valid for ports that are selectively suspended.

If a port is marked as selectively suspended, normal USB traffic is not sent to that port. Resume traffic is also prevented from
going to that port, unless the Resu me com es from the s electively su spended port. If a resume condition is det ec ted o n the port,
hardware reflects a Resume back to the port, sets the Resume bit in the Hub Ports Resume Register, and generates a hub
interrupt.

If a disconnect occurs on a port marked as selectively suspended, the suspend bit is cleared.
The Devic e Remote W akeu p bit (bit 7) of the Hub P orts Suspend Regist er controls wheth er or not the re sume signal is propagated

by the hub after a connect or a disconnect event. If the Device Remote Wakeup bit is set, the hub will automatically propagate
the resume signal after a connect or a disconnect event. If the Device Remote Wakeup bit is cleared, the hub will not propagate
the resume signal. The setting of the Device Remote Wakeup flag has no impact on the propagation of the resume signal after
a downstream remote wakeup event. The hub will automatically propagate the resume signal after a remote wakeup event,
regardless of the state of the De vice Rem ote wak eup bit. The s tate of this bit has no impact on the generati on of the hub in terrupt.

A resume bit is set automatically when hardware detects a resume condition on a selectively suspended downstream port. The
resume condition is a differential ‘1’ for a low-speed device and a differential ‘0’ for a full-speed device.

These registers are cleared on reset or bus reset.

7 6 5 4 3 2 1 0

Device
Remote
Wakeup

Port 7
Selective
Suspend

Figure 16-9. Hub Ports Suspend Register 0x4D (read/write), 1 = Port is Selectively Suspended

Port 6
Selective
Suspend

Port 5
Selective
Suspend

Port 4

Selective

Suspend

Port 3
Selective
Suspend

Port 2

Selective

Suspend

Port 1

Selective

Suspend

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7 6 5 4 3 2 1 0

Reserved Resume 7 Resume 6 Resume 5 Resume 4 Resume 3 Resume 2 Resume 1

Figure 16-10. Hub Ports Resume Status Register 0x4E (read only), 1 = Port is in Resume State

Resume from a selectively suspended port, with the hub not in suspend, typically involves these actions:

1. Hardware detects the Resume , drives a K to the port, and generates the hub inte rrupt. The co rres po ndi ng bit in the Resume
Status Register (0x4E) reads ‘1’ in this case.

2. Firmware responds to hub interrupt, and reads register 0x4E to determine the source of the Resume.

3. Firmware begins driving K on the port for 10 ms or more through register 0x4B.

4. Firmware clears the Selective Suspend bi t for the port (0x4D), which clears the Resume bit (0x4E). This ends the hardware-driv­en Resume, b ut the firmw are-d riven Resume continues. To prevent tra ffi c bei ng fed by the hu b repe ater to the port during or
just after the Resume, firmware should disable this port.

5. Firmware drives a timed SE0 on th e p ort f o r two low-speed bi t t im es as ap pro priate. Firmware must d is able interrupts during
this SE0 so the SE0 pulse isn’t inadvertently lengthened, and appear as a bus reset to the downstream device.

6. Firmware drives a J on the port for one low-speed bit time, then it idles the port.

7. Firmware re-enables the port.

Resume when the hub is suspended typically involves these actions:

1. Hardware detects the Resume, drives a K on the upstream (which is then reflected to all downstream enabled ports), and
generates the hub interrupt.

2. The part comes out of suspend and the clocks start.

3. Once the clocks are stable, firmware execution resumes. An internal counter ensures that this takes at least 1 ms. Firmware
should check for Resume from any selectively suspended ports. If found, the Selective Suspend bit for the port should be
cleared; no other action is necessary.

4. The Resume ends when the host stops sending K from upstream. Firmware should check for changes to the Enable and
Connect Registers . If a port has become disabl ed but is still connec ted, an SE0 has been detecte d on the port. The port should
be treated as having been reset, and should be reported to the host as newly connected.

Firmware can choose to clear the Device Remote Wake-up bit (if set) to implement firmware timed states for port changes. All
allowed port changes wake the part. Then, the part can use internal timing to determine whether to take action or return to
suspend. If Device Remote Wake-up is set, automatic hardware assertions take place on Resume events.

16.5 USB Upstream Port Status and Control

USB status and control is regu lated b y the USB Status and Con trol Register, as shown in Figure 16-11. All bits in the register are
cleared during reset.

7 6 5 4 3 2 1 0

R/W R/W R R R/C R/W R/W R/W

Endpoint

Size

The three control bits allo w the upstream port to be driven ma nually b y firmware. F or normal USB operati on, all of these bits must
be cleared. Ta bl e 16-2 shows how the control bits affect the upstream port.

Endpoint

Mode

D+

Upstream

Figure 16-11. USB Status and Control Register 0x1F (read/write)

D–

Upstream

Bus Activity Control

Bit 2

32

Control

Bit 1

Control

Bit 0

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Table 16-2. Control Bit Definition for Upstream Port

Control Bits Control Action

000 Not Forcing (SIE Controls Driver)
001 Force D+[0] HIGH, D–[0] LOW
010 Force D+[0] LOW, D–[0] HIGH
011 Force SE0; D+[0] LOW, D–[0] LOW
100 Force D+[0] LOW, D–[0] LOW
101 Force D+[0] HiZ, D–[0] LOW
110 Force D+[0] LOW, D–[0] HiZ
111 Force D+[0] HiZ, D–[0] HiZ

Bus Activity (bit 3) is a “sticky” bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware
should check and clear this bit periodically to detect any loss of bus activity. Writing a ‘0’ to the Bus Activity bit clears it, while
writing a ‘1’ preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.

The Upstream D– and D+ (bits 4 and 5) are read only. These give the state of each upstream port pin individually: 1 = HIGH,
0=LOW.

Endpoint Mode (bit 6) and Endpoint Size (bit 7) are used to configure the number and size of USB endpoints. See Section 17.2
for a detailed description of these bits.

The hub generates an EOP at EOF1 in accordance with the USB 1.1 Specification, Section 11.2.2.

17.0 USB Serial Interface Engine Operation

The CY7C65x13 Serial Interface Engine (SIE) supports operation as a single device or a compound device. This section de­scribes the two device addresses, the configurable endpoints, and the endpoint function.

17.1 USB Device Addresses

The USB Controller provides two USB Device Address Registers (A and B). Upon reset and under default conditions, Device A
has three endpoints and Device B has two endpoints. The USB Device Address Register contents are cleared during a reset,
setting the USB device addresses to zero and disabling these addresses. Figure 17-1 shows the format o f the US B Address
Registers.

7 6 5 4 3 2 1 0

Device

Address

Enable

Bit 7 (Device Address Enable) in the USB Device Address Register must be set by firmware before the SIE can respond to USB
traffic to these addresses. The Device Address in bits [6:0] are set by firmware during the USB enumeration process to the
non-zero address assigned by the USB host.

17.2 USB Device Endpoints

The CY7C65x13 controller supports up to two addresses and five endpoints for communication with the host. The configuration
of these endpoints, and associated FIFOs, is controlled by bi ts [7 ,6] of th e US B Status and Cont rol Regis ter (s ee Figure 16-11).
Bit 7 controls the size of the endpoints and bit 6 controls the number of addresses. These configuration options are detailed in
Table 17-1. Endpoint FIFOs are part of user RAM (as shown in Section 5.4.1).

Device

Address

Bit 6

Device

Address

Bit 5

Figure 17-1. USB Device Address Registers 0x10, 0x40 (read/write)

Device

Address

Bit 4

Device

Address

Bit 3

Device

Address

Bit 2

Device

Address

Bit 1

Device

Address

Bit 0

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Table 17-1. Memory Allocation for Endpoints

Two USB addr: 3 EP for Addr A, 2 EP for Addr B One USB address (A), 5 EP

Reg 0x1F, Bits [7,6] = [0,0] Reg 0x1F,Bits [7,6] = [1,0] Reg 0x1F,Bits [7,6] = [0,1] Reg 0x1F,Bits [7,6] = [1,1]

Label

EPB1 0xD8 8 EPB0 0xA8 8 EPA4 0xD8 8 EPA3 0xA8 8
EPB0 0xE0 8 EPB1 0xB0 8 EPA3 0xE0 8 EPA4 0xB0 8

EPA2 0xE8 8 EPA0 0xB8 8 EPA2 0xE8 8 EPA0 0xB8 8
EPA1 0xF0 8 EPA1 0xC0 32 EPA1 0xF0 8 EPA1 0xC0 32
EPA0 0xF8 8 EPA2 0xE0 32 EPA0 0xF8 8 EPA2 0xE0 32

When the SIE writes data to a FI FO , the in ternal data b us is driven by the SIE; not the CPU. This causes a short delay in the C PU
operation. The delay is three clock cycles per byte. For example, an 8-byte data write by the SIE to the FIFO generates a delay
of 2 µs (3 cycles/byte * 83.33 ns/cycle * 8 bytes).

Start

Address Size Label

17.3 USB Control Endpoint Mode Registers

All USB devices are required to hav e a control endpo int 0 (EPA0 and EPB0) that is used to initiali ze and control e ach USB address.
Endpoint 0 provid es access to the de vice configur ation information an d allows generic USB status and control access es. Endpoint
0 is bidirectional to both receive and transmit data. The other endpoints are unidirectional, but selectable by the user as IN or
OUT endpoints.

The endpoint mode r egi ste rs are cl eare d d uring re se t. T he end poi nt zero EPA0 and EPB0 mode registers us e the format shown
in Figure 17-2. Note: In 5-endpoint mode, Register 0x42 serves as non-control endpoint 3, and has the format for non-control

endpoints shown in Figure 17-3.

Start

Address Size Label

Start

Address Size Label

Start

Address Size

7 6 5 4 3 2 1 0

Endpoint 0

SETUP

Received

Bits[7:5] in the end point 0 mode registers are sta tus bi ts tha t are se t b y the SIE to rep ort the type of tok en th at w as mos t recently
received by the corresponding device address. These bits must be cleared by firmware as part of the USB processing.

The ACK bit (bit 4) is set whene v er the SIE engages in a tr ansaction t o the register ’ s endpoin t that complete s with an A CK pac ket.
The SETUP PID status (bit 7) is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of

the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval, and subsequently, until the
CPU first does an IORD to this endpoint 0 mode register.

Bits[6:0] of the end poi nt 0 mode register are lo cked from CP U w rite operations whenever the SIE h as up date d o ne of these bits,
which the SIE does on ly at the en d of t he tok en p hase of a t rans action (SET UP... Data... ACK, OU T... Data... ACK, or IN... Data...
ACK). The CPU can unlock these bits by doing a subsequent read of this register. Only endpoint 0 mode registers are locked
when updated. The locking mechanism does not apply to the mode registers of other endpoints.

Because of these har dware locking f eatures, firmware must perf orm an IORD after an IOW R to an endpoint 0 registe r. Th is verifies
that the contents have changed as desired, and that the SIE has not updated these values.

While the SETUP b it is set, the CPU cannot write to t he endpoint z ero FIFOs . This pre vents fi rmware from ov erwriting an incoming
SETUP transaction be f ore fi rmware has a chance to re ad the SETUP data. R ef er to Table 17-1 for the appro priate endpo int z ero
memory locations.

The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown inTable 18-1.
Additional information on the mode bits can be found in Table 18-2 and Table 18-3. Note that the SIE offers an “Ack out - Status
in” mode and not an “Ack out - Nak in” mode. Therefore, if following the status stage of a C ont rol Write transfer a U SB hos t w ere
to immediat ely sta rt the next tran sfer, the new Setup packet co uld override the data payload of t he data s tage of the previo us
Control Write.

Endpoint 0

IN

Received

Figure 17-2. USB Device Endpoint Zero Mode Registers 0x12 and 0x42, (read/write)

Endpoint 0

OUT

Received

ACK Mode

Bit 3

Mode

Bit 2

Mode

Bit 1

Mode

Bit 0

17.4 USB Non-Control Endpoint Mode Registers

The format of the non-control endpoint mode registers is shown in Figure 17-3.

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7 6 5 4 3 2 1 0

STALL Reserved Reserved ACK Mode

Figure 17-3. USB Non-Control Device Endpoint Mode Registers 0x14, 0x16, 0x44, (read/write)

The mode bits (bits [3:0]) of the Endpoint Mode Register control how the endpoint responds to USB bus traffic. The mode bit
encoding is show n in Table 18- 1.

The ACK bit (bit 4) is set whene v er the SIE engages in a tr ansaction t o the register ’ s endpoin t that complete s with an A CK pac ket.
If STALL (bit 7) is set, the SIE stalls an OUT pac ket i f the mode bits are set to A CK-IN, and the SIE stalls an IN pac ket if the mode

bits are set to ACK-OUT. For all other modes, the STALL bit must be a LOW.
Bits 5 and 6 are reserved and must be written to zero during register writes.

Bit 3

17.5 USB Endpoint Counter Registers

There are five Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byte count i nformatio n for USB tra nsactions, as well as bits for d ata packet s tatus. The format of t hese regi sters is shown
in Figure 17-4:

7 6 5 4 3 2 1 0

Data 0/1

Toggle

Data Valid Byte Count

Bit 5

Figure 17-4. USB Endpoint Counter Registers 0x11, 0x13, 0x15, 0x41, 0x43 (read/write)

Byte Count

Bit 4

Byte Count

Bit 3

Mode

Bit 2

Byte Count

Bit 2

Mode

Bit 1

Byte Count

Bit 1

Mode

Bit 0

Byte Count

Bit 0

The counter bits (bits [5:0]) indic ate the n umber of dat a b ytes in a tr ansac tion. For IN transactions , firmw are load s the coun t with
the number of bytes to be tr an sm itt ed to the host from the endpoi nt FIFO. Valid values are 0 to 32 , i ncl us ive. For OUT or SETUP
transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes. Valid values are
2 to 34, inclusive.

Data Valid bit 6 is used for OUT and SETUP tok en s only. Data is loaded into the FIFOs during t he tr ans action , and th en the D ata
Valid bit is set if a proper CRC is received. If the CRC is not correct, the endpoint interrupt occurs, but Data Valid is cleared to a
zero.

Data 0/1 Toggle bit 7 selects t he D AT A pac ket’ s toggle state : 0 for D ATA0, 1 for D ATA1 . F or IN tr ans action s , firmware m us t set this
bit to the desired state. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.

Whenever the count updates from a SETUP or OUT transaction on endpoint 0, the counter register locks and cannot be written
by the CPU . Reading the register unloc ks it. This pre v ents firmware from ove rwriting a status update on inc oming SETUP or OUT
transactions befo re firmware ha s a chance to read the data. Only endpoint 0 counter r egister is l ock ed when u pdated. The l ockin g
mechanism does not apply to the count registers of other endpoints.

17.6 Endpoint Mode/Count Registers Update and Locking Mechanism

The contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in Figure 17-5. Two
time points, UPDATE and SETUP, are shown in the same figure. The following activities occur at each time point:

UPDATE:

1. Endpoint Mode Register - All the bits are updated (except the SETUP bit of the endpoint 0 mode register).

2. Counter Registers - All bits are updated.

3. Interrupt - If an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpoint is
set at this time. For details on what conditions are required to generate an endpoint interrupt, refer to Table 18-2.

4. The contents of the updated endpoi nt 0 mode a nd counter register s are loc k ed, e xce pt the SETUP b it of the end point 0 mod e
register which was locked earlier.

SETUP:
The SETUP bit of the endpo int 0 mode reg ister i s force d HIGH at t his tim e. Thi s bit is fo rced HI GH by the SIE until the end of the

data phase of a control write transfer. The SETUP bit can not be cleared by firmware during this time.
The affected mode and counter registers of endpoint 0 are locked from any CPU writes once they are updated. These registers

can be unlocked by a CPU read, only if the read operation occurs after the UPDATE. The firmware needs to perform a register
read as a part of the endpoint ISR processing to unlock the effected registers. The locking mechanism on mode and counter
registers ensures that the firmware recognizes the changes that the SIE might have made since the previous IO read of that
register.

35

1. IN Token

CY7C65013
CY7C65113

a)

S

Y
N
C

b)

A

I

N

Token Packet

S

Y
N
C

Token Packet

E

D

N

D

D

R

P

A

I

D

N

D
R

C
R
C

5

C

E

R

N

C

D

5

P

H

O

2. OUT or SETUP Token without CRC er ror

D

S

A

Y

T

N

A

C

1

Data Packet

update

data

S
Y
N
C

H/S Pkt

STALL

S

T

O

S

Y
N
C

A

U

D

T

D

Set

R

up

Token Packet

E

C

N

R

D

C

P

5

D

S

A

Y

T

N

A

C

1

Data Packet

data

C
R
C

1
6

NAK/

C
R
C

1
6

updateSetup

S

Y
N
C

H/S Pkt

S
Y

N

STALL

C

H/S Pkt

A
C
K

update

ACK,
NAK,

D
E
V

I
C
E

3. OUT or SETUP Token with CRC error

O

S
Y
N
C

A

E

U

D

T

D

Set

R

up

Token Packet

Figure 17-5. Token/Data Packet Flow Diagram

C

N

R

D

C

P

5

36

D

S

A

Y

T

N

A

C

1

Data Packet

data

update only if FIFO is

update only if FIFO is

Written (see Table 20-3)

Written (see Table 18-3)

C
R
C
1
6

CY7C65013
CY7C65113

18.0 USB Mode Tables

Table 18-1. USB Register Mode Encoding

Mode Encoding Setup In Out Comments

Disable 0000 ignore ignore ignore Ignore all USB traffic to this endpoint

Nak In/Out

0001

Status Out Only 0010 accept stall check For Control endpoints

Stall In/Out 0011 accept stall stall For Control endpoints

Ignore In/Out 0100 accept ignore ignore For Control endpoints

Isochronous Out 0101 ignore ignore always For Isochronous endpoints

Status In Only 0110 accept TX 0 stall For Control Endpoints

Isochronous In 0111 ignore TX cnt ignore For Isochronous endpoints

Nak Out 1000 ignore ignore NAK An ACK from mode 1001 --> 1000

[3]

Ack Out

(STALL

Ack Out(STALL

=0)

[3]

=1)

1001
1001

Nak Out - Status In 1010 accept TX 0 NAK An ACK from mode 1011 --> 1010
Ack Out - Status In 1011 accept TX 0 ACK This mode is changed b y SIE on is suan ce of ACK --> 1010

Nak In 1100 ignore NAK ignore An ACK from mode 1101 --> 1100

[3]

(STALL

Ack IN
Ack IN(STALL

=0)

[3]

=1)

1101
1101

Nak In - Status Out 1110 accept NAK check An ACK from mode 1111 --> 111 Ack In - Status Out
Ack In - Status Out 1111 accept TX cnt check This mode is changed by SIE on issuance of ACK -->1110

accept NAK NAK Forced from Se tup on Control en dpo int , from modes othe r

than 0000

ignore
ignore

ignore
ignore

ignore
ignore

TX cnt

stall

ACK

stall

ignore
ignore

This mode is chan ged b y SIE on iss uance of ACK --> 1000

This mode is chan ged b y SIE on iss uance of ACK --> 1100

The ‘In’ column represents the SIE’s response to the token type.
A disabled endpoint remains disabled until it is changed by firmware, and all endpoints reset to the disabled state.
Any SETUP pack et to an en able d endpoint with mode set to accep t SETUPs is cha nged b y the SIE to 0001 (NAKing ). Any mode

set to accept a SETUP, ACKs a valid SETUP transaction.
Most modes that control transactions involving an ending ACK, are changed by the SIE to a corresponding mode which NAKs

subsequent packets following the ACK. Exceptions are modes 1010 and 1110.
A Control endpoint has three extra status bits for PID (Setup, In and Out), but must be placed in the correct mode to function as

such. Non-Control endpoints should not be placed into modes that accept SETUPs.
A ‘check’ on an Ou t tok en during a Status tran sacti on ch ec ks to see that th e Out is of z ero len gth and has a Dat a Toggle (DT OG)

of ‘1. ’ If th e DTOG bit is set and the receiv ed Out P acke t has zero length , the Out is ACK ed to com plete the transactio n. Otherwise,
the Out is STALLed.

Note:

3. STALL bit is bit 7 of the USB Non-Control Device Endpoint Mode registers. For more information, refer to Section 17.4.

37

CY7C65013
CY7C65113

Table 18-2. D ecode table for Table 18-3: “Details of Modes for Differing Traffic Conditions”

Properties of incoming packet

Encoding Status bits What the SIE does to Mode bits

PID Status bits Interrupt?

End Point Mode
3 2 1 0 Token count buffer dval DTOG DVAL COUNT

Setup
In
Out

The validity of the received data

The quality status of the DMA buffer

The number of received bytes Acknowledge phase completed

Setup In Out ACK 3 2 1 0 Response Int

End Point
Mode

Legend:

UC: unchanged TX: transmit TX0: transmit 0-length packet
x: don’t care RX: receive
available for Control endpoint only

The response of the SIE can be summarized as follows:

1. The SIE only responds to valid transactions and ignores non-valid ones.

2. The SIE generates an interrupt when a val id tra nsaction is com pleted or w hen the FIFO is co rrupted. FIFO corruptio n occu rs
during an OUT or SETUP transaction to a valid internal address that ends with a non-valid CRC.

3. An incoming Data packet is valid if the count is <

Endpoint Size + 2 (includes CRC) and passes all error checking.

4. An IN is ignored by an OUT configured endpoint and vice versa.

5. The IN and OUT PID status is updated at the end of a transaction.

6. The SETUP PID status is updated at the beginning of the Data packet phase.

7. The entire Endpoint 0 mode register and the count register are locked from CPU writes at the end of any transaction to that
endpoint in which either an ACK is transferred or the mode bits have changed. These registers are only unlocked by a CPU
read of these regist ers, an d only if t hat read hap pens after t he tr ansaction c ompletes . This represents about a 1- µs window in
which the CPU is loc k ed from regi ster writes to th ese USB regist ers . Normally, the firmware should pe rf orm a regis ter rea d at
the beginning of the Endpoint ISRs to unlock and get the mode register information. The interlock on the Mode and Count
registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction.

38

CY7C65013
CY7C65113

Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2 for the decode legend)

End Point Mode PID Set End Point Mode

3 2 1 0 token count buffer dval DTOG DVAL COUNT Setup In Out ACK 3 2 1 0 response int

Setup Packet (if accepting)

See Table 18-1 Setup <= 10 data valid updates 1 updates 1 UC UC 1 0 0 0 1 ACK yes
See Table 18-1 Setup > 10 junk x updates updates updates 1 UC UC UC NoChange ignore yes
See Table 18-1 Setup x junk invalid updates 0 updates 1 UC UC UC NoChange ignore yes

Disabled

0 0 0 0 x x UC x UC UC UC UC UC UC UC NoChange ignore no
Nak In/Out
0 0 0 1 Out x UC x UC UC UC UC UC 1 UC NoChange NAK yes
0 0 0 1 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Ignore In/Out
0 1 0 0 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 0 0 In x UC x UC UC UC UC UC UC UC NoChange ignore no
Stall In/Out
0 0 1 1 Out x UC x UC UC UC UC UC 1 UC NoChange Stall yes
0 0 1 1 In x UC x UC UC UC UC 1 UC UC NoChange Stall yes

Control Write

Normal Out/premature status In
1 0 1 1 Out <= 10 data valid updates 1 updates UC UC 1 1 1 0 1 0 ACK yes
1 0 1 1 Out > 10 junk x updates updates updates UC UC 1 UC NoChange ignore yes
1 0 1 1 Out x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes
1 0 1 1 In x UC x UC UC UC UC 1 UC 1 NoChange TX 0 yes
NAK Out/premature status In
1 0 1 0 Out <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 0 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 0 1 0 In x UC x UC UC UC UC 1 UC 1 NoChange TX 0 yes
Status In/extra Out
0 1 1 0 Out <= 10 UC valid UC UC UC UC UC 1 UC 0 0 1 1 Stall yes
0 1 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
0 1 1 0 In x UC x UC UC UC UC 1 UC 1 NoChange TX 0 yes

Control Read

Normal In/premat ure status Out
1 1 1 1 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
1 1 1 1 Out 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 Stall yes
1 1 1 1 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes
1 1 1 1 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 1 1 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 1 1 1 In x UC x UC UC UC UC 1 UC 1 1 1 1 0 ACK (bac k) yes
Nak In/premature status Out
1 1 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
1 1 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 Stall yes
1 1 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes
1 1 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 1 1 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Status Out/extra In
0 0 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
0 0 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 Stall yes
0 0 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes

39

CY7C65013
CY7C65113

Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2 for the decode legend) (continued)

End Point Mode PID Set End Point Mode

3 2 1 0 token count buffer dval DTOG DVAL COUNT Setup In Out ACK 3 2 1 0 response int

0 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
0 0 1 0 Out x UC invalid UC UC UC UC 1 UC UC NoChange ignore no
0 0 1 0 In x UC x UC UC UC UC 1 UC UC 0 0 1 1 Stall yes

Out endpoint

Normal Out/erron eou s In
1 0 0 1 Out <= 10 data valid updates 1 updates UC UC 1 1 1 0 0 0 ACK yes
1 0 0 1 Out > 10 junk x updates updates updates UC UC 1 UC NoChange ignore yes
1 0 0 1 Out x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes
1 0 0 1 In x UC x UC UC UC UC UC UC UC NoChange ignore no

1 0 0 1 In x UC x UC UC UC UC UC UC UC NoChange Stall no

NAK Out/erroneous In
1 0 0 0 Out <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 0 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 0 0 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 0 0 0 In x UC x UC UC UC UC UC UC UC NoChange ignore no
Isochronous endpoint (Out)
0 1 0 1 Out x updates updates updates updates updates UC UC 1 1 NoChange RX yes
0 1 0 1 In x UC x UC UC UC UC UC UC UC NoChange ignore no

In endpoint

Normal In/errone ous Out
1 1 0 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore no

1 1 0 1 Out x UC x UC UC UC UC UC UC UC NoChange stall no

1 1 0 1 In x UC x UC UC UC UC 1 UC 1 1 1 0 0 ACK (back) yes
NAK In/erroneous Out
1 1 0 0 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 0 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Isochronous endpoint (In)
0 1 1 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 1 1 In x UC x UC UC UC UC 1 UC UC NoChange TX yes

(STALL

(STALL

(STALL

(STALL

[3]

= 0)

[3]

= 1)

[3]

= 0)

[3]

= 1)

40

19.0 Sample Schematic

CY7C65013
CY7C65113

USB-B

Vbus

D­D+

GND

SHELL

Optional

2.2 uF

Vbus

4.7nF

250 VAC

10M

0V

3.3v Regulator
IN

22x2(R

ext

Vref

1.5K
(R

6.000 MHz

)

UUP

0V

0V

OUT

GND

D0-

)

D0+

XTALO

XTALI

GND
GND

Vpp

.01 uF

Vcc

0V

Vref

2.2 uF

.01 uF

Vref

D1­D1+
D2-

D2+
D3-

D3+
D4-

D4+

0V

22x8(R

15K(x8)
(R

UDN

USB-A

Vbus
D­D+
GND

0V

USB-A

ext

)

Vbus

D­D+
GND

0V

USB-A

Vbus
D­D+
GND

)

0V

POWER

MANAGEMENT

0V

USB-A

Vbus
D­D+
GND

0V

41

CY7C65013
CY7C65113

20.0 Absolute Maximum Ratings

Storage Temperature ..........................................................................................................................................–65°C to +150°C

Ambient Temperature with Power Applied .................................................................................................................0°C to +70°C

Supply voltage on V

DC Input Vo ltage........................................................................................................................................... –0.5V to +V

DC Voltage applied to Outputs in High Z State............................................................................................. –0.5V to +VCC+0.5V

Po wer Dissipation .............................................. ...... ..... ...... .................................. ..... ...... ..................................................500 mW

Static Discharge Voltage ................................................................................................................................................... >2000V

Latch-up Current ............................................................................................................................................................ >200 mA

Max Output Sink Current into Port 0, 1, 2, 3 ...................................................................................................................... 60 mA

Max Output Sink Current into DAC[7:2] Pins...................................................................................................................... 10 mA

Max Output Source Current from Port 1, 2, 3, 4, 5, 6, 7 .................................................................................................... 30 mA

21.0 Electrical Characteristics

f

= 6 MHz; Operating Temperature = 0 to 70°C, VCC = 4.0V to 5.25V

OSC

V

REF

V

pp

I

CC

I

SB1

I

ref

I

il

V

di

V

cm

V

se

C

in

I

lo

R

ext

R

UUP

R

UDN

t

vccs

V

UOH

V

UOL

Z

O

R

up

V

ITH

V

H

V

OL

V

OH

4. Add 18 mA per driven USB cable (upstream or downstream. This is based on transitions every 2 full-speed bit times on average.

5. Power-on Reset occurs whenever the voltage on VCC is below approximately 2.5V.

Reference Voltage 3.15 3.45 V 3.3V ±5%
Programming Voltage (disabled) –0.4 0.4 V
VCC Operating Current 50 mA No GPIO source current
Supply Current—Suspend Mode 50 µA
V
Input Leakage Current 1 µAAny pin

Differential Input Sensitivity 0.2 V | (D+)–(D–) |
Differential Input Common Mode Range 0.8 2.5 V
Single Ended Receiver Threshold 0.8 2.0 V
Transceiver Capacit ance 20 pF
Hi-Z State Data Line Leakage –10 10 µA0V < V
External USB Series Resistor 19 21 Ω In series with each USB pin
External Upstream USB Pull-up Resistor 1.425 1.575 kΩ 1.5 kΩ ±5%, D+ to V
External Downstream Pull-do wn Resistors 14.25 15.75 kΩ 15 kΩ ±5%, downstream USB pins

VCC Ramp Rate 0 100 ms Linear ramp 0V to V

Static Output High 2.8 3.6 V 15 kΩ ±5% to Gnd
Static Output Low 0.3 V 1.5 kΩ ±5% to V
USB Driver Output Impedance 28 44 Ω In cluding R

Pull-up Resistance (typical 14 kΩ) 8.0 24.0 kΩ
Input Threshold Voltage 20% 40% V
Input Hysteresis Voltage 2% 8% V
Port 0,1,2,3 Output Low Voltage 0.4

Output High Voltage 2.4 V IOH = 1.9 mA (all ports 0,1,2,3)

relative to VSS....................................................................................................................–0.5V to +7.0V

CC

Parameter Min. Max. Unit Conditions

General

Operating Current 10 mA No USB Traffic

REF

[4]

USB Interface

< 3.3V

in

REG

Power On Reset

[5]

CC

USB Upstream/Downstream Port

REF

Resistor

ext

General Purpose I/O (GPIO)

All ports, low-to-high edge

CC

All ports, high-to-low edge

CC

V

IOL = 3 mA

2.0

V

I

OL

= 8 mA

CC

+0.5V

42

CY7C65013
CY7C65113

22.0 Switching Characteristics

(f

OSC

= 6.0 MHz)

Parameter Description Min. Max. Unit

Clock Source

f

OSC

t

cyc

t

CH

t

CL

t

rfs

t

ffs

t

rfmfs

t

dratefs

Clock Rate 6 ±0.25% MHz
Clock Period 166.25 167.08 ns
Clock HIGH time 0.45 t
Clock LOW time 0.45 t

USB Full Speed Signaling

[6]

CYC
CYC

Transition Rise Time 4 20 ns
Transition Fall Time 4 20 ns
Rise/Fall Time Matching; (tr/tf) 90 111 %
Full Speed Date Rate 12 ±0.25% Mb/s

Timer Signals

t

watch

Watch Dog Timer Period 8.192 14.336 ms

t

CYC

t

CH

CLOCK

t

CL

ns
ns

Figure 22-1. Clock Timing

t

r

10%

D+

D−

10%

t

r

90%

90%

Figure 22-2. USB Data Signal Timing

23.0 Ordering Information

Ordering Code PROM Size

Name Package Type

CY7C65013-PVC 8 KB O48 48-Pin (300-Mil) SSOP Commercial
CY7C65113-SC 8 KB S21 28-Pin SOIC Commercial
CY7C65013-PC 8 KB P25 48-Pin (600 Mil) PDIP Commercial
CY7C65113-PC 8 KB P21 28-Pin (300-Mil) PDIP Commercial

Document #:38-00590-*G

Note:

6. Per Table 7-6 of revision 1.1 of USB specification.

Package

Operating

Range

43

24.0 Package Diagrams

CY7C65013
CY7C65113

48-Lead Shrunk Small Outline Package O48

28-Lead (300-Mil) Molded DIP P21

51-85061-B

51-85014-B

44

CY7C65013
CY7C65113

24.0 Package Diagrams

(continued)

48-Lead (600-Mil) Molded DIP P25

51-85020-A

28-Lead (300-Mil) Molded SOIC S21

51-85026-A

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circui try embodied in a Cypress S emiconductor p roduct. Nor does it conv ey or imply an y license under pa tent or other rights. Cypre ss Semiconductor doe s not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.