Datasheet CY7C63742 Datasheet (CYPRESS)

enCoRe

PRELIMINARY

USB™ CY7C63722/23

CY7C63742/43

CY7C63722/23
CY7C63742/43

enCoRe™

USB
Combination Low-Speed USB & PS/2
Peripheral Controller

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 25, 2000

FOR

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enCoRe™

USB CY7C63722/23

PRELIMINARY

CY7C63742/43

TABLE OF CONTENTS

1.0 FEATURES .....................................................................................................................................5

2.0 FUNCTIONAL OVERVIEW .............................................................................................................6

2.1 enCoRe USB - The New USB Standard .......................................................................................6

3.0 LOGIC BLOCK DIAGRAM .............................................................................................................7

4.0 PIN CONFIGURATIONS .................................................................................................................7

5.0 PIN ASSIGNMENTS .......................................................................................................................7

6.0 PROGRAMMING MODEL ...............................................................................................................8

6.1 Program Counter (PC) ...................................................................................................................8

6.2 8-bit Accumulator (A) ....................................................................................................................8

6.3 8-bit Index Register (X) ..................................................................................................................8

6.4 8-bit Program Stack Pointer (PSP) ...............................................................................................8

6.5 8-bit Data Stack Pointer (DSP) ......................................................................................................8

6.6 Address Modes ..............................................................................................................................9

6.6.1 Data ........................................................................................................................................................9

6.6.2 Direct .....................................................................................................................................................9

6.6.3 Indexed ..................................................................................................................................................9

7.0 INSTRUCTION SET SUMMARY ...................................................................................................10

8.0 MEMORY ORGANIZATION ..........................................................................................................11

8.1 Program Memory Organization .................................................................................................. 1 1

8.2 Data Memory Organization .........................................................................................................12

8.3 I/O Register Summary .................................................................................................................13

9.0 CLOCKING ....................................................................................................................................14

9.1 Internal / External Oscillator Operation .....................................................................................15

9.2 External Oscillator .......................................................................................................................15

10.0 RESET .........................................................................................................................................15

10.1 Low Voltage Reset (LVR) ..........................................................................................................16

10.2 Brown Out Reset (BOR) ......... ............... ... ............... ............... .............. ............... ...................... 1 6

10.3 Watch Dog Reset (WDR) ....................... .............. ............... .... .............. ............... ...................... 1 6

11.0 SUSPEND MODE ..................... ............... .............. ............... ............... .............. ..........................1 6

11.1 Clocking Mode on Wake-up from Suspend .............................................................................1 7

11.2 Wake-up Timer ...........................................................................................................................17

12.0 GENERAL PURPOSE I/O PORTS .............................................................................................18

12.1 Auxiliary Input Port ................................ .............. ............... ............... .............. ..........................2 0

13.0 USB SERIAL INTERFACE ENGINE (SIE) .................................................................................20

13.1 USB Enumeration ......................................................................................................................21

13.2 USB Port Status and Control ....................................................................................................21

14.0 USB DEVICE ...............................................................................................................................22

14.1 USB Address Register ..............................................................................................................2 2

14.2 USB Control Endpoint ...............................................................................................................22

14.3 USB Non-Control Endpoints (2) ............................................................................................... 2 3

14.4 USB Endpoint Counter Registers ............................................................................................ 2 3

15.0 USB REGULATOR OUTPUT ......................................................................................................24

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TABLE OF CONTENTS

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CY7C63742/43

16.0 PS/2 OPERATION ...... .............. ............... .............. ............... ............... .............. ..........................24

17.0 SERIAL PERIPHERAL INTERFACE (SPI) .................................................................................25

17.1 Operation as an SPI Master ......................................................................................................26

17.2 Master SCK Selection ................................................................................................................26

17.3 Operation as an SPI Slave ........................................................................................................2 7

17.4 SPI Status and Control ..............................................................................................................27

17.5 SPI Interrupt ...............................................................................................................................28

17.6 SPI modes for GPIO pins ..........................................................................................................28

18.0 12-BIT FREE-RUNNING TIMER .................................................................................................29

19.0 TIMER CAPTURE REGI STERS ........................... ............... ............... .............. ............... ...........30

20.0 PROCESSOR STATUS AND CONTROL REGISTER ............ .............. ............... ............... .......32

21.0 INTERRUPTS ..............................................................................................................................33

21.1 Interrupt Vectors ........................................................................................................................34

21.2 Interrupt Latency .......................................................................................................................35

21.3 Interrupt Sources .......................................................................................................................35

21.3.1 USB Bus Reset or PS/2 Activit y ............... ......... .......................... .......... .......................... ................35

21.3.2 Free Running Timer Interrupts ........................................................................................................35

21.3.3 USB Endpoint Int e r ru pts ................... .......... ......... .......... ......... .........................................................35

21.3.4 SPI Inte rru pt .. ......... .......... .................................................................................... .............................35

21.3.5 Capture Timer Interrupts .................................................................................................................35

21.3.6 GPIO Inte rrupt ... .......... ......... .......... ................................. ......... .......... ......... ......................................35

21.3.7 Wake-up Interrupt .............................................................................................................................37

22.0 USB MODE TABLES ..................................................................................................................37

23.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................4 0

24.0 DC CHARACTERISTICS ............................................................................................................4 1

25.0 SWITCHING CHARACTERISTICS .............................................................................................4 2

26.0 ORDERING INFORMATION .......................................................................................................47

27.0 PACKAGE DIAGRAMS ..............................................................................................................47

LIST OF FIGURES

Figure 8-1. Program Memory Space with Interrupt Vector Table ..................................................11

Figure 9-1. Clock Oscillator On-chip Circuit ...................................................................................14

Figure 9-2. Clock Configuration Register (Address 0xF8) .............................................................14

Figure 10-1. Watch Dog Reset (WDR) ..............................................................................................16

Figure 12-1. Block Diagram of GPIO P ort (one pin shown) ............... ............... .............. ...............18

Figure 12-2. Port 0 Data (Add r ess 0x00)

..........................................................................................19

Figure 12-3. Port 1 Data (Address 0x01) ..........................................................................................19

Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A) ............................................................19

Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B) ............................................................20

Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C) ............................................................20

Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) ............................................................20

Figure 12-8. Port 2 Data Register (Address 0x02) .............................. ............... .............. ...............20

Figure 13-1. USB Status and Control Register (Address 0x1F) ....................................................21

Figure 14-1. USB Device Address Register (Address 0x10) ..........................................................22

Figure 14-2. USB EP0 Mode Register (Address 0x12) ....................................................................22

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PRELIMINARY

LIST OF FIGURES

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CY7C63742/43

Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14, 0x16) ..........................2 3

Figure 14-4. USB Device Counter Registers (Addresses 0x11h, 0x13h, 0x15) ............................23

Figure 16-1. Diagram of USB - PS/2 Syste m Connections ............. ............... ............... .............. ....25

Figure 17-1. SPI Block Diagram ........................................................................................................26

Figure 17-2. SPI Data Register (Address 0x60) ...............................................................................26

Figure 17-3. SPI Control Register (Address 0x61) ..........................................................................27

Figure 17-4. SPI Data Timing ............................................................................................................28

Figure 18-1. Timer LSB Register (Address 0x24) ...........................................................................29

Figure 18-2. Timer MSB Register (Address 0x25) ...........................................................................29

Figure 18-3. Timer Block Diagram ....................................................................................................29

Figure 19-1. Capture Timers Block Diagram ...................................................................................30

Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40) ...........................................31

Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41) ......................... .............. ....31

Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42) ...........................................31

Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43) ......................... .............. ....31

Figure 19-6. Capture Timers Configuration Register (Address 0x44) ............. .............. ...............31

Figure 19-7. Capture Timers Status Register (Address 0x45) .......................................................31

Figure 20-1. Processor Status and Control Register (Address 0xFF) ..........................................32

Figure 21-1. Global Interrupt Enable Register 0x20h (read/write) .................... .............. ...............33

Figure 21-2. USB End Point Interrupt Enable Register (Address 0x21) .......................................33

Figure 21-3. Interrupt Controller Logic Block Diagram ..................................................................34

Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04) ....... ............... ............... .............. ....36

Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05) ....... ............... ............... .............. ....36

Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06) .....................................................36

Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07) .....................................................36

Figure 21-8. GPIO Interrupt Diagram ............................. ............... .............. ............... ............... .. .....36

Figure 25-1. Clock Timing ..................... ............... ............... .............. ............... ............... ..................43

Figure 25-2. USB Data Signal Timing ...................... .............. ............... ............... .............. ............... 4 3

Figure 25-3. Receiver Jitter Tolerance ......... .............. ............... ............... .............. ............... ...........44

Figure 25-4. Differential to EOP Transition Skew and EOP Widt h ...................... ............... ...........44

Figure 25-5. Differential Data Jitter ..................................................................................................44

Figure 25-7. SPI Slave Timing, CPHA=0 ..........................................................................................45

Figure 25-6. SPI Master Timing, CPHA=0 ........................................................................................45

Figure 25-8. SPI Master Timing, CPHA=1 ........................................................................................46

Figure 25-9. SPI Slave Timing, CPHA=1 ..........................................................................................46

LIST OF TABLES

Table 8-1. I/O Register Summary ......................................................................................................1 3

Table 11-1. Wake-up Timer Adjust Settings .................................................................................... 18

Table 12-1. Ports 0 and 1 Output Control Truth Table ...................................................................19

Table 13-1. Control Modes to Force D+/D– Outputs .......................................................................22

Table 17-1. SPI Control Register Definitions ...................................................................................27

Table 17-2. SPI Pin Assignments .....................................................................................................28

Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) ............ 3 2

Table 21-1. Interrupt Vector Assignments .......................................................................................34

Table 22-1. USB Register Mode Encoding ......................................................................................37

Table 22-2. Decode table for

Table 22-3

: “Details of Modes for Differing Traffic Conditions” ...3 8

Table 22-3. Details of Modes for Differing Traffic Conditions .......................................................39

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USB CY7C63722/23

PRELIMINARY

CY7C63742/43

1.0 Features

• enCoRe™ USB - enhanced Component Reduction
—Internal oscillator eli m inates the need for an exte rnal crystal or resonator

—Interface can auto-configure to opera te as PS/2 or USB without the need for external components to switch between

modes (no GPIO pins needed to manage dual mode capability)

—Internal 3.3V regulator for USB pull-up resistor
—Configurable GPIO for real-world interface without external components

• Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads,

joysticks, and many others.

• USB Specification Complia nce
—Conforms to USB Specification, Version 1.1
—Conforms to USB HID Specification, Version 1.1

—Supports 1 Low-Speed USB device address and 3 data endpoints
—Integrated USB transceiver
—3.3V regulated output for USB pull-up resist or

• 8-bit RISC microcontroller
—Harvard architecture
—6-MHz external ceramic resonator or internal clock mode
—12-MHz internal CPU clock
—Internal memory
—256 bytes of RAM
—6 Kbytes of EPROM (CY7C63722, CY7C63742)
—8 Kbytes of EPROM (CY7C63723, CY7C63743)
—Interface can auto-configure to operate as PS/2 or USB
—No external components for switching between PS/2 and USB modes
—No GPIO pins needed to manage dual mode capability

• I/O ports
—Up to 16 versatile General Purpose I/O (GPIO) pins, individually configurable
—High current drive on any GPIO pin: 50 mA/pin current sink

—Each GPIO pin supports high-impedance i nputs, internal pull-ups, open dr ain outputs or traditional CMOS outputs
—Maskable interrupts on all I/O pins

• SPI serial communication block
—Master or slave operation

—2 Mbit/s transfers

• Four 8-bit Input Capture registers
—Two registers each for two input pins
—Capture timer setting with 5 pre-scaler settings

—Separate registers for rising and falling edge capture
—Simplifies interface to RF inputs f or wir eless applications

• Internal lo w -power wake-up timer during suspend mode
—Periodic wake-up with no external components

• Optional 6-MHz internal oscillator mode
—Allows fast start-up from suspend mode

• Watch dog timer (WDT)

• Low Voltage Reset at 3.75V

• Internal br own-out reset for suspend mode

• Improved output drivers to reduce EMI

• Operating vol tage from 4.0V to 5.5VDC

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USB CY7C63722/23

PRELIMINARY

• Operating temperature from 0 to 70 degrees Celsius

• CY7C63722/23 available in 18-pin PDIP

• CY7C63742/43 available in 24-pin SOIC, 24-pin PDIP

• Industry standard programmer support

CY7C63742/43

2.0 Functional Overview

2.1

Cypress has re-invented its leadership position in the low-speed USB market with a new family of innovative microcontrollers.
Introducing...
create a new family of low-speed USB microcontrollers that will enable peripheral developers to design new products with a
minimum number of components. At the heart of our
oscillator. By int egrat ing t he osc illato r into our chi p , an e xternal crystal o r resona tor is no longer need ed. We ha ve also integrated
other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a

3.3V regulator. All of this adds up to a lower system cost.
The CY7C63722/23 and CY7C63742/ 43 are 8-bit RISC One Time Progr ammable (O TP) mic rocontroll ers. The instructi on set has

been optimiz ed specif ical ly f or USB an d PS/ 2 opera tions , al though t he mi crocont roll ers ca n be u sed f or a va riety o f o ther embed ­ded applications.

The CY7C637xx features up to 16 general purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins
are grouped into two ports (Port 0 to 1) where each pin can be i ndividually configured as i nputs with internal pull-ups, open drain
outputs, or tr adit ional CMOS outpu ts with pr og rammab le driv e streng th o f up to 50 mA out put driv e . Addit ional ly, each I/O pin can
be used to gener at e a GPIO inte rrupt to t he mi crocont roll er . Note t he GPI O inter rupts all shar e the s ame “GPIO” int errupt vect or .

The CY7C637xx microcontrollers feature an internal 5% accurate 6-MHz clock source. Optionally, an external 6-MHz ceramic
resonator can be used to provide a highe r precision reference for USB operation. This cloc k generator reduces the clock-related
noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontrol ler.

The CY7C637xx is offered with two EPROM options to maximize flexibility and minimize cost. The CY7C637x2 has 6 Kbytes of
EPROM. The CY7 C637x3 has 8 Kbyt es of EPR OM. Al l v ersi ons hav e 2 56 b ytes of dat a RAM f or stac k spac e, u ser v ariab l es, and
USB FIFOs.

These parts include low-voltage reset logic, a watch dog timer, a vectored interrupt controller, a 12-bit free-running timer, and
capture timers. The l ow-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state,
and begins executing instructions at EPROM addres s 0x0000. LVR will also reset the part when V
voltage r ange. The watch dog timer can be used to ensure the firmware never gets stalled for more than approxim ately 8 ms.

The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB
Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, two capture timers, an internal
wake-up timer and the GPIO ports. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after
USB transact ions c omple te on t he b us. Th e captur e ti mers in terrupt whene v er a ne w tim er v alue i s sav ed due to a sel ected GPIO
edge event. The GPIO ports have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional
flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be
either rising or falling edge.

The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 µs and 1.024 ms ). The timer
can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event,
and subtracting the two values. The four capture timers save a programmable 8 bit range of t he free-running timer when a GPIO
edge occurs on the two capture pins (P0.0, P0.1).

The CY7C637xx incl udes an int egrat ed USB seri al int erf ace eng in e (SIE) that su pports the int egrat ed p eripher als. The har dwar e
supports one USB device ad dress with t hree endpoin ts. The SIE all ows the USB host to communicat e with the funct ion integr ated
into the microcontroller. A 3.3V regulated output pin provides a pull-up source for t he external USB resistor on the D– pin.

The USB D+ and D– USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to
respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and
SDATA, the ability to disable the re gulato r output pin, and an interru pt to signal t he start of PS/2 activity. No external components
are necessary fo r dual USB and PS/2 sys tems, and no GPIO pins need to be dedic ated to s witc hing betw een modes . Slo w edge
rates operate in both modes to reduce EMI.

enCoRe

USB - The New USB Standard

enCoRe

USB—“enhanced Componen t Reducti on.” Cy press has leveraged its design e xpertise in USB solutions to

enCoRe

TM

USB technology is the breakthrough design of a crystal-less

drops below the operat ing

CC

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USB CY7C63722/23

3.0 Logic Block Diagram

Internal

Oscillator

Oscillator

EPROM

6K/8 K B yte

Brown-out

Reset

Watch

Dog

Timer

Low

Voltage

Reset

4.0 Pin Configurations

CY7C63722/23

18-pin PDIP

P0.0
P0.1
P0.2
P0.3

VSS
VPP

VREG

XTALIN/P2.1

PRELIMINARY

Xtal

8-bit

RISC

core

1
2
3
4
5
6
7
8
9

18
17
16
15
14P1.0
13
12
11
10

Wake-Up

Interrupt

Contro ller

Regulator

P0.4
P0.5

P0.6
P0.7
P1.1

D+/SCLK
D–/SDATA
VCC
XTALOUT

Timer

3.3V

VREG

256 Byte

Top View

RAM

USB

Engine

USB &

PS/2

Xcvr

D+,D–

12-bit
Timer

Port 1
GPIO

P1.0–P1.7

CY7C63742/43

24-pin SOIC/PDIP

P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
P1.4
P1.6

VSS

VPP

VREG

XTALIN/P2.1

CY7C63742/43

Capture

Timers

Port 0
GPIO

P0.0–P0.7

24
23
22
21
20
19
18
17
16
15
14
13

P0.4
P0.5

P0.6
P0.7

P1.1
P1.3
P1.5
P1.7
D+/SCLK
D–/SDATA
VCC
XTALOUT

1
2
3
4
5
6

7
8
9
10
11
12

SPI

5.0 Pin Assignments

CY7C63722/23 CY7C63742/43

Name I/O

D–/SDATA,
D+/SCLK

P0[7:0] I/O 1, 2, 3, 4,

I/O 12

13

15, 16, 17, 18

15
16

1, 2, 3, 4,

21, 22, 23, 24

P1[7:0] I/O 5, 14 5, 6, 7, 8,

17, 18, 19, 20

XTALIN/P2.1 IN 9 12 6-MHz cerami c resonator or ext ernal clock input, or P2.1 input
XTALOUT OUT 10 13 6-MHz cerami c resonator return pin or internal oscillator output
V

PP

V

CC

7 10 Programming v oltage supply, ground for normal oper ati on

11 14 V olt age supply

VREG/P2.0 8 11 Vo ltage su ppl y for 1.5-kΩ USB pull-up resistor (3.3V nomi nal). Als o

V

SS

6 9 Ground

Description18-Pin 24-Pin

USB diff erential data lines (D– and D+), or PS/2 clock and data sig­nals (SDATA and SCLK)

GPIO Po rt 0 capable of sinking up t o 50 mA/pin, or sinking co ntrolled
low or high prog rammable current. Can also source 2 mA current,
provide a res istive pul l-up , or serve as a high impedance input. P0. 0
and P0.1 provi de inputs to Capture Timers A and B, respect ively.

IO Port 0 capable of sinking up to 50 mA/pin, or sinking controlled
low or high prog rammable current. Can also source 2 mA current,
provide a resistive pull-up, or serve as a high impedance input.

serves as P2.0 input.

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USB CY7C63722/23

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CY7C63742/43

6.0 Programming Model

Refer to the

6.1 Program Counter (PC)

The 13-bit program counter (PC) allows access for up to 8 Kbytes of EPROM using the CY7C637xx architecture. The program
counter is cleared during res et, such that the first instruction executed after a reset is at ad dress 0x0000. This is typically a jump
instruction to a res et handler that initializes the applicat ion.

The lower 8 bi ts of the progr am counter are incremented as i nstructio ns are loaded and e xecu ted. The upp er 5 bits of the pr ogram
counter are increment ed by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page”
of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will ca use the assembler to inser t
XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to
insert a NOP followed by an XPAGE for correct execution.

The program counte r of t he ne xt i nstruct ion t o be e x ecut ed, car ry flag, and z er o fla g are sav ed a s two b yt es on the prog ram stack
during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zer o flag are restored from the
program stack only during a RETI instructio n.

Please note the program counter cannot be accessed directly by the firmware. The progr am stack can be examined by reading
SRAM from locat ion 0x00 and up.

6.2 8-bit Accumulator (A)

The accumulator is the general purpose, do everything register in the architecture where results are usually calculated.

6.3 8-bit Index Register (X)

The inde x r egist er “X” is availabl e to the firmware as an auxiliary accu mulator . The X register also allows the processor to perf orm
indexed operations by loading an index value into X.

CYASM Assembler User’s Guide

for more details on f irmwar e operation with the CY7C637xx mic rocontrollers.

6.4 8-bit Program Stack Pointer (PSP)

During a reset, the pr ogram stack pointer (PSP) is set to zero. This m eans the program “stack” starts at RAM address 0x00 and
“grows” upward from there . Note the prog ram stac k pointe r is directl y address ab le under firmware control , using the MO V PSP,A

instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware
control.

During an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two
bytes of data memory . The first byte is stor ed in the memory addressed by the progr am stack pointe r, then the PSP is inc remented.
The second b yte is stored in memory addressed by the program stac k pointer and the PSP is incremented again. Th e net effect
is to store the progr am cou nter and flags on the program “stack” and increment the program stack pointer by two.

The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory
addressed by the PSP. The program stack pointer is decremented again and the first byte is restored from memory addressed
by the PSP. Aft er th e prog r am cou nter and flags hav e be en rest ored fr om stac k, the inte rrupts are en ab le d. The eff e ct i s to res tore
the program counter and flags from the program stack, decrement the pr ogram stack pointer by two, and re-enable interrupt s.

The call subr outine (CAL L) instruction s tores the p rogram counter and flags on t he progra m stack and incremen ts the PSP b y two .
The return fr om subr out ine ( RET) ins tructi on re sto res t he prog r am co unter, but not th e fla gs, from pr og ram stac k and decrement s

the PSP by two.
Note that t here ar e rest ricti ons i n us ing some ju mp , cal l, a nd index instructions across the 4KB boundary of the prog ram memory.

Refer to the

CYASM Assembler User’s Guide

for a detailed description.

6.5 8-bit Data Stack Pointer (DSP)

The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
instruction wi ll pre- decr ement th e DSP, then write data to t he memory l ocatio n address ed b y the DSP. A POP instruction will rea d
data from the memory location addressed by the DSP, then post-increment the DSP.

During a reset, the Data Stack Poi nter will be set to zero. A PUSH instruction when DSP equal zero will write data at th e to p of
the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB
applications, this works fine and is not a prob lem.

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For USB appl icati ons, the fi rmware sh ould set the DSP t o an a ppropria te loc ation to av o id a memory conf lict wi th RAM dedicat ed
to USB FIFOs. The memory requirements for the USB endpoints are shown in Section 8.2. For example, assembly instructions
to set the DSP to 20h (giving 32 bytes for program and data stack combined) are shown below:

MOV A,20h ; Move 20 hex into Accumulator (must be D8h or le ss to avoid USB FIFOs)
SWAP A,DSP ; swap accumulator value into DSP register

CY7C63742/43

6.6 Address Modes

The CY7C637xx microcontrollers support three addressing modes for instructions that require data operands: data, direct, and
indexed.

6.6.1 Data

The “Data” address mode ref er s to a da ta operand that i s a ctual ly a con stant encod ed in t he inst ructi on. As an e xa mple, cons ider
the instruction that loads A with the constant 0x30:

• MOV A, 30h

This instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the
second byte. The second byt e of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior
“EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown
above:

• DSPINIT: EQU 30h

• MOV A,DSPINIT

6.6.2 Direct

“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address
location 0x10h:

• MOV A, [ 10h]

In normal usage, variable nam es are assigned to var iable addresses using “EQU” statements to improve the readability of the
assembl er source code. As an example, the following code is equivalent to the example shown above:

• buttons: EQU 10h

• MOV A,[buttons]

6.6.3 Indexed

“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the
“base” address of an array of data and the X register will contain an index that indicates which element of the array is actually
addressed:

• array: EQU 10h

• MOV X,3

• MOV A,[x+array]

This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth
element would be at add ress 0x13h.

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7.0 Instructio n Set Summary

Refer to the

HALT 00 7 NOP 20 4
ADD A,expr data 01 4 INC A acc 21 4
ADD A,[expr] direct 02 6 INC X x 22 4
ADD A,[X+expr] index 03 7 INC [expr] direct 23 7
ADC A,expr data 04 4 INC [X+expr] index 24 8
ADC A,[expr] direct 05 6 DEC A acc 25 4
ADC A,[X+expr] index 06 7 DEC X x 26 4
SUB A,expr data 07 4 DEC [expr] direct 27 7
SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8
SUB A,[X+expr] index 09 7 IORD expr address 29 5
SBB A,expr data 0A 4 IOWR expr address 2A 5
SBB A,[expr] direct 0B 6 POP A 2B 4
SBB A,[X+expr] index 0C 7 POP X 2C 4
OR A, ex pr data 0D 4 PUSH A 2D 5
OR A,[expr] direct 0E 6 PUSH X 2E 5
OR A,[X+expr] index 0F 7 SWAP A,X 2F 4
AND A,expr data 10 4 SWAP A,DSP 30 4
AND A,[expr] direct 11 6 MO V [expr],A direct 31 5
AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6
XOR A,expr data 13 4 OR [expr],A direct 33 7
XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8
XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7
CMP A,expr data 16 5 AND [X+expr],A index 36 8
CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7
CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8
MOV A,expr data 19 4 IOWX [X+expr] index 39 6
MOV A,[ex pr] direct 1A 5 CPL 3A 4
MOV A,[X+expr] index 1B 6 ASL 3B 4
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[ex pr] direct 1D 5 RLC 3D 4

reserved

XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50 - 5F 10
JMP addr 80-8F 5 JC addr C0-CF 5
CALL addr 90-9F 10 JNC addr D0-DF 5
JZ addr A0-AF 5 JACC addr E0-EF 7
JNZ addr B0-BF 5 INDEX addr F0-FF 14

CYASM Assembler User’s Guide

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles

for det ailed information on these instructions.

1E RRC 3E 4

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8.0 Memory Organization

8.1 Program Memory Organization

After re s e t Address

13 -bit PC 0x0000 Program execution begins here after a reset.

CY7C63742/43

0x0002 USB Bus Reset interrupt vector

0x0004 128-µs timer interrupt vector

0x0006 1.024-ms timer interrupt vector

0x0008 USB endpoint 0 interrupt vector

0x000A USB endpoint 1 interrupt vecto r

0x000C USB endpoint 2 interrupt vecto r

0x000E SPI interrupt vector

0x0010 Capture timer A interrupt Vector

0x0012 Capture timer B interrupt vector

0x0014 GPIO inte r r u pt vec tor

0x0016 Wake-up i n terrupt vector

0x0018

0x0FFF

0x17FF

0x1FDF 8 KB PROM ends here (CY7C63723, CY7C63743)

Program Memory begins here

4 KB

6 KB PROM ends here (CY7C63722, CY7C63742)

(8K - 32 bytes)

Figure 8-1. Program Memory Space with Interrupt Vector Table

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8.2 Data Memory Organization

The CY7C637xx microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas:
program stack, data stack , user variables and USB endpoint FIFOs as shown below:

After re s e t Address

8-bit D S P 8-bit PSP 0x00

(Move DSP)

8-bit DSP user selected

User Var iables

0xE8

USB FIFO for Address A endpoint 2

0xF0

USB FIFO for Address A endpoint 1

Program Stack Gr owth

Data Stack Growth

0xF8

Top of RAM Memory 0xFF

USB FIFO for Address A endpoint 0

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8.3 I/O Register Summary

I/O registers are accessed via the I/O Read (IORD) and I/O Write ( IOWR, IOWX) instructions. IORD reads the selected port into
the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X
to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that
specifying address 0 with IOWX (e.g., IOW X 0h) means the I/O port is selected solely by the contents of X.

Note: All bits of all registers are cleared to all zeros on reset,

All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always

0xFF).

be written as 0.

Table 8-1. I/O Register Summary

Register Name I/O Address Read/Write Function Fig.

Port 0 Data 0x00 R/W GPIO Port 0 12-2
Port 1 Data 0x01 R/W GPIO Port 1 12-3
Port 2 Data 0x02 R Auxiliary input regis ter for D+, D–, VREG, XTALIN 12-8
Port 0 Interrupt Enabl e 0x04 W Interrupt enable for pins in Port 0 21-4
Port 1 Interrupt Enabl e 0x05 W Interrupt enable for pins in Port 1 21-5
Port 0 Interrupt Polarity 0x06 W Interrupt polarity for pins in Port 0 21-6
Port 1 Interrupt Polarity 0x07 W Interrupt polarity for pins in Port 1 21-7
Port 0 Mode0 0x0A W Controls output configuration for Port 0 12-4
Port 0 Mode1 0x0B W 12-5
Port 1 Mode0 0x0C W Controls output configuration for Port 1 12-6
Port 1 Mode1 0x0D W 12 -7

USB Device Address 0x10 R/W USB Device Address register 14-1
EP0 Counter Register 0x11 R/W USB Endpoint 0 counter regi ster 14-4
EP0 Mode Register 0x12 R/W USB Endpoint 0 configuration register 14-2
EP1 Counter Register 0x13 R/W USB Endpoint 1 counter regi ster 14-4
EP1 Mode Register 0x14 R/W USB Endpoint 1 configuration register 14-3
EP2 Counter Register 0x15 R/W USB Endpoint 2 counter regi ster 14-4
EP2 Mode Register 0x16 R/W USB Endpoint 2 configuration register 14-3
USB Status & Control 0x1F R/W USB status and control re gister 13-1

Global Interrupt Enable 0x20 R/W Global interrupt enable register 21-1
Endpoint Interrupt Enab le 0x21 R/W USB endpoint interrupt enables 21-2
Timer (LSB) 0x24 R Lower 8 bits of free-running timer (1 MHz) 18-1
Timer (MSB) 0x25 R Upper 4 bits of free-running timer 18-2
WDR Clear 0x26 W Watch Dog Reset clear -

Capture Timer A Rising 0x40 R Rising edge Capture Timer A data register 19-2
Capture Timer A Fa ll ing 0x41 R Falling edge Capture Timer A data register 19-3
Capture Timer B Rising 0x42 R Rising edge Capture Timer B data register 19-4
Capture Timer B Fa ll ing 0x43 R Falling edge Capture Timer B data register 19-5
Capture TImer Conf iguration 0x44 R/W Capture Timer configuration register 19-6
Capture Timer Status 0x45 R Capture Timer status register 19-7

SPI Data 0x60 R/W SPI read and write data register 17-2
SPI Control 0x61 R/W SPI status and control register 17-3

Clock Configuration 0xF8 R/W Internal / External Clock configuration register 9-2
Processor Status & Control 0xFF R/W Processor status and contr ol 20-1

except the Processor Status and Control Register (address

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9.0 Clocking

The chip can be clocked from either the internal on-chip clock, or from an oscillator based on an ex ternal resonator/crystal, as
shown in
Configuration Register,

Figure 9-1

Clk2x (12 MHz)

(to Microcontroller)

. No addit ional capacitan ce is included on chip at the XTALIN/OUT pins. Oper ati on is controlled by the Clock

Figure 9-2

Int Clk Output Disable

Interna l Osc

Ext Clk Enable

Clk1x (6 MHz)

(to USB SIE)

.

Clock

Doubler

XTALOUT

XTALIN

30 pF

Port 2.1

Figure 9-1. Clock Oscillator On-chip Circui t

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W - R/W R/W

Ext. Clock

Resume

Delay

All bits of the Clock Configuration Register reset to 0. Reserved bits must always be written as a 0.
Setting External Oscillator Enable (bit 0) high causes the part to switch to external clock mode, as described in Section 9.1. (If

the bit is already set, writing a ‘1’ again has no effect.) Clearing this bit has no immediate effect, although the state of this bit is
used when waking out of suspend mode to select between internal and external clock. When this bit is cleared XTALIN will be
configured as an input with a weak pull down and can be used as a GPIO input (P2.1).

The Internal Clock Output Disable ( bit 1) can be set to 1 to keep the internal clock from driving out to XTALOUT. If set, XTALOUT
will drive hi gh. Thi s bit has no effect when the external oscillator is enabled.

The Precisi on USB Clocking Enabl e (bit 2) only affects operation in Internal Oscillator M ode. In that mode, this bit mus t be set to
1 to cause t he internal c lo ck t o a utomati call y preci se ly tu ne to USB t iming r equir ement s (6 M Hz ±1. 5%). The f requ ency m ay ha v e
a looser initia l to lerance at power-up, but all USB transmissions from the chip wil l meet the USB specification.

The Low Voltage Reset Disable (bit 3) disables the LVR circuit when set to 1. See Section 10.1.
The Wake-up Timer Adjust Bits (bit s 6:4) are used to adjust the Wake-up timer period, as descri bed in Section 11.2.
The Resume Delay (bit 7) selects the delay time when switching to the external oscillator, or when waking from suspend mode

with the e xternal oscil lator enab led. The del ay is 128 µs when this bit is 0, and 4 ms when this bit is 1. The sho rter time is adequat e
for operation with ceramic re sonators, while the long er ti m e is preferred for start-up with a crystal. (These times
an initial osci llator st art-up time which depends on t he resonatin g element. This ti me is typicall y 50–100 µs for ce ramic r esonators
and 1–10 ms for crystals). When waking from suspend mode with the internal osci llator , t he delay time is only 8 µs in addition to
a delay of appr oximately 1 µs for the oscillator to start.

Wake-up

Timer Adjust

Bit 2

Wake-up

Timer Adjust

Bit 1

Figure 9-2. Clock Configuration Register (Address 0xF8)

Wake-up

Timer Adjust

Bit 0

Low Voltage

Reset

Disable

Precision

USB Clocking

Enable

Internal Clock

Output

Disable

External

Oscillator

Enable

do not include

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9.1 Internal / External Oscillator Operation

The internal oscillator provi des an operating clock, factory set to a nominal frequency of 6 MHz. This clock requires no external
components . At power-up, the chip operates from the internal c lock. In this mode, t he internal clock is b uffered and driven to the
XTALOUT pin by default, and the state of the XTALIN Pin can be read at Port 2.1. While the internal clock is enabled, its output
can be disable d at the XTALOUT pin by setting the Internal Clock Output Disable bit of the Clock Confi guration Register.

Setting bit 0 o f the Cl oc k Confi gura tion Reg ister disab l es the i nternal cloc k, and ha lts t he pa rt while the e x ternal resona tor/crystal
oscillator is started. The steps involved in switching from Internal to External Cloc k m ode are as follows:

1. At reset, chip begins operation using the internal clock.

2. Firmware sets Bit 0 of the Clock Configuration Register. For example,
mov A, 1h ; Set Bit 0 (External Oscillator Enable); bit 7 cleared gives fas ter start-up

iowr F8h ; Write to Clock Configuration Register

3. Internal clocking is halted, the internal oscillator is disabled, and the external cloc k oscillator is enabled.

4. After the e xternal cloc k bec omes sta ble , ch ip cloc ks are re -enab le d using the e xternal cloc k signal . (Note t hat the tim e for the

external cl ock to become stable depends on the external resonating device; see next section.)

5. After an addition al del ay the CPU i s released to run. This delay depends on the state of the Ext. Clock Resum e Delay bit of

the Clock Configuration Register. The time is 128 µs if the bit is 0, or 4 ms if the bit is 1.

6. Once the chip ha s been set to ext ernal oscill ator , it can only retu rn to internal cloc k when wak ing from sus pend mode. Clearing

bit 0 of the Clock Conf iguration Register will not re-enable internal clock mode until suspend mode is ent ered. See Section

11.0 for more details on suspend mode oper ation.

If the Internal Clock is enabled, the XTALIN pin can serve as a general purpose input, and its state can be read at Port 2, Bit 1
(P2.1) . Refer to
cannot provi de an interrupt source to the CPU .

Figure 12-8

for the Port 2 data register. In this mode, there is a weak pull-down at the XTALIN pin. This input

9.2 External Oscillator

The user can connect a l ow-cost ceramic re sonator or an external osci ll ator to the XTALIN / XTALOUT pins to provi de a precise
reference frequency for the chip clock, as shown in
crystal with external capacitors. To run from the external resonator, Bit 0 o f the Clock Conf iguration Register must be set to 1, as
explained in the previous section.

Start up times for the external oscillator depend on the resonating device. Ceramic resonator based oscillators typically start in
less than 100 µs, while cryst al based oscillators take l onger, typically 1 to 10 ms. Board capacitance s hould be minimized on the
XTALIN and XTALOUT pins by keeping the traces as short as possible.

An external 6 MHz cloc k can be appli ed to the XTALIN pin if the XTALOUT pin is left open.

Figure 9-1

. The ext ernal components required are a ceramic resonator or

10.0 Reset

The USB Controller supports three ty pes of resets. The effects of the reset are listed below. The reset types are:

1. Low Voltage Reset (L VR)

2. B rown Out Res e t (B O R)

3. Watch Dog Reset (WDR)

The occurrence of a reset is recorded in the Processor Status and Control Register (see
record the occurrence of LVR/BOR and WDR respectivel y. The firmware can interrogate these bits to determine the cause of a
reset.

The microcont roller begi ns e xecut ion fro m ROM addr ess 0x00 00 after a LVR, BOR or WDR reset. A lthough t his looks lik e interrupt
vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto
program stack. Attempting to execute either a RET or RETI in the reset handler will cause unpredictable execution results.

The foll owing eve nts take place on reset. More det ails on the various resets are given in the following sections.

1. All registers are reset to their default st ates (all bits cleared, except in Processor Status and Control Register).

2. GPIO and USB pins are set to high-impedance state.

3. The VREG pin is set to high-impe dance state.

4. Interrupts are disabled.

5. USB operation is disabled and must be enabl ed by fi rmware if desired, as explained in Section 14.1 .

6. For a BOR or LVR, the external oscil lator is disab led and Internal Clo ck mode is acti vated, follo wed by a t ime-out period t

for V

to stabilize . A WDR does not change the cloc k mode , and there is no dela y for VCC stabilizati on on a WDR. Note that

CC

Figure 20-1

). Bits 4 and 6 are used to

START

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PRELIMINARY

Figure 9-2

) will be cleared b y a WDR, but it does not take eff ect until suspend mode is

CY7C63742/43

entered.

7. The Program Stack Pointer (PSP) and Data Sta ck Pointer (DSP) reset to address 0x00. (Firmwar e should move the DSP for

USB applications, as explained in Sect ion 6.5.)

8. Program execution begins at address 0x000 0 (af ter the appropriate time-out peri od).

10.1 Low Voltage Reset (LVR)

The CY7C637xx enter s a p artial suspend sta te when VCC is first appl ied t o the chi p . Th e internal osci llat or is started and the Lo w
Voltage Reset (LVR) signal is initially asserted at power-up until V
and an internal co unter starts counting. After t
0x0000. This pro vides time for V

to stabilize before the part executes code.

CC

the partial suspend state ends and program ex ecution begins from a ddress

START

As long as the LVR is enabled, this reset sequence repeats whenever the V
disabled by firmware by setting the Low Voltage Reset Disable bit in the Clock Configuration Regi ster. In addition, the LVR is

has risen above V

CC

pin voltage drops below V

CC

. At that point, the LVR is deasserted

LVR

. The LVR can be

LVR

automatically disabled in suspend m ode to save power. LVR becomes active again (if enabled) once the suspend mode ends.
Whenever LVR is disabled (i.e. by firmware or during suspend mode), a secondary low-voltage monitor (BOR) is active, as

described i n the nex t section. The LVR/BOR bit, bit 4 of the Processor Status and Con trol Register (20-1), is set to “1” to indicate
that one of these resets has occurred.

10.2 Brown Out Reset (BOR)

The Brown Out Reset (BOR) circuit is activ e whenever L VR is disab led. BOR is asserted whene v er the VCC voltage t o the de vi ce
is below an in ternally def ined trip v ol tage of appro xim ately 2.5V. This reset behaves lik e LVR, and in addition re-ena b les the LVR.
That is, once V
before normal operation (from reset ) resumes.

In suspend mode, only the BOR detection is active, giving a reset if V
suspended and code is not executing, this lower voltage is safe for retaining the state of all registers and memory.

drops and trips BOR, the part remains in reset until VCC rises above V

CC

drops below approximately 2.5V. Since the device is

CC

. At that point, the t

LVR

START

dela y occur s

10.3 Watch Dog Reset (WDR)

The Watch Dog Timer Reset (WDR) occurs when the internal Watch Dog timer rolls over. Writing any value to the write-only
Watch Dog Restart Register at address 0x26 will clear the timer. The timer will roll over and WDR will occur if it is not cleared
within t
register contents are set to 010X0001 by the WDR). A Watch Dog Timer Reset lasts for 2–4 ms after which the microcontroller

(10 ms minimum ) of the las t clear. Bit 6 of the Processor Stat us an d Control Regi ster i s set t o recor d this event (the

WATCH

begins execution at ROM address 0x0000. The cloc k mode (internal or external) is not changed by a WDR.

10.1 to

WDR

14.6 ms

(at F

OSC

= 6 MHz)

2–4 ms

At least 10.1 ms

since last write to WDT

WDR goes HIGH
for 2–4 ms

Execution begins at

ROM Ad dress 0x000 0

Figure 10-1. Watch Dog Reset (WDR)

11.0 Suspend Mode

The CY7C637xx parts support a versat ile low-po w er suspend m ode. In su spend mod e, onl y an enabl ed interrupt or a LO W state
on the D–/SDATA pin will wake the part. Two options are available. For lowest po wer, all internal circuits can be disabled, so only
an external event will resume operation. Alternately, a low-power internal wake-up timer can be used to trigger the wake-up
interrupt. This timer is described in Section 11.2, and can be used to periodically poll the system to check for changes, such as
looking for movement in a mouse, while maintaining a low average power.

The CY7C637xx is pl ace d into a low- power sta te by setti ng the Su spend bit of the Pro cessor St atus an d Control Regist er (

20-1

). All logic blocks in the de vice are turned off except the GPIO interrupt logic , the D–/SDAT A pin inpu t receiv er , and ( optionally)

the wake-up timer. The clock oscillators, as well as the free-running and watch dog timers are shut do wn. Only the occurrence of

Figure

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an enabled GPIO interrupt, wake-up interrupt, SPI slave interrupt, or a LOW state on the D–/SDATA pin will wake the part from
suspend (D– LOW indi cates non-idle USB activity). Once one of these resuming conditions occur s, cl ocks will be restarted and
the device returns to full operation after the oscillator is stable and the selected delay period expires. This delay period is
determined by selecti on of int ernal vs. external cl ock, and by t he state of the Ext . Clock Resume Del ay as e xpl ained in Sec tion 9.0.

Note that executing the DI instruction to turn off all interrupts before suspending can cause an unintended wake-up from a

pending

Interrupt Enab le Regis ter and t he USB End Poi nt Inte rrupt Enab le Register (Sectio n 21.0). In that ca se e xec uting the DI instruc tion
is not necessary.

If a resuming condition exists when the suspend bi t is set, the part will still go into suspend and then awake after t he appropriate
delay time. The Run bi t in the Processor Status and Control Register must be set for a part to resume out of suspend.

Once the clock is stable and the dela y time has expired, the microcontroller will execute the instruction following the I/O write that
placed the device into suspend mode before servi cing any interrupt requests.

To achieve the lowest possible current during suspend mode, all I/O should be held at either VCC or ground.

applies to internal port pins that m ay not be bonded in a particular package. Any unused bit s of Ports 0 and 1 should typic ally be
set to pull-up mode, even if the pin s are not present on the package.
21-5

Interrupt Enable (
Typical code for entering suspend is shown below:

interrupt. To avoid this, any interr upts not intended for waking from suspend should be disabled through the Global

In addition, the GPIO

) should be disable d for any pins that are not being used for a wake-up interrupt. This should be done even if the main GPIO

... ; All GPIO set to low-po wer st ate (no floating pins, and bit interrupts disabled unless using f or wake-up)
... ; Enable GPIO and/or wake-up timer interrupts if desired for wake-up
... ; Select clock mode for wake-up (see Section 11.1)
mov a, 09h ; Set suspend and run bits
iowr FFh ; Write to Status and Control Register - Enter suspend, wait for GPIO / wake-up interrupt or USB activit y
nop ; This executes before any ISR
... ; Remaining code for exiting suspend routine

Figure 21-1

) is off.

bit

CY7C63742/43

Note that this also

interrupts (

Figure 21-4

and

Figure

11.1 Clocking Mode on Wake-up from Suspend

When exiting suspend on a wake-up event, the device can be configured to run in either Internal or External Clock mode. The
mode is selected by the state of the External Oscillator Enable bit in the Clock Configuration Register (
Internal Clock saves the exter nal oscillator start-up time and keeps that oscillator off for additional power savings. The ext ernal
oscillator mode can be activated when desired, similar to operation at power-up.

The sequence of events for these modes is as follows:

Wake in Internal Clock Mode:

1. Before entering suspend, clear bit 0 of the Clock Configuration Regi ster. Thi s selects Internal cloc k mod e aft er suspend.

2. Enter suspend mode by setting the suspend bit of the Processor Status and Control Register.

3. After a wake- up event, the internal clock starts immediately (within 2 µs).

4. A time-out period of 8 µs passes, and then fi rmw are execution begins.

5. At some later point , to activ ate Ext ernal Clock mode, set bit 0 of the Clock Con figurati on Register . Thi s halts the internal clocks

while the ex ternal clock becomes stable. After an additional time-out (128 µs or 4 ms, see Section 9.0 ), firmware execution
resumes.

Wake in External Clock Mode:

1. Before entering suspend, the external clock must be selected by set ting bit 0 of the Clock Confi guration Register. Make sure

this bit i s still set when suspend mode is entered. This selects External clock mode after suspend.

2. Enter suspend mode by setting the suspend bit of the Processor Status and Control Register.

3. After a wake- up event, the external oscil lator is started. The clock is monitored for stab il ity (this takes appr oximately 50–100

µ

s with a ceramic resonator).

4. After an additional time-out period (128 µs or 4 ms, see Section 9.0), firmware execution resumes.

Figur e 9- 2

). Using the

11.2 Wake-up Timer

The wake- up timer runs whenev er the wake-up i nterrupt is enabled, and is turned off whenev er that interrupt is di sabled. Opera tion
is independent of whether the de vice is in suspend mode or if t he global inter rupt bit is enab led. Only th e wake-up i nterrupt enable
controls the w ake-up timer.

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Once this timer is activated, it wi ll give interrupts after its tim e-out period (see below). These interrupts conti nue periodically until
the interrupt is disab led. Whenev er the interrupt is disab led, the wake-up tim er is reset, so that a subsequent enab le always results
in a full wake-up time .

The wake- up timer can be adjust ed by the user through the W ake-up Ti mer Adjust bits i n the Clock Conf igurat ion Register (

9-2

). These bits clear on reset. In addition to allowing the user to select a range for the wake-up time, a firmware algorithm can

Figure

be used to tune out i nitial proc ess and operat ing condition v ariati ons in this wak e-up tim e. This can be done by timi ng the wake-up
interrupt time with the accurate 1.024-ms timer interrupt, and adjusting the Timer Adjust bits accordingly to approximate the
desired wake-up time.

Table 11-1. Wake-up Timer Adjust Settings

Adjust Bits [2:0]

(Bits [6:4] of Register 0xF8) Wake-up Time

000 (reset state ) 1 * t

001 2 * t
010 4 * t
011 8 * t
100 16 * t
101 32 * t
110 64 * t
111 128 * t

WAKE
WAKE
WAKE
WAKE

WAKE
WAKE
WAKE

WAKE

12.0 General Purpose I/O Ports

Ports 0 and 1 provide up to 16 versatile GPIO pins that can be read or written (the number of pins depends on package t ype).
Each pin can be configured as high-impedance inputs, inputs with internal pull-ups, open drain outputs, or traditional CMOS
outputs with selectable drive strengths.
independentl y of any other pin. Port 0 is an 8-bit port; Port 1 contains e it her 2 bits, P1.1–P1.0 in the CY7C63722/23, or a ll 8-bi ts,
P1.7 - P1.0 i n the CY7C6374 2/43 parts . Each bi t can al so be selec ted as an inter rupt sour ce f or the mic rocontr oll er , as e xpl ained
in Section 21.3.6.

GPIO
Mode

SPI Bypass (P0.5–P0.7 only)

(=1 if SPI inactive, or for non-SPI pins)

Internal
Data Bus

Data
Out
Register

Port Write

Figure 12-1

2

(Data Reg must be 1
for SPI outputs)

shows a diagram of a GPIO port pin. Each I/O pin can be configured

V

CC

Q1

Control

14 k

Q3

Ω

GPIO

Pin

Q2

Threshold Select

Port Read

Interrupt
Polarity

Interrupt
Enable

Interrupt

Logic

To Interrupt
Controller

Figure 12-1. Block Dia gram of GPIO Port (one pin shown)

18

To Capture Timers (P0.0, P0.1)

and SPI (P0.4–P0.7))

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The driving state of each pin is determined by the value written to the pin’s Data Register and by two Mode bits for each pin.

Table 12-1

cleared, so the pins are all in a high-impedance stat e. The available GPIO modes are:
Mode 00 High-impedance mode.

Mode 01 Medium Drive CMOS Mode: 8 mA sink cur rent / 2 mA source current.
Mode 10 Low Drive / Resistive Mode: 2 mA sink current / 14 kΩ pull-up resistor.
Mode 11 High Drive CMOS Mode. 50 mA sink current / 2 mA source current.

Note that open drain m ode can be achieved by fixing the Data and Mode1 Regist ers low, and switching the Mo de0 register .
Input thresholds are CMOS (centered around V

minimize noise sensitivity. In suspend mode, if a pin is used for a wake-up interrupt using an external R-C circuit, CMOS mode
is prefe rred for lowest power.

Table 12-1. Ports 0 and 1 Output Control Truth Table

Data Register Mode1 Mode0 Output Drive Strength Input Threshold

lists the configuration states based on these bits. The GPIO ports default on reset to all Data and Mode Registers

/2), or TTL as shown in the table. Both input modes include hysteresis to

CC

0 0 0 Hi-Z CMOS
0 0 1 0 - Medium Sink CMOS
0 1 0 0 - Low Sink CMOS
0 1 1 0 - High (50 mA) Sink CMOS
1 0 0 Hi-Z TTL
1 0 1 1 Strong CMOS
1 1 0 1 R esistive CMOS
1 1 1 1 Strong CMOS

CY7C63742/43

Note that reading the GPIO port returns a byte based on the actual voltage of each pin, and does not affect the port’s Data or
Mode Registers.

The Port 0 Data Register is shown in
bits for the two GPIO ports are given in

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/W

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/W

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

Note:

1. When performing a read of the Port 0 or Port 1 Data registers, above, only the status of the GPIO pins will be read. The registers content will NOT be read.

7 6 5 4 3 2 1 0

W W W W W W W W

P0.7 Mode0 P0.6 Mode0 P0.5 Mode0 P0.4 Mode0 P0.3 Mode0 P0.2 Mode0 P0.1 Mode0 P0.0 Mode0

Figure 12-2

Figure 12-4

Pins 7:2 only in CY7C63742/43 Pins 1:0 in all parts

Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A)

, and the Port 1 Data Register is shown in

through

Figure 12-2. Port 0 Data (Address 0x00)

Figure 12-3. Port 1 Data (Address 0x01)

Figure 12-7

.

[1]

[1]

Figure 12-3

. The Mode0 and Mo de1

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7 6 5 4 3 2 1 0

W W W W W W W W

P0.7 Mode1 P0.6 Mode1 P0.5 Mode1 P0.4 Mode1 P0.3 Mode1 P0.2 Mode1 P0.1 Mode1 P0.0 Mode1

Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B)

7 6 5 4 3 2 1 0

W W W W W W W W

P1.7 Mode0 P1.6 Mode0 P1.5 Mode0 P1.4 Mode0 P1.3 Mode0 P1.2 Mode0 P1.1 Mode0 P1.0 Mode0

Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C)

7 6 5 4 3 2 1 0

W W W W W W W W

P1.7 Mode1 P1.6 Mode1 P1.5 Mode1 P1.4 Mode1 P1.3 Mode1 P1.2 Mode1 P1.1 Mode1 P1.0 Mode1

Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D)

Refer to Sect ion 21.3.6 for detai ls on using the GPIO as interrupt sources.

CY7C63742/43

12.1 Auxiliary Input Port

Port 2 serves as an auxili ary input port. The state of the D+ and D– pins can be read from this port, as shown in
addition, the VREG and XTALIN pins can serve as general purpose input s in certain modes. For the VREG pin, refer to Section

15.0. For t he XTALIN pin, refer to Section 9.1 . In these m odes, t he pin states can be read from Port 2.
The Port 2 inputs all have TTL input thresholds.

Figure 12-8

. In

7 6 5 4 3 2 1 0

- - R R - - R R

Reserved Reserved D+ (SCLK)

State

Figure 12-8. Port 2 Data Register (Address 0x02)

D– (SDATA )

State

Reserved Reserved P2.1

(Internal

Clock Mode

only)

P2.0

VREG Pin

State

13.0 USB Ser ia l Interface Engine (S I E)

The SIE allows the micr ocontroller to communicate with the USB host. The SIE simplifies the inter face between t he microcontroller
and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller:

• Bit stuffing/unstuffing

• Checksum gener ation/checking

• ACK/NAK

• Token type identification

• Address checking

Firmware is required to handl e the rest of the USB interface wi th the following tasks:

• Coordinate enumeration by responding to set-up packets

• Fill and empty the FIFOs

• Suspend/Resume coordination

• Verify and select Data toggl e values

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CY7C63742/43

13.1 USB Enumeration

A typical USB enumeration sequence is shown below. In this description, ‘Firmware’ refers to embedded firmware in the
CY7C637xx controller.

1. The host computer sends a SETUP packet followed by a D ATA packet to USB address 0 requesting the Devi ce descriptor.

2. Firmware decodes the request and retrieves its Device descriptor from the progr am memory tables.

3. The host comput er p erf orms a cont rol r ead sequence a nd Fi rmware r espon ds b y sendi ng the De vice desc riptor o v er the USB

bus, via t he on-chip FIFO.

4. After receivi ng the descriptor, the host sends a SETUP packet followed by a DATA packet to addres s 0 assigning a new USB

address to the device.

5. Firmware stores the new address in its USB Device Address Register after the no-data control sequence completes.

6. The host sends a request for the Device descriptor using the new USB addr ess.

7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.

8. The host performs a cont rol read sequence and Firmware responds by sending its Device descriptor over the USB bus.

9. The host generates control reads f rom the device to request the Configuration and Report descriptors.

10.Once the device receives a Set Configuration request, its functions may now be used.

11.Firmware should take appropriate action for Endpoint 1 and/or 2 transactions, which may occur from this point.

13.2 USB Port Status and Contr o l

USB status and control is regulated by the USB Status and Control Register as shown in
written to zero. All bits in the register are cleared during reset.

Figure 13-1

. All reserved bits must be

7 6 5 4 3 2 1 0

R/W R/W R/W - R/W R/W R/W R/W

PS/2 Pull-up

Enable

The Control Bits (bits 2:0) allow firmware to directly drive the D+ and D– pins, as shown in
controlled edge rates in these modes for low EMI. For forcing these pins in USB mode (e.g. Force K for resume), Control Bit 2
should be 0. Setting Control Bit 2 HIGH puts both pins in an open-drain mode, preferred for applications such as PS/2 or LED
driving.

The Bus Activity bi t (bit 3) is a “sticky” bit that indicates if any no n-idle USB ev ent has oc curred on the USB b us. The user firmwar e
should check and clear this bit periodically to detect any loss of bus activity. Writing a “0” to the Bus Activity bit clears it while
writing a “1” preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.
The 1.024-ms timer interrupt service routine is normall y used to check and clear the Bus Activity bit.

Bits 4 is reserved and must be written as a 0.
The USB-PS/2 Interrupt Mode (bit 5) selects the definition of the USB Reset / PS/2 Activity Interrupt. The default cleared state

puts the interrupt into USB mode. Setting this bit HIGH switches the interrupt definition to PS/2 mode. Details of the mode
definitions are given in Section 21.3.1.

VREG Enable (bit 6) enables the 3.3V output voltage on the VREG pin when set to 1. This output is provided to sour ce current
for a 1.5-kΩ pull-up resistor connected to the D– pin. On reset, this bit is cleared, so the VREG pin is in hi gh-impedance state.

PS/2 Pullup Enable (bit 7) can be set to enabl e the internal PS/2 pull-up resistors on the SDATA and SCLK pins. Normally the
output high level on these pins is V
Enable bit is set, or if the Device Addr ess is enabled (bit 7 of the USB Device Address Register,

VREG

Enable

USB Reset-

PS/2 Activity

Interrupt

Mode

Figure 13-1. USB Status and Control Register (Address 0x1F)

, but not e that the output will be clamped to approximately 1 Volt above VREG if the VREG

CC

Reserved USB

Bus Activity

Control

Bit 2

Control

Table 13-1

Figure 14-1

Bit 1

. Outputs are driven with

).

Control

Bit 0

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Table 13-1. Control Modes to Force D+/D– Outputs

Contro l Bits [2:0] Control action Application

000 Not forcing (SIE controls driver) Any Mode
001 Force K (D+ HIGH, D– LOW) USB Mode
010 Force J (D+ LO W, D– HIGH)
011 Force SE0 (D– LOW, D+ LOW)
100 Force D– LOW, D+ LOW PS/2 Mode
101 Force D – LOW, D+ HiZ
110 Force D– HiZ, D+ LOW
111 Force D– HiZ, D+ HiZ

Note:

2. For PS/2 operation, the [2:0] = 111b mode must be set initially (one time only) before using the other PS/2 force modes.

CY7C63742/43

[2]

14.0 USB Device

The CY7C637xx supp orts one USB De vice Address with thr ee endpoints: EP0, EP1, and EP2. Control Endpoint 0 (EP0) all ows
the USB host to recognize, set-up, and control the device. In particular, EP0 is used to receive and transmit control (including
set-up) packets.

14.1 USB Address Register

The USB Device Address Register contains a 7-bit USB address and one bit to enable USB communication. This register is
cleared during a reset, setting the USB device address to zero and marking this address as disabled.
format of the USB Address Regi ster.

Figure 14-1

shows the

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/W

Device

Address

Enable

Bit 7 (Device Address Enable) in the USB Device Address Register must be set by firmware before the serial interface engine
(SIE) will respond to USB traffic at this address. The Device Addr ess in bits [6:0] must be set by firmware during the USB enu­meration process to the non-zero address assigned by the USB host. This register is cleared by both hardware resets and the
USB bus reset.

Device

Address

Bit 6

Device

Address

Bit 5

Figure 14-1. USB Device Address Register (Address 0x10)

Device

Address

Bit 4

Device

Address

Bit 3

Device

Address

Bit 2

Device

Address

Bit 1

Device

Address

Bit 0

14.2 USB Control Endpoint

All USB devices are required to have an endpoint number 0 (EP0) that is used to initialize and control the USB device. EP0
provides acces s to t he devi ce confi gurat ion i nfo rmation and al lows generic USB st atus an d con trol accesse s. EP0 is bi direc tional
as the device can both receive and transmit data. EP0 uses an 8-byte FI FO at SRAM locations 0xF8–0xFF, as shown in Secti on

8.2.
The endpoint mode registers are cleared during reset. The EP0 endpoint mode register uses the format shown in

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/ W

Endpoint 0

SETUP

Received

Endpoint 0

IN

Received

Endpoint 0

OUT

Received

Figure 14-2. USB EP0 Mode Register (Address 0x12)

ACK Mode

Bit 3

Mode

Bit 2

Mode

Bit 1

Figure 14-2

Mode

Bit 0

.

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Bits[7:5] i n the endpoint 0 mode registers are “sticky” status bits that are set by the SIE to report the type of token that was most
recently recei ved by the corre sponding devi ce address. The stic ky bits must be clear ed by firmware as part of the USB processing.

The ACK bit (bit 4) is set whene v er the SIE engages in a transa ction to the register’s endpoint that co mpletes wi th an A CK p ack et .
The SETUP PID status (b it 7) i s forced HIGH from the start of the data pack et phase of the SETUP transacti on, until the start of

the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval, and subsequently until the
CPU first does a IORD to this endpoin t 0 mode regi ster.

Bits[6:0] of the endpoint 0 mode register are loc ked from CPU write operations whenever t he SIE has updated one of these bits,
which the SIE does only at the end of a packet transaction (SETUP... Data... ACK, or OUT... Data... ACK, or IN... Data... ACK).
The CPU can unlock these bits by doing a subsequent read of this register.

Because of these hardware locking features, firmware must perform an IORD after an IOW R to an endpoint 0 register to verify
that the contents have changed as desired, and that t he SIE has not updated these values.

While the SETUP bit is set, the CPU cannot write to the EP0 FIFO. This prevents firmware from overwri ting an incoming SETUP
transaction before firmware has a chance to read the SETUP data.

The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in
Additional information on the mode bits can be found in

Ta bl e 22 -2

and

Ta bl e 22 -3

.

CY7C63742/43

Table 22-1

14.3 USB No n- C o nt rol E nd poi nt s ( 2 )

The format of the non-control endpoint mode registers is shown in
0xF0–0xF7, while EP2 uses an 8-b yte FIFO at SRAM locations 0xE8–0xEF, as shown in Section 8.2.

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W

STALL Reserved Reserved ACK Mode

Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14, 0x16 )

Figure 14-3

Bit 3

. EP1 uses an 8-byte FIFO at SRAM locations

Mode

Bit 2

Mode

Bit 1

Mode

Bit 0

.

The Mode bits (bits [3:0]) of the Endpoint Mode Registers control how the endpoint responds to USB bus traffic. The mode bit
encoding is shown in

The ACK bit (bit 4) is set whene v er the SIE engages in a transa ction to the register’s endpoint that co mpletes wi th an A CK p ack et .
If STALL (bit 7) is set, the SIE will stall an O UT packet if the mode bits are set to ACK-IN, and the SIE will stall an IN pac ket if the

mode bits are set to ACK-OUT. For all other modes the STALL bit must be a LOW.
Bits 5 and 6 are reserved and must be written to zero during r egister writes.

Table 22-1

.

14.4 USB Endpoint Counter Registers

There are three Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byt e count i nfor mation f or USB transa ction s, as wel l as bi ts f or data packe t stat us. The format of thes e re gisters i s shown

Figure 14-4

in

R/W R/W R/W R/W R/W R/ W

Data 0/1

Toggle

The counter bits (bits [3:0]) indicate the number of data bytes in a transaction: For IN transactions, firmware loads the count with
the number of bytes to be transm itted to the host from the endpoint FIFO. Valid values are 0 to 8 inclusive. For OUT or SETUP
transactions, t he count i s updated by hardware to the number of dat a bytes received, plus 2 for the CRC bytes. Valid values are
2 to 10 inclusive.

Data V alid bi t 6 is used f or OUT and SETUP toke ns only. Data is lo aded into the FIFOs during the transact ion, and t hen the Data
Valid bit will be set if a proper CRC is received. If the CRC is not correct, the endpoint interrupt will occur, but Data Valid will b e
cleared to a zero.

Data 0/1 Toggle bit 7 selects the DATA pac k et’s toggle state: 0 fo r D ATA0, 1 for DAT A1. F or I N trans actio ns , fi rmware must s et thi s
bit to the desired st ate. For OUT or SETUP transactions, the hardw are sets this bit to the state of the re ceived Data Toggle bit.

.

7 6 5 4 3 2 1 0

Data Valid Reserved Reserved Byte Count

Bit 3

Figure 14-4. USB Device Counter Regi sters (Addresses 0x11h, 0x13h, 0x15)

Byte Count

Bit 2

Byte Count

Bit 1

Byte Count

Bit 0

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Whenever the count updates from a SETUP or OUT transaction, the count register locks and cannot be written by the CPU.
Reading the regis ter unl ocks i t. T his pr ev e nts f irmware from overwriting a status u pdate o n inc oming SETUP or OUT tran sact ions
before firmware has a chance to read the data.

CY7C63742/43

15.0 USB Regulator Output

The VREG pin provides a regulated output for connecting the pull-up resistor required for USB operation. For USB, a 1.5 k
resistor is connected between the D– pin and the VREG pin, to indicate low-speed USB operation. Since the VREG output has
an internal series resistance of approximately 200Ω, the external pull-up resistor required is R

The regulator output is placed in a high-im pedance st ate at reset , and must be enab led by firmware by settin g the VREG Enable
bit in the USB Status and Control Register (
the USB pull-up resi stor can be left in place duri ng PS/2 operation without loading the PS/2 line. In this mode, VREG
used as an input and its state can be read at port P2.0. Refer to
threshold.

Note that enabling the device for USB (by setting the Device Address Enable bit,
even if the VREG Enabl e bit is cleared t o 0. This insures proper USB signaling in the case wher e the VREG pin is used as an
input, and an e xt ernal r egulat or is prov ided for the USB pull-up re sisto r . This als o limit s t he s wi ng on t he DM and DP pins to about
1V above the inte rnal regulator volt age, so the Devic e Address Enab le bit normally shoul d only be set for USB operati ng modes .

The regulat or output is desi gned to pr ovide cu rrent f or the USB pull- up resist or , and c an only so urce curr ent up to I
the output v olta ge at the VREG pi n is eff ect iv ely di sco nnected when the CY7C6 37xx de vi ce tra nsmits USB f rom the i nternal SIE.
This means that the VREG pi n does not provide a stable voltage during transmits, although this does not affect USB signaling.

Figure 13-1

). This simplifies the design of a combination PS/2 - USB devi ce, since

Figure 12-8

for the Port 2 data register. This input has a TTL

Figure 14-1

(see Section 24.0 ).

PU

pin can be

) activates the internal regulator,

. In addition,

REG

16.0 PS/2 Operation

Ω

The CY7C637xx parts are optimized for combination USB or PS/2 devices, through the following features:

1. USB D+ and D– lines can also be used for PS/2 SCLK and SDATA pins, respectively. With USB disabled, these lines can be

placed in a high impedance state that will pull up to V
Address Register,

2. An interrupt is pro vided to indicate a long LOW state on the SDATA pin. This el iminates the need to poll this pi n to check for

PS/2 activity. R e fer to Se c ti on 2 1. 3 .1 .

3. Internal PS/2 pull-up resistors can be enabled on t he SCLK and SDATA lines, so no GPIO pins are required f or th is task (bit

7, USB Status and Control Register,

4. The controlled slew rate outputs from these pins apply to both USB and PS/2 modes to minimize EM I.

5. The state of the SCLK and SDATA pins can be read, and can be individ ually driven low in an open drain mode. The pins are

read at bits [5:4] of Port 2, and are driven with the Control Bits [2:0] of the USB Status and Control Register.

6. The VREG pin can be placed into a high-i mpedance sta te, so tha t a USB pull-up resist or on the D–/SD AT A pi n will not inter fere

with PS/2 operation (bit 6, USB Status and Control Register).

The PS/2 on-chip support circuitry is illustrated in

Figure 14-1

).

Figure 13-1

Figure 16-1

. (Disab le USB by clearing the Address Enable bit of the USB Device

CC

).

.

24

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Port 2.0

VREG Enable

PS/2 Pull-up
Enable

Port 2.5

3.3V

Regulator

USB - PS/2
Driver

5 k

CY7C63742/43

Ω

200

V

CC

Ω

5 k

Ω

VREG

Ω

1.3 k

D+/SCLK

D–/SDATA

Port 2.4

Figure 16-1. Diagram of USB - PS/2 System Connections

On-chip Off-chip

17.0 Serial Periph er al Interface (SPI )

SPI is a 4-wire, full-duplex serial communication interface between a master device and one or more slave devices. The
CY7C637xx SPI circuit supports byte serial transfers in either Master or Slave modes. The block diagram of the SPI circuit is
shown in
CY7C637xx can b e configured as ei ther an SPI Master or Slave. The external interface cons ists of Master-Out/Slave-In (MOSI),
Master-In/Slave-Out (MI SO), Serial Clock (SCK), and Sla ve Select (SS
the transmit buffer, while reads from this register read the receive buffer contents.

SPI modes are activ ated by setting the appropriate bits in the SPI Control Register, as described below.

Figure 17-1

. The block contains buffers for both transmit and receive data for maximum flexibility and throughput. The

). Writes to the SPI Data Regi ster (see

Figure 17-2

) load

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Data Bus

TX Buffer

8 bit shift register

RX Buffer

Data Bus

Write

Read

Figure 17-1. SPI Block Diagram

Master
/ Slave
Control

4

Internal SCK

CY7C63742/43

MOSI

MISO
SCK

SS

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/ W

Data I/O [7] Data I/O [6] Data I/O [5] Data I/O [4] Data I/O [3] Data I/O [2] Data I/O [1] Data I/O [0]

Figure 17-2. SPI Data Register (Address 0x60)

17.1 Operation as an SPI Master

Only an SPI Master can initiat e a b yte/d ata transfer. This is done by t he Mast er writing to the SPI Data regi ster. The Master shifts
out 8 bits of dat a (MSB first) al ong with the seri al cloc k SCK for the Sl av e. The Maste r’s outgoing byte i s replaced wit h an incoming
one from a Slave device. When the last bit is received, the shift register contents are transferred to the Receive Buffer and an
interrupt is generated. The receive data must be read from the SPI Data Register before the next byte of data is transferred to
the receiv e buffer, or the data will be lost.

When operating as a M aster , an active LO W Sla ve Select (SS
Select is g enerated under firmware control, and is not part of the SPI internal hardware. Any available GPIO can be used for the
Master’s Slave Sele c t ou tput.

When the Mas ter writ es to th e SPI Da ta Regist er , the dat a is loaded i nto t he Transmit buff er . If the s hift r egist er is not b usy shif ting
a previous byte, the TX buffer contents will be automatically transferred into the shift register and shifting will begin. If the shift
register is busy, the new byte will be loaded into the shi ft register only after the active byte has finished and is transferred to the
Receive Buf fe r . The ne w byt e will then be shift ed out. The Transmit Buffer Full ( TBF) bit wi ll be s et HIGH unt il t he tr ansmit b uffer’s
data-byte is transferred to the shift register. Writing to the transmit buffer while the TBF bit is HIGH will overwrite the old byte in
the Transmit Buffer.

The byte shifting and SCK generation are handled by the hardware (based on firmware selection of the clock source). Data is
shifted out on the MOSI pin (P0.5) and the serial clock is output on the SCK pin (P0.7). Data is received from the slave on the
MISO pin (P0.6). The outp ut pins must be set t o the desi re d driv e stren gth, and the GPI O data reg ister must be s et t o 1 to enab le
a bypass mode for these pins. The MISO pin must be configured in the desired GPIO input mode. See Section 12. 0 for GPIO
configura tion details.

) must be ge ner ated to enab l e a Sla ve f or a b yte trans fe r. This Slave

17.2 Master SCK Selection

The Master’s SCK is programmable to one of four clock settings, as shown in
Clock Select Bits of the SPI control register. The hardware provides 8 output clocks on t he SCK pin (P0.7) for each byte transfer.
Clock phase and polarity are selected by the CPHA and CPOL contr ol bits (see

The master SCK duty cycle is nominally 33% in the fastest (2 Mb/s) mode, and 50% in all other modes.

26

Figure 17-1

Figures 17-1

. The frequency is selected with the

17-4

and

).

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USB CY7C63722/23

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CY7C63742/43

17.3 Operation as an SPI Slave

In slave mode, the chip receives SCK from an external master on pin P0.7. Data from the master is shifted in on the MOSI pin
(P0.5), while data is being shifted out of the slave on the MISO pin (P0.6). In addition, the active LOW Slave Select must be
asserted to enable the sla ve for trans mit. The Slav e Select pin is P0.4. These pins must be confi gured in appropriate GPIO modes,
with the GPIO data register set to 1 to enable bypass mode selected for the MISO pin.

In Slave mode, writes to the SPI Data Register load the Transmit buffer. If the Slave Select is asser ted (SS
register is not busy shifting a previous byte, the TX buffer contents will be automatically transferred into the shift register. If the
shift register is busy, the new byte will be loaded int o the shift register only after th e active byte has finished and is transf erred to
the Receive Buffer. The new byte is then ready to be shifted out (shifting waits for SCK from the Master). If the Slave Select is
not activ e when the t ransmit buff er is l oaded, dat a is not tr ansf erred to th e shift r egister until Sla ve Selec t is asse rted. The Transmit
Buffer Full (TBF) bit wil l be set HIGH until the transmit buffer’s data-byte is tr ansferred to the shift regis ter. Writing to the tra nsm it
buffer while the TBF bit is HIGH will ov erwrite the old byte in the Transmit Buffer.

If the Sl ave Select i s deasserted b efore a by te tra nsfer is compl ete, t he trans fer is aborted and no inte rrupt is gene rate d. Whenever
Slave Select is asserted, the transmit buffer is automatically reloaded into the shift register.

Clock phase and polarity m ust be select ed to match the SPI m aster, using the CPHA and CPO L control bits (see

Figure 17-4

The SPI slave logic continues to operate in suspend, so if the SPI interrupt is enabled, the device can go into suspend during a
SPI slave transaction, and it will wake up at the interrupt that signals the end of the byte transfer.

).

LOW) and the shift

Table 17-1

and

17.4 SPI Status and Control

The SPI contro l register is show n in
SPI modes.

Figure 17-3

. The timing diagram i n

Figure 17-4

shows t he clock and data st ates f or the v arious

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/ W

TCMP TBF M ode[1] Mode[0] CPOL CPHA SCK Select [1] SCK Select [0]

Figure 17-3. SPI Control Regist er (Address 0x61)

Table 17-1. SPI Control Register Definitions

Bit(s) Definition Function

1:0 SCK Select Master mode SCK frequency selection (no effect in Slave Mode):

00 2 Mbit/s
01 1 Mbit/s
10 0.5 Mbit/s

11 0.0625 M bit/sec
2 CPHA SPI Clock Phase (see
3 CPOL SPI Clock Polarity (see

5:4 Comm

Modes

6 TBF Transmit Buffer Full. TBF=1 indicates data in the transmit buf fer has not transferred to the shift

7 TCMP Transfer Complete. TCMP is set to 1 by the hardware when 8 bit transfer is complete. This bit is

00 All Comm unications functions disabled (default)

01 SPI Master Mode

10 SPI Slave Mode

11 reserved

register.

only cleared by firmwa re. The SPI interrupt is asserted at the same time TCMP is set to 1.

Figure 17-4

Figure 17-4

)

): 0 SCK idles LOW, 1 SCK i dles HIGH

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SCK (CPOL=0)
SCK (CPOL=1)

SS

CPHA=0:

MOSI / MISO
Data Capture Strobe

Interrupt Issued

CPHA=1:
MOSI / MISO

Data Capture Strobe
Interrupt Issued

PRELIMINARY

x

MSB LSB

MSB LSB

Figure 17-4. SPI Data Timing

CY7C63742/43

x

17.5 SPI Interrupt

For SPI, an interrupt request is ge nerated after a b yte is receiv ed or transmit ted. See Section 21.3.4 f or details on the SPI int errupt.

17.6 SPI modes for GPIO pins

The GPIO pins used for SPI outputs (P0.5–P0.7) contain a bypass mode, as shown in the GPIO block diagram (
Whenever the SPI block is inactive (Mode[5:4] = 00), the bypass value is 1, which enables normal GPIO operation. When SPI
master or sla v e modes are act iv ate d, the appr opriat e bypass si gna ls are driv en b y the hard ware f o r output s, and ar e held at 1 f or

Note that the corresponding data bits in the Port 0 Data Regist er must be set to 1 for each pin being used f or an

inputs.

SPI output.

firmware to the desir ed drive strength mode.
For GPIO pins that are not used for SPI outputs, the SPI bypass value in

Table 17-2. SPI Pin Assignments

Master Out, Sla ve In (MOSI) P0.5 Data output for master, data input for slave.
Master In, Sla ve Out (MISO) P0.6 Data input for master, dat a output for slave.

In addition, the GPIO modes are not affected by operation of the SPI block, so each pin must be programmed by

Figure 12-1

SPI Function GPIO Pin Comment

Slave S e l e ct (SS

SCK P0.7 SPI Clock: Output f or master, input for slave.

) P0.4 For Master Mode, Firmware se ts SS, may use any GPIO pin.

For Slave M ode, SS

is always 1, for normal GPIO operation.

is an active LOW input.

Figure 12-1

).

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PRELIMINARY

CY7C63742/43

18.0 12-bit Free-running Timer

The 12-bit timer operates wi th a 1-µs tick, provides two i n terrupts (128 µs and 1.024 ms) and allows the firmware to directly time
ev ents that are up to 4 ms in duration. The lower 8 bit s of the timer ca n be read directly by the firmware. Reading the l ower 8 bits
latches t he upper 4 bits into a temporary register. When the firmware reads the upper 4 bits of the timer , it is a ctually reading the
count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even when the two
reads are separated in time.

7 6 5 4 3 2 1 0

R R R R R R R R

Timer

Bit 7

7 6 5 4 3 2 1 0

Reserved Reserved Reser ved Reserved Timer

Timer

Bit 6

Timer

Bit 5

Figure 18-1. Timer LSB Register (Address 0x24)

Figure 18-2. Timer MS B Register (Address 0x25)

Timer

Bit 4

Timer

Bit 3

R R R R

Bit 11

Timer

Bit 2

Timer

Bit 10

Timer

Bit 1

Timer

Bit 9

1.024-ms interrupt

µ

128-

s interrupt

Timer

Bit 0

Timer

Bit 8

10 9 7856 432

1 011

L1 L0L2L3

D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

8

Figure 18-3. Ti mer Block Diagram

1 MHz clock

To Timer R eg isters

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PRELIMINARY

CY7C63742/43

19.0 Timer Capture Registers

Four 8-bit timer capture registers provide both rising and falling edge event timing capture on two pins. Capture Timer A is
connected to Pin 0.0, and Capture Timer B is connected to Pin 0.1. These can be used to mark the time at which GPIO events
occur . Eac h timer will capt ur e 8 bits of the free- running t imer i nto a dat a regi ster. A prescaler allows se lecti on of t he captu re t i mer
tick size. Interrupts can be individually enabled for the four capture registers. A block diagram is shown in

Each of the four capture registers can be individually enabled to provide interrupts.
The four capture data registers are read-only, and are shown in

Figure 19-2

through

Figure 19-5

.

Free-runni ng Timer

11 10 9 8 7 4 3 2 1 0

6 5

Prescaler

First Edge Hold

Bit 7, Reg 0x44

Rising

Mux

8-bit Capture Regist ers

Timer A Rising Edge Time

Edge

GPIO
P0.0

Detect
Falling

Timer A Falling Edge Time

Edge
Detect

Figure 19-1

1 MHz

Clock

.

Rising

Timer B Rising Edge Time

Edge

GPIO
P0.1

Detect
Falling

Timer B Falling Edge Time

Edge
Detect

Capture A Rising Int Enable

Bit 0, Reg 0x44

Capture A Falling Int Enable

Bit 1, Reg 0x44

Capture B Rising Int Enable

Bit 2, Reg 0x44

Capture B Falling Int Enable

Bit 3, Reg 0x44

Capture Timer A Interrupt Request

Capture Timer B Interrupt Request

Figure 19-1. Capture Ti mers Block Diagram

Three prescal er bit s allow the captur e timer c lock r ate to b e selected among 5 c hoices, as sho wn in
Status Regis ter (

Figure 19-6

) contains the pres cale s etti ngs and the inte rrupt e nab les f or t he 4 po ssi ble e ve nts . Set tin g an enab le

T ab le 19 -1

below . The Capture

bit allows for an interrupt from the respective timer event. No te that both Capture A ev ents share a comm on interrupt request , as
do the two Capture B event s. I n addition to the event enables, the main Ca ptur e Interrupt Enables in the Global Inte rrupt Enable
register (Section 21.0) must be set to activate a capture interrupt.

The Capture Status Register (

Figure 19-7

) records the occurrence of any rising or falling edges on the capture GPIO pins. Bits

in this register are cleared by reading the corresponding data register .

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By default, a capture timer register holds the time of the most recent edge for that register (i.e. if multiple edges have occurred
before reading the capture timer, the time for the last one will be read). Setting the global First Edge Hold (bit 7,
modifies th is so that the first occurrence of an edge is held in the capture regi ster until the data is read. In this case, subsequent
edges are ignored unt il the capture register i s read. The First Edge Hold function appl ies globally to all four capture timers.

7 6 5 4 3 2 1 0

R R R R R R R R

Capture A

Rising

Bit 7

7 6 5 4 3 2 1 0

R R R R R R R R

Capture A

Falling

Bit 7

7 6 5 4 3 2 1 0

R R R R R R R R

Capture B

Rising

Bit 7

Capture A

Rising

Bit 6

Capture A

Falling

Bit 6

Capture B

Rising

Bit 6

Capture A

Rising

Bit 5

Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40)

Capture A

Falling

Bit 5

Figure 19-3. Capture Timer A-Falling, Data Regist er (Address 0x41)

Capture B

Rising

Bit 5

Capture A

Rising

Bit 4

Capture A

Falling

Bit 4

Capture B

Rising

Bit 4

Capture A

Rising

Bit 3

Capture A

Falling

Bit 3

Capture B

Rising

Bit 3

Capture A

Rising

Bit 2

Capture A

Falling

Bit 2

Capture B

Rising

Bit 2

CY7C63742/43

Figure 19-6

Capture A

Rising

Bit 1

Capture A

Falling

Bit 1

Capture B

Rising

Bit 1

Capture A

Rising

Bit 0

Capture A

Falling

Bit 0

Capture B

Rising

Bit 0

)

Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42)

7 6 5 4 3 2 1 0

R R R R R R R R

Capture B

Falling

Bit 7

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/W

First Edge

Hold

7 6 5 4 3 2 1 0

- - - - R R R R

Reserved Reserved Reserved Reserved Capture B

Capture B

Falling

Bit 6

Prescale

Bit 2

Capture B

Falling

Bit 5

Figure 19-5. Capture Timer B-Falling, Data Regist er (Address 0x43)

Prescale

Bit 1

Figure 19-6. Capture Timers Confi guration Register (Address 0x44)

Capture B

Falling

Bit 4

Prescale

Bit 0

Capture B

Falling

Bit 3

Capture B

Falling

Int Enable

Falling

Event

Capture B

Falling

Bit 2

Capture B

Rising

Int Enable

Capture B

Rising

Event

Capture B

Falling

Bit 1

Capture A

Falling

Int Enable

Capture A

Falling

Event

Capture B

Falling

Bit 0

Capture A

Rising

Int Enable

Capture A

Rising

Event

Figure 19-7. Capture Timers Status Register (Address 0x45)

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Table 19-1. Capture Timer Prescalar Settings (Step si ze and range for F

Prescale 2:0 Capture Fr om : LSB Step Size Range

000 Bits 7:0 of free running timer 1 µs 256 µs
001 Bits 8:1 of free running timer 2 µs 512 µs
010 Bits 9:2 of free running timer 4 µs 1.024 ms
011 Bits 10:3 of free running timer 8 µs 2.048 ms
100 Bits 11:4 of free running timer 16 µs 4.096 ms

= 6 MHz)

CLK

CY7C63742/43

20.0 Processor Status and Control Register

7 6 5 4 3 2 1 0

R R/W R/W R/ W R/W R R/W R/W

IRQ

Pending

The Run bit (bit 0) is manipul ated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at
the end of the current instruction. The pr ocessor remains halted until a reset occurs (low-voltage, brown-out, or watch dog). This
bit should normally be written as a 1.

Bit 1 is a reserved bit that mus t be writt en as a 0.
The Interrupt Enable Sense (bit 2) sho ws whether in terrupts are enab led or di sabl ed. Firmware has no direct control ov er this bit

as writing a zero or one to this bit position wi ll have no effect on int errupts. A ‘0’ indicates that interrupt s are masked off and a ‘1’
indicates that the interrupts ar e enable d. This bi t is further gate d with the bit set tings of the Global In terrupt Enab le Regis ter ( 0x20)
and USB Endpoint Interrupt Enable Register (0x21). Instructions DI, EI, and RETI manipulate the state of this bit.

Writing a 1 to the Suspend bit (bit 3) will halt the processor and cause the microcontroller to enter the suspend mode t hat
significantly reduces power consumption. A pending, enabled interrupt or USB bus activity will cause the device to come out of
suspend. After coming out of suspend, the de vi ce will res ume firmwar e e xec ution at the inst ructi on f ollo wing the IO WR which pu t
the part into su spend . Wh en writ ing t he suspe nd b it wi th a resum e condi tion pr esent (such as n on-idl e USB ac tivi ty), the susp end
state will stil l be entered, fol lowed immed iately by the wak e-up process (wi th appropriate dela ys for th e clock start-up). See Section

11.0 for more details on suspend mode oper ation.
The Low-Voltage or Brown-Out Reset (bit 4) is set to 1 during a power-on reset. Firmware can check bits 4 and 6 in the reset

handler to determine whether a reset w as caused by a LVR/BOR condition or a watch dog timeout. (Note that a LVR/BOR event
may be followed by a watch dog reset before firmware begins executing, as explained below.)

The Bus Interrupt Event (bit 5) is set whenever the event for the USB Bus Reset / PS/2 Activity interrupt occurs. The event type
(USB or PS/2) is selected by the state of the USB-PS/2 I nterrupt Mode bit (see
that set this bit are given in Section 21.3.1. In either mode, this bit is set as soon as the event has lasted for the specified time
(128–256 µs), and the bit will be set e ven if the interrupt is not enabled. The bit is onl y cleared by firmware or LVR/WDR.

The Wat ch Dog Reset (bit 6) is set during a reset initiated by the Watch Dog Timer. This indicates the Watch Dog Timer went for
more than t

IRQ pending (bit 7), when set, indicates one or more of the interrupts has been recognized as active. This bit is only valid if the
Global Int errupt Enable bit is disabled. An interrupt will re ma in pending until its interrupt enable bit is set (registers 0x20 or 0x21)
and interrupts are gl oball y enabled. At that point the internal interrupt handling sequence will clear this bit unt il ano th e r inte r r u pt
is detected as pending.

During power-up, or duri ng a low-voltage reset, the Processor Status and Cont rol Register is set to 00010001, which indicates a
LVR/BOR (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). Note that during the t
start-up (explained in Section 10.1), a Watch Dog Reset will also occur. When a WDR occurs during the power-up suspend
interval, firmware would read 01010001 from the Status and Control Register after power-up. Normally the LVR/BOR bit should
be cleared so that a subsequent WDR can be clearl y identified.

examines this register, the Bus Interrupt Event bit would al so be set.

During a Watch Dog Reset , the Processor Status and Contro l Regi ster is set to 01XX0001, which indic ates a Watch Dog Reset
(bit 4 set) has occurred and no interrupts are pending (bit 7 clear).

Watch Do g

Reset

(8 ms minimum) between Watch Dog clears. This can occur with a POR/LVR event, as note d below.

WATCH

Bus Interrupt

Event

Figure 20-1. Processor Status and Control Register (Address 0xFF)

Low V oltage or

Brown-Out

Reset

Suspend Interrupt

Enable

Sense

Figure 13-1

Note that if a USB bus reset (long SE0) is receiv ed before firmware

). The details on the event conditions

Reserved Run

START

ms partial suspend at

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CY7C63742/43

21.0 Interrupts

Interrupts can be generated by the GP IO lines, the internal free-running timer, the SPI b lock, the c apture timers , on various USB
events, PS/2 activity, or by the wake-up timer. All interrupts are maskable by the Global Interrupt Enable Register and the USB
End Point Interrupt Enable Register. Writing a 1 to a bit position enables t he interrupt associated with that bit position. During a
reset, the co ntents of the interrupt enable registers are cleared, along wit h the Global Interrupt ena ble bit of the CPU, effectively
disabli ng all interrupts.

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/ W

Wake-up

Interrupt

Enable

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved EP2

GPIO

Interrupt

Enable

Figure 21-2. USB End Poi nt Interrupt Enable Register (Address 0x21)

Capture
Timer B

Intr. Enable

Figure 21-1. Global Interrupt Enable Register 0x20h (read/write)

Capture
Timer A

Intr. Enable

SPI

Interrupt

Enable

1.024 ms
Interrupt

Enable

Interrupt

Enable

128 µs

Interrupt

Enable

R/W R/W R/W

EP1

Interrupt

Enable

USB Reset /
PS/2 Activity

Intr. Enable

EP0

Interrupt

Enable

The interrupt cont roll er conta ins a separ ate fl ip- flop f or ea ch inter rupt. See
controller. When an interrupt is generated it is first registered as a pending interrupt. It will stay pending until it is serviced or a
reset occurs. A pending interrupt will only generate an interrupt request if it is enabled by the corresponding bit in the interrupt
enable regi ster s. The high est prio rity int errupt r equest wi ll be serviced f ollo wi ng the com plet ion of the cu rr ently ex ec uting instruc­tion.

When servicing an interrupt, the hardware will first disable all interrupts by clearing the Global Interrupt Enable bit in the CPU
(the state of this bit can be read at Bit 2 of the Processor Status and Control Register). Next, the flip-flop of the current interrupt
is cleared. This is followed by an automatic CALL instruction to the ROM address associated with the interrupt being serviced
(i.e., the Interrupt Vector, see Section 21.1). The instruction in the interrupt table is typically a JMP instruction to the address of
the Interrupt Service Routine (ISR). The user can re-enable interrupt s in the interrupt service routine by executing an EI instruc­tion. Interrupt s can be nested to a level limi ted only by the available stack space.

The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for insuring that the
processor state is preserved and restored during an i nterrupt. The PUSH A instruction should typically be used as the first
command in t he ISR t o save the accumul ator value and the POP A inst ruction should be used just befor e the RETI instruction to
restore t he accum ulator v alue . The p rogram c ounter , CF and ZF are r estored a nd inter rupts are enabled when t he RETI i nstruction
is executed.

The DI and EI instructions can be used to di sable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used t o re-enable interrupts while inside an ISR, instead of waiting for th e
RETI that exits the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examin ing the IRQ Sense bit (Bit 7 in the Processor Status and Control Register ).

Figure 21-3

for the l ogic b lock dia gram of the int errupt

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Wake-up

Int

1

USB­PS/2
Int

1

EP2
Int

PRELIMINARY

USB-PS/2 Clear

CLR

Q

D

CLK

CLR

D

CLK

CLR

1

D

CLK

Enable [0]

(Reg 0x20)

Q

Enable [2]

(Reg 0x 21 )

Q

Enable [7]

(Reg 0x 20)

USB-PS/2 IRQ
128 µs CLR

128 µs IRQ
1 ms CLR

1 ms IRQ

EP0 CLR

EP0 IRQ
EP1 CLR

EP1 IRQ
EP2 CLR

EP2 IRQ
SPI CLR

SPI IRQ

Capture A CLR

Capture A IRQ

Capture B CLR

Capture B IRQ

GPIO CLR
GPIO IRQ

Wake-up CLR

Wake-up IR Q

Interrupt

Priority

Encoder

Interrupt

Vector

IRQout

To CPU

CPU

Global

Interrupt

Enable

Bit

CLR

Interrupt

Acknowledge

CY7C63742/43

IRQ Pending

(Bit 7, Reg 0xFF)

IRQ

Int Enable
Sense

(Bit 2, Reg 0xFF)

Controlled by DI, EI, and
RETI Instructions

Figure 21-3. Interrupt Controller Logic Block Diagram

21.1 Interrupt Vectors

The Interrupt Vectors supported by the de vice are listed in
activity), and the lo we st priority int errupt is #11 (W ak e-up Ti mer). Although Reset is not an interrupt , the fir st inst ructi on executed
after a reset is at ROM addr ess 0x0000h, which corr esponds to the first entry in the Interru pt Vect or T abl e. Interrupt vec tors occupy
2 bytes to allow for a 2 byte JMP instruction to the appropriate Interrupt Service Routine (ISR).

T able 21-1. Interrupt Vector Assignments

Interrupt Vector Number ROM Address Function

not applicable 0x0000 Execution af ter Reset begins here.

1 0x0002 USB Bus Reset or PS/2 Activity interrupt
2 0x0004 128-µs timer interrupt
3 0x0006 1.024-ms timer interrupt
4 0x0008 USB Endpoint 0 interrupt
5 0x000A USB End point 1 interrupt
6 0x000C USB Endpoint 2 interrupt
7 0x000E SPI Interrupt
8 0x0010 Capture Timer A interrupt

9 0x0012 Capture Timer B interrupt
10 0x0014 GPIO interrupt
11 0x0016 Wake-up Timer interrupt

T able 21-1

. The highest pri ori ty interrupt is #1 (USB Bus Reset / PS/ 2

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21.2 Interrupt Latency

Interrupt latency can be calculated from the following equation:
Interrupt Latency = (Number of clock cycles remai ning in the current i nstruction) + (10 clock cycles f or the CALL instruction) +

For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine will execute a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt
is issued. With a 6 MHz e xternal resonator, i nternal CPU clock speed is 12 MHz, so 20 cloc ks take 20 / 12 MHz = 1.67 µs.

(5 clock cycles for the JMP inst ruction)

21.3 Interrupt Sources

The foll owing sections pro vide details on the different types of interrupt sources.

21.3.1 USB Bus Reset or PS/ 2 Acti vity

The function of this interrupt is selectable between detection of either a USB bus reset condition, or PS/2 activity. The selection
is made wit h the USB–PS/2 Interrupt Mode bi t in the USB St atus and Control Register (
will occur if the selected condition exists for 256 µs, and may occ ur as earl y as 128 µs.

A USB bus reset is indicated by a single ended ze ro (SE0) on the USB D+ and D– pins. The USB interrupt occurs when the SE0
condition ends. PS/2 activity is indicated by a continuous low on the SDATA pin. The PS/2 interrupt occurs as soon as the long
low state is detected.

21.3.2 Free Running Timer Interrupts

There are two periodic timer interrupts from the free-running timer: the 128-µs interrupt and t he 1.024-ms interrupt (based on a
6-MHz clock). The user should disable bot h timer interrupts before going into the suspend mode t o avoid possible conflicts
between servicing the timer interrupts first or the suspend request first when waking up.

Figure 13-1

). In either case, the interrupt

21.3.3 USB Endpoint Interrupts

There are three USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to
a USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet
of the transaction (e.g., on the host’s ACK during an IN, or on the device ACK during on OUT). If no ACK is received during an
IN transact ion, no interrupt will be generated.

21.3.4 SPI Interru p t

The SPI interrupt occurs at the end of each SPI byte transaction, at the final clock edge, as shown in
interrupt, the received data byt e can be read from the SPI Data Register, and th e TCMP cont rol bit will be high

21.3.5 Capture Timer Interrupts

There are two capture timer interrupts, one for each associated pin. Each of these interrupts occurs on an enabled edge of the
selected GPIO pin(s). F or each pin, ri sing and/or falling edge capture interrupts can be in selected. Refer to Section 19.0. These
interrupts are in dependent of the GPIO interrupt, described i n the next section.

21.3.6 GPIO Inter r upt

Each GPIO pin c an serve as an int errupt i nput. During a re set, GPI O inter rupts ar e disab led b y c learin g all GPI O inter rupt enab le
registers. Writing a 1 to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin. These registers
are show n in
main GPIO interrupt mu st be enabled, as explained in Section 21.0.

The polarity that triggers an interrupt is controlled independently for each GPIO pin by the GPIO Interrupt Polarity Registers.
Settin g a Polar ity bi t to “0” allows an interrupt on a falling GPIO edge, while setting a Polarity bit to “1” allows an interrupt on a
rising GPIO edge. The Polarity Registers reset to 0 and are shown in

All of the GPIO pins share a single interrupt vector, which means the firmware will need t o read the GPIO ports with enabled
interrupts to determine which pin or pins caused an interrupt.The GPIO interrupt structure is illustrated in

Note that if one port pin triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to
its inactive (non-trigger) state or it s corresponding port interrupt enable bit is cleared. The CY7C637xx does not assign interrupt
priority to different port pins and the Port Inter rupt Enab le Registers are not affected by the interrupt acknowledge process.

Figure 21-4

for Port 0 and

Figure 21-5

for Port 1. In addition to enabl ing the desi red indivi dual pins f or int errupt, the

Figure 21-6

for Por t 0 and

Figure 21-7

Figure 17-4

for Port 1.

Figure 21-8

. After th e

.

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CY7C63742/43

7 6 5 4 3 2 1 0

W W W W W W W W

P0.7

Intr Enable

P0.6

Intr Enable

P0.5

Intr Enable

P0.4

Intr Enable

P0.3

Intr Enable

P0.2

Intr Enable

P0.1

Intr Enable

Figure 21-4. P ort 0 Int errupt Enable Register (Address 0x04)

7 6 5 4 3 2 1 0

W W W W W W W W

P1.7

Intr Enable

P1.6

Intr Enable

P1.5

Intr Enable

P1.4

Intr Enable

P1.3

Intr Enable

P1.2

Intr Enable

P1.1

Intr Enable

Figure 21-5. P ort 1 Int errupt Enable Register (Address 0x05)

7 6 5 4 3 2 1 0

W W W W W W W W

P0.7

Intr Polarity

P0.6

Intr Polarity

P0.5

Intr Polarity

P0.4

Intr Polarity

P0.3

Intr Polarity

P0.2

Intr Polarity

P0.1

Intr Polarity

Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06)

P0.0

Intr Enable

P1.0

Intr Enable

P0.0

Intr Polarity

7 6 5 4 3 2 1 0

W W W W W W W W

P1.7

Intr Polarity

P1.6

Intr Polarity

P1.5

Intr Polarity

P1.4

Intr Polarity

P1.3

Intr Polarity

P1.2

Intr Polarity

P1.1

Intr Polarity

Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07)

1

Global

Enable

GPIO Interr upt
Flip Flop

DQ

CLR

Interrupt

Priority

Encoder

GPIO
Pin

IRA

1 = Enable
0 = Disable

Port Bit Interrupt

Polarity Register

M
U
X

Port Bit Interrupt
Enable Register

(1 input per

1 = Enable
0 = Disable

OR Gate

GPIO pin)

GPIO Interrupt

(Bit 6, Register 0x20)

P1.0

Intr Polarity

IRQout

Interrupt

Vector

Figure 21-8. GPIO Interrupt Diagram

36

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USB CY7C63722/23

PRELIMINARY

CY7C63742/43

21.3.7 Wake-up Interrupt

The internal wake-up timer can be used to wake the part from suspend m ode (al though it can also provide an interrupt when the
part is awak e). T he w ake-u p timer is cl ear ed whene v er t he wa ke-u p inter rupt ena ble b it ( Regi ster 0x 20) is written t o a 0, and runs
whenev er that bit i s written to a 1. When the inter rupt is enabled, the wake-u p timer prov ides periodic int errupts with period t
The wake- up ti m e can be adjusted by firmware as explained in Section 11.2.

WAKE

22.0 USB Mod e Tables

The following tabl es give details on mode setting for the USB Serial Interface Engine.

T able 22-1. USB Register Mode Encoding

Mode Encoding Setup In Out Comments

Disable
Nak In/Out

Status Out Only
Stall In/Out
Ignore In/Out
Reserved
Status In Only
Reserved
Nak Out

[3]

=0)

Ack
Ack Out

(STALL

[3]

=1)

Nak Out - Status In
Ack Out - NAK In
Nak In

[3]

(STALL

STALL

=0)

[3]

=1)

Ack IN
Ack IN(

Nak In - Status Out
Ack In - Status Out

Note:

3. STALL bit is the bit 7 of the USB Non-Control Device Endpoint Mode registers. Refer to Section 14.3 for more explanation.

The ‘In’ column represents the SIE’s response to the token type.
A disabled endpoint will remain disabled until changed by f irmwar e, and al l endpoints reset to the disabled state.
Any SETUP pack et to an enabled endpoint with mode set to accept SETUPs will be changed by the SI E to 0001 (NAKi ng). Any

mode set to accept a SETUP will ACK a valid SETUP transaction.
Most modes t hat control transactions involving a n ending ACK will be changed by the SIE to a cor responding mode which NAKs

subsequent packets following the AC K. Exceptions are modes 1010 and 1110.
A Control endpoint has three extra status bits for PID (Setup, In and Out), but must be placed in the correct mode to function as

such. Non-Contr ol endpoints should not be placed into modes that accept SETUPs.
A ‘check’ on an Out token during a St atus tr ansact ion checks to see that t he Out is of z ero len gth and has a Data Toggle (DTOG)

of 1.

0000
0001

ignore ignore ignore I gnore all USB traffic to this endpoint

accept NAK NAK Forced from Set up on Control endpoint, fro m m odes other

than 0000

0010
0011
0100
0101
0110
0111
1000

1001
1001

1010
1011
1100
1101

1101
1110
1111

accept stall check For Control endpoints
accept stall stall For Control endpoints
accept ignore i gnore For Control endpoints

ignore ignore always Not Complaint or Low-speed device

accept TX 0 stall For Control Endpoints

ignore TX cnt ignore Not Complaint or Low-speed device
ignore ignore NAK An ACK from mode 1001 --> 100 0
ignore

ignore

ignore
ignore

ACK

stall

This mode is changed by SIE on issuance of ACK --> 1000

accept TX 0 NAK An ACK from mode 1011 --> 1010
accept NAK ACK This mode is changed by SIE on issuance of AC K --> 0001

ignore NAK ignore An ACK from mode 1101 --> 1100
ignore

ignore

TX cnt

stall

ignore
ignore

This mode is changed by SIE on issuance of ACK --> 1100

accept NAK check An ACK from mode 1111 --> 111 Ack In - Status Out
accept TX cnt check This mode is changed by SIE on issuanc e of ACK -->1110

.

37

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USB CY7C63722/23

Table 22-2. Decode table for

PRELIMINARY

T able 22-3

: “Details of Modes for Differing Traffic Conditions”

CY7C63742/43

Properties of incoming packet

Encoding Status bits What the SIE does to Mode bits

PID Status bits Interrupt?

End Point Mode
3 2 1 0 Token count buffer dval DTOG DVAL COUNT

Setup
In
Out

The validity of the received data

The quality status of the DMA buffer

The number of received bytes Acknowledge phase completed

Legend:

UC: unchanged TX: transmit TX0: trans m it 0-length packet
x: don’t care RX: receive
available for Control endpoint only

Setup In Out ACK 3 2 1 0 Response Int

End Point
Mode

The response of the SIE can be summarized as follows:

1. The S IE will o n ly res p o nd to vali d tra n s actions, and will ignore non-valid ones.

2. The SIE wil l genera te an inter rupt when a val id transac tion i s completed or when t he FIFO is corrupted. FIFO corruption occ urs
during an OUT or SETUP transacti on to a valid internal address, that ends with a non-valid CRC.

3. An incoming Data packet is valid if t he count is <

Endpoint Size + 2 (includes CRC) and passes all error checki ng;

4. An IN will be ignored by an OUT configured endpoint and visa versa.

5. The IN and OUT PID status is updated at the end of a transaction.

6. The SETUP PID status is updated at the beginning of the Data packet phase.

7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that
endpoint in which an ACK is transfer red. These regist ers are only unlocked by a CPU read of these registers, and only if that
read happens after the transacti on completes. This represents about a 1-µs window i n which the CPU is locked from register
writes to these USB registers. Normally the firmware should perform a reg ister read at the beginning of the Endpoint ISRs to
unlock and get the mode register information. The interlock on the Mode and Count registers ensures that the firmware
recognizes the changes that the SIE might ha ve made during the previous transact ion.

38

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USB CY7C63722/23

PRELIMINARY

CY7C63742/43

T able 22-3. Details of Modes for Differi ng Traffic Conditions

End Point Mode PID Set End Point Mode
3 2 1 0 token count buffer dval DTOG DVAL COUNT Setup In Out ACK 3 2 1 0 response int
Setup Packet (if accepting)
SeeTable 22-1. Setup <= 10 data valid updates 1 updates 1 UC UC 1 0 0 0 1 ACK yes
SeeTable 22-1. Setup > 10 junk x updates updates updates 1 UC UC UC NoChange ignore yes
See Tab le 22-1. Setup x junk inv alid updates 0 updates 1 UC UC UC NoChange ignore yes
Disabled
0 0 0 0 x x UC x UC UC UC UC UC UC UC NoChange ignore no
Nak In/Out
0 0 0 1 Out x UC x UC UC UC UC UC 1 UC NoChange NAK yes
1 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 0 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
0 0 0 1 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Ignore In/Out
0 1 0 0 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 0 0 In x UC x UC UC UC UC UC UC UC NoChange ignore no
Stall In/Out
0 0 1 1 Out x UC x UC UC UC UC UC 1 UC NoChange Stall yes
1 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 0 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
0 0 1 1 In x UC x UC UC UC UC 1 UC UC NoChange Stall yes
Control Write
Normal Out/
1 0 1 1 Out <= 10 data valid updates 1 updates UC UC 1 1
1 0 1 1 Out > 10 j unk x updates upda tes updates UC U C 1 UC NoChange ignore yes
1 0 1 1 Out x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes
1 0 1 1 In x UC x UC UC UC UC 1 UC
NAK Out/premature status In
1 0 1 0 Out <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 0 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 0 1 0 In x UC x UC UC UC UC 1 UC 1 NoChange TX 0 yes
Status In/extra Out
0 1 1 0 Out <= 10 UC valid UC UC UC UC UC 1 UC 0 0 1 1 Stal l yes
0 1 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
0 1 1 0 In x UC x UC UC UC UC 1 UC 1 NoChange TX 0 yes
Control Read
Normal In/premature status Out
1 1 1 1 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
1 1 1 1 Out 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 Stall yes
1 1 1 1 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes
1 1 1 1 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 1 1 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 1 1 1 In x UC x UC UC UC UC 1 UC 1 1 1 1 0 ACK (back) yes
3 2 1 0 token count buffer dval DTOG DVAL COUNT Setup In Out ACK 3 2 1 0 response int
Nak In/premature status Out
1 1 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
1 1 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 Stall yes
1 1 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes
1 1 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no

NAK In

UC

0001

NoChange

ACK yes

NAK

yes

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USB CY7C63722/23

PRELIMINARY

T able 22-3. Details of Modes for Differi ng Traffic Conditions

1 1 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 1 1 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Status Out/extra In
0 0 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
0 0 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 Stall yes
0 0 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes
0 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
0 0 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
0 0 1 0 In x UC x UC UC UC UC 1 UC UC 0 0 1 1 Stall yes
Out endpoint
Normal Out/erroneous In
1 0 0 1 Out <= 10 data valid updates 1 updates UC UC 1 1 1 0 0 0 ACK yes
1 0 0 1 Out > 10 j unk x updates upda tes updates UC U C 1 UC NoChange ignore yes
1 0 0 1 Out x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes
1 0 0 1 In x UC x UC UC UC UC UC UC UC NoChange ignore no
NAK Out/erroneous In
1 0 0 0 Out <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 0 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 0 0 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 0 0 0 In x UC x UC UC UC UC UC UC UC NoChange ignore no
Reserved
0 1 0 1 Out x updates updates updates updates updates UC UC 1 1 NoChange RX yes
0 1 0 1 In x UC x UC UC UC UC UC UC UC NoChange ignore no
In endpoint
Normal In/erroneous Out
1 1 0 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 0 1 In x UC x UC UC UC UC 1 UC 1 1 1 0 0 ACK (back) yes
NAK In/erroneous Out
1 1 0 0 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 0 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Reserved
0 1 1 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 1 1 In x UC x UC UC UC UC 1 UC UC NoChange TX yes

(continued)

CY7C63742/43

23.0 Absolu te M aximum Ratings

Storage Temperature ....... ..................................... .............. ....................... .. .............. .........................................–65°C t o +150°C

Ambient Temperature with Power Applied ...............................................................................................................–0°C to +70°C

Supply Voltage on V

DC Input Voltage.......................................................................................................................................... –0.5V to +VCC+0.5V

DC Voltage Applied to Outputs in High Z State .......................................................................................... –0.5V to + VCC+0.5V

Maximum Total Sink Output Current into Port 0 and 1 and Pins........................ .. ..................................... ........... .. .. ............ 7 0 mA

Maximum Total Source Output Current into Port 0 and 1 and Pins........... ....................... ................................................... 30 mA

Maximum On-chip Power Dissipation on any GPIO Pin ................................................................................... ... .............. ..50 mW

Power Dissipation .......................................................................................................................... .. ............... ...................300 mW

Static Dischar ge Voltage ................................................................................................................................................... >2000V

Latch- u p Cu rr e nt ...... ........................... .............. ............... .............. ............... ................................................................. >200 mA

Relative to VSS..................................................................................................................–0.5V to +7 .0 V

CC

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24.0 DC Characteristics

F

= 6 MHz; Operating Temperature = 0 to 70°C

OSC

Parameter Min Max Units Conditions

General

V

CC1

V

CC2

I

CC

I

SB1

I

SB2

V

PP

T

RSNTR

I

IL

I

SNK

I

SRC

V

LVR

t

VCCS

V

RG

C

REG

V

OHU

V

OLU

V

OHZ

V

DI

V

CM

V

SE

C

IN

I

LO

R

PU

R

PD

V

OLP

R

PS2

R

UP

V

ICR

V

ICF

V

HC

V

ITTL

V

OL1A

V

OL1B

V

OL2

V

OL3

V

OH

R

XIN

Operating Voltage 4.0 5.5 V Note 4
Operating Voltage 4.35 5.25 V Note 4
VCC Operating Supply Current 25 mA V
Standby Curren t - No Wake-up Osc 25
Standby Curren t - With Wake-up Osc 75
Programming Voltage (disabled) –0.4 0.4 V
Resonator Start-up Interval 256
Input Leakage Current 1
Max ISS GPIO Sink Current 70 mA Cumulativ e across all ports
Max ICC GPIO Source Current 30 mA Cumulative across al l ports

Low Voltage & Power-On Reset

Low-Voltage Reset Trip Voltage 3.6 3.9 V VCC below V
VCC Power-on Slew Time 100 ms linear ramp: 0 to 4V

USB Interface

VREG Regulator Output Voltage 3.0 3.6 V Load = RPU +R
Capacitance on VREG Pin 300 pF External cap not required
Static Output High, driven 2.8 3.6 V RPD to Gnd
Static Output Low 0.3 V With RPU to VREG pin
Static Output High, idle or suspend 2.7 3.6 V R

Differentia l In put Sensitivity 0.2 V |(D+)–(D–)|
Differential Input Common Mode Range 0.8 2.5 V
Single Ended Receiv er Thr eshold 0.8 2.0 V
Transceiver Capacit ance 20 pF
Hi-Z State Data Line Leakag e –10 10
External Bus Pull-up resistance (D–) 1.274 1.326 k
External Bus Pull-down resistance 14.25 15.75 k

PS/2 Interface

Static Output Low 0.4 V Isink = 5 mA, SDATA or SCLK pins
Inter n al PS /2 P ul l- up R esistance 3 7 k

General Purpose I/O Interface

Pull-up Resist ance 8 24 k
Input Threshold Voltage, CMOS mode 40% 60% V
Input Threshold Voltage, CMOS mode 35% 55% V
Input Hysteresis Voltage, CMOS mode 3% 10% V
Input Threshold Voltage, TTL mode 0.8 2.0 V Ports 0, 1, and 2
Output Low Voltage, high drive mode 0.8

Output Low Voltage, medium drive mode 0.4 V I
Output Low Voltage, low drive mode 0.4 V I
Output High Voltage, strong drive mode VCC–2 V Port 0 or 1, IOH = 2 mA
Pull-down resistance, XTALIN pin 50 k

PRELIMINARY

0.4

CY7C63742/43

= 5.5V, no GPIO loading

CC

µ

A O scillat o r of f, D – > 2.8 V

µ

A O scillat o r of f, D – > 2.8 V

µ

sVCC = 5.0V, ceramic resonator

µ

AAny I/O pin

for >100 ns

LVR

[7]

[8, 9]

PD

[4]

connected D– to Gnd, RPU con-

PD

nected D– to VREG pin

µ

A0 V < Vin<3.3 V (D+ or D– pins)

Ω

1.3 kΩ ±2% to VREG

Ω

15 kΩ ±5% to Gnd

Ω

SDATA, SCLK pins, PS/2 Enabled

Ω

Low to high edge, Por t 0 or 1

CC

High to low edge, Port 0 or 1

CC

High to low edge, Port 0 or 1

CC

V

I

= 50 mA, Ports 0 or 1

V

OL1

I

= 25 mA, Ports 0 or 1

OL1

= 8 mA, Ports 0 or 1

OL2

= 2 mA, Ports 0 or 1

OL3

Ω

Internal Cl ock M ode only

[4]

[10]

[4]

[4]
[4]
[4]

[4]

[5]
[5]

[6]

41

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USB CY7C63722/23

PRELIMINARY

CY7C63742/43

25.0 Switching Characteristics

Parameter Description Min. Max. Unit Conditions

Internal Clock Mode

F

ICLK

F

ICLK2

T

CYC

T

CH

T

CL

T

START

T

WAKE

T

WATCH

T

R

T

R

T

F

T

F

T

RFM

V

CRS

Internal Clock Frequency 5.7 6.3 MHz Internal Clock Mode enab led
Internal Clock Frequency, USB

mode

5.91 6.09 MHz Internal Cloc k M ode enabled, Bit 2 of regis­ter 0xF8h is set (Pr ecision USB Clocki ng)

External Oscillator Mode

Input Clock Cycle Time 164.2 169.2 ns USB Operation, with External ±1.5%

Ceramic Resonator or Crystal

Clock HIGH Time 0.45 t
Clock L OW Time 0. 45 t

CYC
CYC

ns

ns
Time-out Delay after LVR/BOR 24 60 ms
Internal Wake-up Period 1 5 ms Enabled Wake-up Interrupt
Watc hDog Timer Period 10.1 14.6 ms F

OSC

= 6 MHz

USB Driver Characteri stics

Transition Rise Time 75 ns CLoad = 200 pF (10% t o 90%
Transition Rise Time 300 ns CLoad = 600 pF (10% to 90%
Transition Fall Time 75 ns CLoad = 200 pF (10% t o 90%
Transition Fall Time 300 ns CLoad = 600 pF (10% to 90%
Rise/Fall Time Matching 80 125 % tr/t
Output Signal Crossover Voltage 1.3 2.0 V CLoad = 200 to 600 pF

[4, 13]

f

[4]

[12]

[11]

[4]

)

[4]

)

[4]

)

[4]

)

T

DRATE

T

DJR1

T

DJR2

T

DEOP

T

EOPR2

T

EOPT

T

UDJ1

T

UDJ2

T

LST

T

FPS2

T

SMCK

T

SSCK

T

SCKH

T

SCKL

T

MDO

USB Data Timing

Low Speed Data Rate 1.4775 1.5225 Mb/s Ave. Bit Rate (1.5 Mb/s ±1.5%)
Receiver Data Jitter Tolerance –75 75 ns To Next Transi tion
Receiver Data Jitter Tolerance –45 45 ns For Paired Transitions

[14]

[14]

Diffe rent ial to EOP transition Skew –40 100 ns Note 14
EOP Width at Receiv er 670 ns Accepts as EOP
Source EOP Width 1.25 1.50

µ

s
Differentia l D r ive r Ji tt er –95 95 ns To next transition,
Differentia l D r ive r Ji tt er –150 150 ns To paired transition,

[14]

Figure 25-5

Figure 25-5

Width of SE0 during Diff . Transition 210 ns

Non-USB Mode Driver

Note 15

Characteristics

SDATA / SCK Tr ansit ion Fall Time 50 300 ns CLoad = 150 pF to 600 pF

SPI Timing

SPI Master Clock Rate 2 MHz F

Figures 25-6 to 25-9

See

Figure 17-1

/3; see

CLK

[16]

SPI Slave Clock Rate 2.2 MHz
SPI Clock High Time 125 ns High for CPOL=0, Low for CPOL=1
SPI Clock Low Time 125 ns Low for CPOL=0, High for CPOL=1
Master Data Output Time –25 50 ns SCK to data valid

42

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USB CY7C63722/23

PRELIMINARY

CY7C63742/43

Parameter Description Min. Max. Unit Conditions

T

MDO1

Master Data Output Time,

100 ns Time before leading SCK edge

First bit with CPHA=1

T

MSU

T

MHD

T

SSU

T

SHD

T

SDO

T

SDO1

T

SSS

T

SSH

Notes:

4. Full functionality is guaranteed in V

5. Total current cumulative across all Port pins, limited to minimize Power and Ground-Drop noise effects.

6. LVR is automatically disabled during suspend mode.

7. LVR will re-occur whenever V

8. V

RG

is not regulated, and should not be used as a general source of regulated voltage in that case. During receive of USB data, the VREG output drops when D- is
low due to internal series resistance of approximately 200Ω at the VREG pin.

9. In suspend mode, V

10. The 200Ω internal resistance at the VREG pin gives a standard USB pull-up using this value. Alternately, a 1.5 kΩ,5%pull-up from D- to an external 3.3V supply
can be used.

11. Initially F

12. Wake-up time for Wake-up Adjust Bits cleared to 000b (minimum setting)

13. Tested at 200 pF.

14. Measured at cross-over point of differential data signals.

15. Non-USB Mode refers to driving the D–/SDATA and/or D+/SCLK pins with the Control Bits of the USB Status and Control Register, with Control Bit 2 HIGH.

16. SPI timing specified for capacitive load of 50 pF, with GPIO output mode = 01 (medium low drive, strong high drive).

.

Master Input Data Set-Up time 50 ns
Master Input Data Hold time 50 ns
Slave Input Data Set-Up Time 50 ns
Slave Input Data Hold Time 50 ns
Slave Data Output Time 100 ns SCK to data valid
Slave Data Output Time,

100 ns Time after SS LOW to data valid

First bit with CPHA=1
Slave Sel ect Set-Up Time 150 ns Befor e first SCK edge
Slave Sel ect Hold Time 150 ns After last SCK edge

range, except USB transmitter specifications and GPIO output currents are guaranteed for V

CC1

drops below V

specified for regulator enabled, idle conditions (i.e. no USB traffic), with load resistors listed. During USB transmits from the internal SIE, the VREG output

ICLK2=FICLK

CC

is only valid if RPU is connected from D– to VREG pin, and RPD is connected from D– to ground.

RG

until a USB packet is received.

. In suspend or with LVR disabled, BOR occurs whenever VCC drops below approximately 2.5V.

LVR

CC2

range.

CLOCK

V

oh

V

crs

V

ol

T

CYC

T

CH

T

CL

Figure 25-1. Cloc k Timing

90%

T

F

10%

T

+

D

R

90%

10%

−

D

Figure 25-2. USB Data Signal Timing

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USB CY7C63722/23

T

PERIOD

Differential
Data Lines

PRELIMINARY

T

JR

Consecutive

Transitions

N * T

Figure 25-3. Receive r Jit ter T olerance

PERIOD

+ T

JR1

Transitions

N * T

Paired

PERIOD

+ T

JR2

CY7C63742/43

T

JR1

T

JR2

T

PERIOD

Differential
Data Lines

T

Differential
Data Lines

PERIOD

Crossover

Crossover

Point Exten de d

Point

Diff. Data to

N * T

SE0 Skew

+ T

PERIOD

DEOP

Source EOP Width: T
Receiver EO P Width: T

Figure 25-4. Differential to EOP Tran sit ion Skew and EOP Width

Crossover

Points

Consecutive

Transitions

N * T

PERIOD

+ T

xJR1

Transitions

N * T

Paired

PERIOD

+ T

xJR2

EOPT

EOPR1

, T

EOPR2

Figure 25-5. Differential Data Jitter

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USB CY7C63722/23

SS

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MISO

T

MDO

PRELIMINARY

(SS is under firmware control in SPI Master mode)

T

SCKL

T

SCKH

MSB

MSB LSB

CY7C63742/43

LSB

SS

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MISO

T

SSS

T

SDO

T

T

MSU

MHD

Figure 25-6. SPI Master Timing, CPHA= 0

T

SCKL

T

SCKH

MSB LSB

T

T

SSU

SHD

MSB

LSB

T

SSH

Figure 25-7. SPI Slave Ti ming, CPHA=0

45

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USB CY7C63722/23

SS

SCK (CPOL=0)

SCK (CPOL=1)

T

MOSI

MISO

MDO1

T

MSU

T

MHD

PRELIMINARY

(SS is under firmware control in SPI Master mode)

T

SCKL

T

SCKH

T

MDO

MSB

CY7C63742/43

LSB

LSBMSB

SS

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

T

SDO1

MISO

T

SSS

T

SSU

T

SHD

T

SCKH

MSB

Figure 25-8. SPI Master Timing, CPHA= 1

T

SCKL

T

SDO

T

SSH

LSBMSB

LSB

Figure 25-9. SPI Slave Ti ming, CPHA=1

46

FOR

FOR

enCoRe™

USB CY7C63722/23

PRELIMINARY

CY7C63742/43

26.0 Ordering Information

EPROM

Ordering Code

CY7C63722-PC 6 KB
CY7C63723-PC 8 KB P3 18-Pin (300-Mil) PDIP Commercial
CY7C63742-PC 6 KB P13 24-Pin (300-Mil) PDIP Commercial
CY7C63743-PC 8 KB P13 24-Pin (300-Mil) PDIP Commercial
CY7C63742-SC 6 KB S13 24-Pin Small Outline Package C ommercial
CY7C63743-SC 8 KB S13 24-Pin Small Outline Package C ommercial

Document #: 38- 00944

Size

Package

Name

P3 18-Pin (300-Mil) PDIP Commercial

Package Type

Operating

Range

27.0 Package Diagrams

18-Lead(300-Mil) MoldedDIP P3

24-Lead(300-Mil) MoldedSOIC S13

51-85010-A

51-85025-A

47

enCoRe™

PRELIMINARY

24-Lead(300-Mil) MoldedDIP P13/P13A

USB CY7C63722/23

CY7C63742/43

51-85013-A

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.