Datasheet CY7C43644AV, CY7C43664AV, CY7C43684AV Datasheet (CYPRESS)

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Page 1

查询CY7C43644AV供应商

CY7C43644AV

PRELIMINARY

3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching

Features

• 3.3V high-speed, l ow-power, bidirectional, First-I n FirstOut (FIFO) memori es w/ bus matching capabil it ies

• 1Kx36x2 (CY7C43644 AV)

• 4Kx36x2 (CY7C43664 AV)

• 16Kx36x2 (CY7C43684AV)

• 0.25-micr on CMOS for optimum speed/powe r

• High-speed 133- MHz operat ion (7.5- ns read /write c ycle times)

• Low power

= 60 mA

—I

= 12 mA

—I

Logic Block Diagram

CLKA

CSA

W/RA

ENA MBA

RT2

MRS1

PRS1

FFA/IRA

AFA

Por t A Control Logic

FIFO1, Mail1 Reset Logic

Input

Write Pointer

Mail1 Register

1K/4K/16K

Dual Ported Memory

Status Flag Logic

x36

CY7C43664AV/CY7C43684AV

• Fully asynchronous and simultaneous read and write operation permitted

• Mailbox bypass register for each FIFO

• Parallel and Serial Programmable Almost Full and Almost Empty flags

• Ret ra n smit func tion

• Standard or FW FT mod e user sel ectable

• Partial Reset

• Big or Little Endian format for word or byte bus sizes

• 128-Pin TQFP packaging

• 3.3V pin-compatible, feature enhanced, density upgrade to IDT723624/34/44 family

• Easily expandable in width and depth

Port B Control Logic

Read Pointer

Bus Matching

Output

MBF1

CLKB CSB W/RB ENB MBB RTI BE BM SIZE

EFB/ORB AEB

SPM

FS0/SD

FS1/SEN

0–35

EFA/ORA

AEA

MBF2

Cypress Semiconductor Corporation

Programmable Flag Offset Registers

Output

Write Pointer

Status Flag Logic

1K/4K/16K

x36 Dual Ported Memory

Mail2 Register

Timing Mode

Read Pointer

Input

FIFO1, Mail1 Reset Logic

B BE/FWFT

FFB/IRB AFB

MRS2

PRS2

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600 August 30, 1999

0–35

Page 2

CY7C43644AV

Pin Configuration

W/RA

ENA

CLKA

GND

A A A A

A A

GND

A A A A A A A

BE/FWFT

GND

A A A A

GND

A A A A A

RT2

GND

A A

PRELIMINARY

CY7C43664AV/CY7C43684AV

TQFP

Top View

/RB

GND

FFB/IRB

MBF2

AEA

AFA

VCCPRS1

EFA/ORA

FFA/IRA

CSA

128

127

126

125

124

123

1 2 3

122

121

MBA

120

MRS1

119

FS0/SD

118

GND

117

GND

116

FS1/SEN

115

MRS2

114

MBB

113

112

VCCMBF1

111

AEB

110

AFB

109

4 5

34 33

8 9

13 14

27 26

18 19

20 21

27 28

33 34

35 36

CY7C43644AV CY7C43664AV CY7C43684AV

39404142434445464748495051525354555657585960616263

6A7A8A9

GND

A3A4A

SPM

0A1

GND

5B4B3B2B1

EFB/ORB

108

CSB

ENB

107

106

105

104

103

102

CLKB

101

PRS2 V

100

GND

94 93

RT1

87 86

84 83

GND

GND B

SIZE

GND

B9B8B

Page 3

CY7C43644AV

PRELIMINARY

Functional Description

The CY7C436X4AV is a monolithic, high-speed, low-power, CMOS Bidirectional Synchronous (clocked) FIFO memory which supports cloc k freque ncies up to 133 M Hz an d h as read access times as fast as 6 ns. Two independent 1K/4K/16K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit fo rmats wit h a choice of Big or Little Endian configurations.

The CY7C436X4AV is a synchronous (clocked) FIFO, meaning each port emplo ys a sync hron ous int erf ace . All data t ransfers th rough a port are gate d to the LO W - to-HI GH trans iti on of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidi rectional i nterfac e between microproces sors and/or buses with synchronous control.

Communication b etw een each port ma y b ypas s the FIF Os via two mailbox registers. The mailbox registers’ width matches the selected P ort B bus width. Each mailbo x register has a f lag (MBF1

and MBF2) to signal when new mail has been stored.

T w o kinds of reset are a vailab le on th e CY7C436X4A V : Master Reset and Partial Reset . Master Rese t init ializ es t he read and write pointers to the fi rst location of the memory array, configures the FIFO for Big or Little Endian byte arrangement and selects serial flag programming, parallel flag program m ing, or one of the three possible default flag offset settings, 8, 16, or

64. Each FIFO has its own independent Master Reset pin, MRS1

and MRS2.

Partial Reset also sets the read and write pointers to the first location of the memory. Unlike M aster Reset, any set tings existing prior to P artial Reset ( i.e., progr amming meth od and partial flag default offsets) are retained. Partial Reset is useful since it permits fl ushing of the FI FO memory witho ut chang in g any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1

The CY7C436X4AV have two modes of operation: In the CY Standard mode, the first word writt en to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First-Word Fall-Through mode (FW FT), the first

and PRS2.

CY7C43664AV/CY7C43684AV

long-word (36-bit wide) written to an empty FIFO appears automatically on the out puts, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/FWFT operation dete rmines t he mod e in use.

Each FIFO has a combined Empty/Output Ready flag (EFA ORA and EFB (FFA

/IRA and F FB/IRB). The EF a nd FF func tions ar e select ed in the CY Standard mode. EF is full or not. The IR and OR functions are sele cted in the First Word F all- Through mode. IR indi cates whet her or not the FIFO has ava il able memory locations. OR shows whet her the FIFO has data available for read ing or not. It marks the presence of valid data on the outputs.

Each FIFO has a programmable Al mo st Empty flag (AEA AEB

) and a programmable Almost Full flag (AFA and AFB).

AEA

and AEB indicate when a selected number of words written to FIFO memory achieve a predetermined “almost empty state.” AFA words written t o the m emory achi ev e a predet ermined “almost full sta te.”

IRA, IRB, AFA writes data into its array. ORA, ORB, AEA chronized to th e port clock that reads data from its arr ay. Programmable offset for AEA parallel usi ng Port A or i n serial v ia the SD i nput. Three d efault offset settings are also pro vided . The AEA can be set at 8, 16, or 64 locations from the empty boundary and AF A from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider data paths. If at any time the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (I minimum. Init iating any oper ati on (b y act iv atin g contr ol inputs ) will immediately take the device out of the Power Down state.

A Retransmit feature is available on these devices. The CY7C436X4AV are characterized for operation from 0

to 70

C. Input ESD protect ion is g reater than 2001V, and latch-

up is prevented by the use of guard rings.

/ORB) and a combined Full/Input Ready flag

indicates whether the memory

and AFB indicate when a selected number of

, and AFB are synchro nized to the port clock tha t

, AEB, AFA, and AFB are loaded in

and AFB threshol d can be se t at 8, 16, or 64 locat ions

pin during F IFO

and

, and AEB are syn-

and AEB threshold

) is at a

Selectio n Gu ide

CY7C43644/64/84AV

Maximum Frequency (MHz) 133 100 66.7 Maximum Access Time (ns) 6 8 10 Minimum Cycle Time (ns) 7.5 10 15 Minimum Data or Enable Set-Up (ns) 3 4 5 Minimum Data or Enable Hold (ns) 0 0 0 Maximum Flag Delay (ns) 6 8 10 Active Power Supply

Current (I

Density 1K x 36 x2 4K x 36 x2 16K x 3 6 x 2 Package 128 TQFP 128 TQFP 128 TQFP

CC1

) (mA)

Commercial 60 60 60 Industrial 60

CY7C43644AV CY7C43664AV CY7C43684AV

−

CY7C43644/64/84AV

−

CY7C43644/64/84AV

−

Page 4

CY7C43644AV

PRELIMINARY

CY7C43664AV/CY7C43684AV

Pin Definitions

Signal Name Description I/O Function

0–35

AEA

AEB

AF A Port A Almost

AFB

0–35

BE/FWFT

BM Bus Match

CLKA Port A Clock I CLKA is a continuous clock t hat synchr onizes al l data tr ansf ers through P ort A a nd can

CLKB Port B Clock I CLKB is a continuous clock t hat synchr onizes al l data tr ansf ers through P ort B a nd can

CSA

CSB

EFA

/ORA Port A Empty/

EFB

/ORB Port B Empty/

ENA Port A Enable I ENA must be HIGH to enable a L O W -to- HIGH tra nsition of CLKA to rea d or write dat a

ENB Port B Enable I ENB must be HIGH to enable a L O W -to- HIGH tra nsition of CLKB to rea d or write dat a

FFA

/IRA Port A Full/Input

Port A Data I/O 36-bit bidirectional data port for side A. Port A Almost

Empty Flag

Port B Almost Empty Flag

Full Flag

Port B Almost Full Flag

Port B Data I/O 36-bit bidirect ional data port for side B. Big Endian/

First-Word FallThrough Select

Select (Port A)

Port A Chip Select

Port B Chip Select

Output Ready Flag

Ready Flag

O Programmab le Almost Empty flag sy nchroni zed to CLKA. It is LO W when the numb er

of words in FIFO2 is less t han or equa l to the val ue in the Alm ost Empty A of fset register , X2.

O Programmab le Almost Empty flag sync hroni zed to CLKB . It is LO W when the nu mber

of words in FIFO1 is less t han or equa l to the val ue in the Alm ost Empty B of fset register , X1.

O Programmab le Almost Full flag synchronized to CLKA. It is LOW when the number of

empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset register, Y1.

O Programmab le Almost Full flag synchronized to CLKB. It is LOW when the number of

empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset register, Y2.

I This is a dual-purpose pin. During Maste r Reset, a HIGH on BE will selec t Big Endian

operation. In thi s case, depe nding on the bus size, the most signi ficant byt e or word on Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LO W on BE will select Little Endia n operati on. In this case , the lea st significant byte or word on Port A is read from P ort B fir st ( for A-to-B da ta f low) or written to Port B first (B-to -A data flo w). Af ter Mast er Reset , th is pi n selec ts th e timi ng mode . A HI GH on FWFT Once the timing mode has be en selecte d, the le ve l on FWFT device operation.

I A HIGH on this pin enables either b yte or wor d bus widt h on Po rt B, dependin g on the

state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. The lev el of BM must be st ati c throughout device operation.

be asynchronous or coincident to CLKB. FFA synchronized t o the LOW-to-HIGH transition of CLKA.

be asynchronous or coincident to CLKA. FFB synchronized t o the LOW-to-HIGH transition of CLKB.

ICSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on

Port A. The A

ICSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on

Port B. The B

O This is a dual -function pin. In the CY Stand ard mode , the EF A func tion is selected. EF A

indicates whether or not the FIFO2 memo ry is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on A able for reading. EFA

O This is a dual-funct ion pin. In the CY Standard mode , the EFB functio n is selected. EFB

indicates whether or not the FIFO1 memo ry is empty. In the FWFT mode, the ORB function is selected. ORB indicates the presence of valid data on B able for reading. EFB

on Port A.

on Port B.

O This is a dual-fu nction pi n. In the CY Stand ard mode, the FFA function is selecte d. FF A

indicates whether or not t he FIFO1 memory is full. In the FWFT mode , the IRA function is selected. IRA indicat es whether or not there is space av ailable fo r writing to the FIFO1 memory. FFA

selects CY Standard mode , a LOW selects First-Word Fall-Thro ugh m ode.

outputs are in the high-impedance state when CSA is HIGH.

0–35

outputs are in the high- impedance state when CSB is HIGH.

0–35

/ORA is synchronized to t he LOW-to-HIGH transition of CLKA.

/ORB is synchronized to t he LOW-to-HIGH transition of CLKB.

/IRA is syn ch r on i ze d to th e L OW-to-H IG H tra n s iti o n o f CLK A .

must be stati c through out

/IRA, E FA/ORA, AFA, and AEA are all

/IRB, EFB /ORB, AFB, and AEB are all

outputs, avail-

0–35

outputs, avail-

0–35

Page 5

CY7C43644AV

PRELIMINARY

Pin Definitions

Signal Name Description I/O Function

FFB/IRB Port B Full/Input

FS1/SEN

FS0/SD Flag Offset

MBA Port A Mailbox

MBB Port B Mailbox

MBF1

MBF2

MRS1

MRS2

PRS1

PRS2

RT1

RT2

SIZE Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9- bit) size on P ort B. A LOW

(continued)

Ready Flag

Flag Offset Select 1/Serial Enable

Select 0/Serial Data

Select

Mail1 Register Flag

Mail2 Register Flag

FIFO1 Master Reset

FIFO2 Master Reset

FIFO1 Partial Reset

FIFO2 Partial Reset

Retransmit FIFO1

Retransmit FIFO2

O This is a du al-functi on pin. I n the CY St andard m ode, th e FFB funct ion is selected. FFB

indicates whether or not t he FIFO2 memory is full. In the FWFT mode , the IRB function is selected. IRB indicat es whether or not there is space av ailable fo r writing to the FIFO2 memory. FFB

I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-

ming. During Master Reset , FS1/ SEN offset program ming method. Three offs et register prog ramming methods are a vailab le: automatically load one of three preset values (8, 16, or 64), parallel l oad from Port A,

and serial load. When serial load i s selec ted f or fl ag offs et regi ster p rogr amming, FS1/ SEN

is used as an enab le synchron ous to the LO W -to-HIGH tr ansition of CLKA. When FS1/SEN and Y registers. The number of bi t writes r equir ed to pr ogr am the of fset re gisters i s 4 0 for the CY7C43644AV, 48 for the CY7C43664AV, and 56 f or the CY7C43684AV. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB.

I A HIGH lev el on MBA chooses a mailbox regi ster for a Port A read or write operation.

When the A register for output and a LOW level select s FIFO2 output register data for output.

I A HIGH lev el on MBB chooses a mailbox regi ster for a Port B read or write operation.

When the B register for output and a LOW level select s FIFO1 output register data for output.

OMBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail 1

register. Writes to the Mail1 register are inhibited while MBF1 HIGH by a LOW- to-HI GH transiti on of CLKB when a Po rt B read is selected and MBB is HIGH. MBF1

OMBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail 2

register. Writes to the Mail2 register are inhibited while MBF2 HIGH by a LOW- to-HI GH transiti on of CLKA when a Po rt A read is selected and MBA is HIGH. MBF2

I A LOW on this pin initializes the FIFO1 read and write pointers to the first locati on of

memory and sets the P ort B output register to a ll zeroes. A LOW puls e on MRS1 the programmi ng method (serial or parallel ) and one of th ree programmab le flag def ault offsets f or FIFO1. It al so confi gures Port B for bus siz e and endian arr a ngement. F ou r LOW-t o-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1

I A LOW on this pin initializes the FIFO2 read and write pointers to the first locati on of

memory and sets the P ort A output register to a ll zeroes. A LOW puls e on MRS2 one of three program ma ble flag default offsets for FIFO2. Four LOW-to- HIGH transitions of CLKA and four LOW-to-H IGH transitions of CLKB must occur whi le MRS2 LOW.

I A LOW on this pin initializes the FIFO1 read and write pointers to the first locati on of

memory and sets the Port B output register to all zeroes. During Partial Reset, the currently selected bus size , endian arrangement, programmi ng me thod (serial or parallel), and progr am m able flag settings are all retained.

I A LOW on this pin initializes the FIFO2 read and write pointers to the first locati on of

memory and sets the Port A output register to all zeroes. During Partial Reset, the currently selected bus size , endian arrangement, programmi ng me thod (serial or parallel), and progr am m able flag settings are all retained.

I A LOW strobe on this pin will retransmit data on FIFO1 fro m the location of the write

pointer at the last P artial or Master reset.

I A LOW strobe on this pin will retransmit data on FIFO2 fro m the location of the write

pointer at the last P artial or Master reset.

on this pin when BM is HIGH sele cts word (18-bit) bus size. SI ZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation.

/IRB is syn ch r on i ze d to th e L OW-to-H IG H tra n s iti o n o f CLK B.

is LOW, a rising edge on CLKA loads t he bit present on FS0/SD into the X

outputs are active, a HIGH level on MBA selects data from the Mail2

0–35

outputs are active, a HIGH level on MBB selects data from the Mail1

0–35

is set HIGH following either a Master or Partial Reset of FIFO1.

is set HIGH following either a Master or Partial Reset of FIFO2.

is LOW.

CY7C43664AV/CY7C43684AV

and FS0/SD , toget her with SPM, sel ect the f lag

is LOW. MBF1 is se t

is LOW. MBF2 is se t

selects

Page 6

CY7C43644AV

CY7C43664AV/CY7C43684AV

Pin Definitions

PRELIMINARY

(continued)

Signal Name Description I/O Function

SPM

W/RA

RB Port B Write/

Maximum Ratings

Serial Programming

Port A Write/ Read Select

Read Select

[1]

I A LOW on this pin se lects serial prog ramming o f partial flag offs ets. A HIGH on thi s pin

selects paral lel programming or default off sets (8, 16, or 64).

I A HIGH selects a write operation and a LOW selects a read operation on Port A for a

LOW-t o-HIGH transition of CLKA. The A when W/RA

is HIGH.

0–35

I A LOW selects a write operation and a HIGH sel ects a read operation on Port B for a

LOW-to-HIGH transitio n o f CLKB . T h e B when W

/RB is LOW.

0–35

Static Discharge Voltage ........... ............ .. ............ .. ....>2001V

(per MIL-STD-883, Method 3015) (Abov e which the useful life may be impaired. For user guidelines, not tested.)

Latch-Up Current .....................................................>200 mA

Storage Temperature .......... ............ .............–65°C to +150°C

Ambient Temperature with

Operating Range

Power Applied...............................................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Voltage Applied to Outputs in High Z State

DC Input Voltage

[2]

......................................–0.5V to VCC+0.5V

[2]

...................................–0.5V to VCC+0.5V

Range

Commercial 0°C to +70°C 3.3V ± 10% Industrial –40°C to +85°C 3.3V ± 10%

Output C ur re n t in to O u tp u ts (LOW) ..... ......... .......... .....20 mA

outputs are i n the high-impedance state

outputs are in the high-impedance state

Ambient

Temperature

[3]

Electrical Characteristics

Over the Operating Range

CY7C43644/64/84AV

Parameter Description Test Conditions

OZL

OZH

[4]

CC1

[5]

Capacitance

Output HIGH Voltage VCC = 3.0V ,

= –2.0 mA

Output LOW Voltage VCC = 3.0V ,

= 8.0 mA

Input HIGH Volta g e 2.0 V Input LOW Voltage –0.5 0.8 V Input Leakage Current V Output OFF, High Z

= Max. –10 +10 µA

VSS < VO< V

Current Active Power Supply

Current Ave rage Standby

Current

[6]

2.4 V

0.5 V

–10 +10

Com’l 60 mA Ind 60 mA Com’l 12 mA Ind 12 mA

UnitMin. Max.

µA

Parameter Description Test Conditions Max. Unit

OUT

Notes:

1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

3. Operating V

4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded.

5. All inputs = V

6. Tested initially and after any design or process changes that may affect these parameters.

Range for -7 speed is 3.3V ± 5%.

– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.

Input Capacitance TA = 25°C, f = 1 MHz,

= 3.3V

Output Capacitance 8 pF

4 pF

Page 7

CY7C43644AV

PRELIMINARY

AC Test Loads and Waveforms (-10 & -15)

R1=330

3.3V

OUTPUT

CL=30 pF

INCLUDING

JIG AND

SCOPE

AC Test Loads and Waveforms (-7)

I/O

Z0=50

Ω

R2=680

Ω

VCC/2

50Ω

Ω

3.0V

GND

3.0V

GND

CY7C43664AV/CY7C43684AV

ALL INPUT PULSES

90%

10%

≤

90%

10%

3ns

ALL INPUT PULSES

90%

10%

3ns

Switching Characteristics

Over the Operating Range

Parameter Description

CLK

CLKH

CLKL

ENS

RSTS

FSS

BES

SPMS

SDS

SENS

FWS

ENH

Note:

7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

Clock Frequency, CLKA or CLKB 133 100 67 MHz Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns Set-U p Tim e, A

CLKB↑

before CLKA↑ and B

0–35

before

Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB

Set-Up Time, M RS1, MRS2, PRS1, or PRS2 LOW before CLKA↑ or CLKB↑

, W/RB, ENB, and MBB be for e CLKB↑

[7]

Set-Up Time , FS0 and FS1 bef ore MRS1 a nd MRS2 HIGH

Set-Up Time, BE/FWFT before MRS1 and MRS2 HIGH

Set-Up Time, SPM before MRS 1 and MRS2 HIGH 5 7 7.5 ns Set-Up Time, FS0/SD before CLKA↑ 3 4 5 ns Set-Up Time, FS1/SEN before CL K A ↑ 3 4 5 ns Set-Up Time, BE/FWFT before CLKA↑ 0 0 0 ns Hold Time, A

CLKB↑

after CLKA↑ and B

0–35

after

Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB

, W/RB, ENB, and MBB after CLKB↑

CY7C43644/

64/84AV

–7

CY7C43644/

64/84AV

–10

CY7C43644/

64/84AV

–15

UnitMin. Max. Min. Max. Min. Max.

3 4 5 ns

2.5 4 5 ns

5 7 7.5 ns

0 0 0 ns

1 2 0 ns

Page 8

CY7C43644AV

CY7C43664AV/CY7C43684AV

CY7C43644/

64/84AV

–7

CY7C43644/

64/84AV

–10

CY7C43644/

64/84AV

–15

Switching Characteristics

PRELIMINARY

Over the Operating Range (continued)

Parameter Description

RSTH

FSH

BEH

SPMH

SDH

SENH

SPH

SKEW1

SKEW2

WFF

REF

PAE

PAF

Hold Time, MRS1, MRS 2, PRS1, or PRS2 LOW after CLKA↑ or CLKB↑

[7]

Hold Time, FS0 and FS1 after MRS1 and MRS2

1 1 4 ns

1 1 2 ns

HIGH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 0 0 2 ns Hold Time, SPM after MRS1 and MRS2 HIGH 0 0 2 ns Hold Time, FS0/SD after CLKA↑ 0 1 0 ns Hold Time, FS1/SEN after CLKA↑ 5 5 0 ns Hold Time, FS1/SEN HIGH after MRS1 and MRS2

2 2 2 ns

HIGH

[8]

Skew Time between CLKA↑ and CLKB↑ for EFA/ ORA, EFB

[8]

Skew Time between CLKA↑ and CLKB↑ for AEA, AEB

Access Time, CLKA↑ to A

/ORB, FFA/IRA, and FFB/IRB

, AFA, AFB

and CLKB↑ to B

0–35

Propagation Delay Time, CLKA↑ to FFA/IRA a n d CLKB↑ to FFB

/IRB

Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to EFB

/ORB

Propagation Delay Time, CLKA↑ to AEA and

0–35

7.5 7.5 7.5 ns

7 8 12 ns

1 6 1 8 3 10 ns 1 6 1 8 2 10 ns

1 6 1 8 1 10 ns

CLKB↑ to AEB Propagation Dela y Time, CLKA↑ to AFA and CLKB↑

1 6 1 8 1 10 ns

to AFB

PMF

Propagation Delay Time, CLKA↑ to MBF 1 LOW or MBF2

HIGH and CLKB↑ to MBF2 LOW or MBF 1

0 6 0 8 0 10 ns

HIGH

PMR

MDV

RSF

DIS

Propagation Delay Time, CLKA↑ to B CLKB↑ to A

0–35

[10]

Propagation Delay Time, MBA to A MBB to B

0–35

Va lid

Propagation Delay Time, MRS1 or PRS1 LOW to AEB

LOW, AFA HIGH, FFA / IRA LOW, EFB /ORB LOW and MBF1 AEA

LOW, AFB HIGH, FFB / IRB LOW, EFA /ORA LOW and MBF2

HIGH and MRS2 or PRS2 LOW t o

HIGH

Enable Time, CSA or W/RA LOW to A and CSB

LOW and W/RB HIGH to B

Disable Time , CSA or W/RA HIGH to A Impedance an d CSB

HIGH or W/RB LOW to B

at High Impedance

PRT

RTR

Notes:

8. Ske w time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB cycle.

9. Writing data to the Mail1 register when the B

10. Writing data to the Mail2 register when the A

Retransmit pulse Width 60 60 60 ns Retransmit Recovery Time 90 90 90 ns

outputs are active and MBB is HIGH.

0–35

outputs are active and MBA is HIGH.

0–35

Valid and

0–35

[9]

and

Active

at High

0–35

1 7 2 11 3 12 ns

1 6 2 9 3 11 ns

1 6 1 10 1 15 ns

1 5 2 8 2 10 ns

1 5 1 6 1 8 ns

UnitMin. Max. Min. Max. Min. Max.

Page 9

CY7C43644AV

PRELIMINARY

Switching Waveforms

FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight

CLKA

CLKB

RSTS

MRS1

BE/FWFT

SPM

FS1/SEN FS0/SD

FFA

EFB

/IRA

/ORB

RSF

CY7C43664AV/CY7C43684AV

[11, 12]

RSTS

FWS

FWFT

WFF

SPMS

BES

FSS

BEH

SPMH

FSH

RSF

AEB

RSF

AFA

RSF

MBF1

Notes:

11. Master Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.

12. PRS1

must be HIGH during Master Reset.

Page 10

CY7C43644AV

PRELIMINARY

Switching Waveforms

FIFO1 Partial Reset (CY Stan dard and FW FT Mo des)

CLKA

CLKB

PRS1

FFA/IRA

EFB

/ORB

AEB

AFA

MBF1

(continued)

RSTS

RSF

[13, 14]

CY7C43664AV/CY7C43684AV

RSTH

WFF

Parallel Program ming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset

(CY Standard and FWFT Modes)

[15]

CLKA

, MRS2

MRS1

FSS

FSH

SPM

FSS

FSH

FS1/SEN, FS0/SD

FFA/

IRA

WFF

ENS

ENH

ENA

AEB Offset (X1)

AFB

Offset (Y2)

AEA

Offset (X2)

0 − 35

AFA Offset (Y1)

CLKB

/IRB

FFB

Notes:

13. Partial Reset is performed in the same manner for FIFO2.

14. MRS1

15. CSA

16. t

must be HIGH during Partial Reset.

=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.

is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising

SKEW1

edge of CLKA and rising edge of CLKB is less than t

, then FFB/IRB may transition HIGH one cycle later than shown.

SKEW1

[16]

SKEW1

First Word to FIFO1

Page 11

CY7C43644AV

PRELIMINARY

FSH

(continued)

SPH

SDS

AFA Offset (Y1) MSB

SENS

[17]

SENH

SDH

SENS

SDS

AEA Offset (X2) LSB

Switching Waveforms

Serial Programming of the Almost -Full Flag and Almost-Empty Flag Offset Values (CY Standard and FWFT Modes)

CLKA

MRS1

, MRS2

FSS

SPM

FFA/IRA

FS1/SEN

FS0/SD

CLKB

FFA/

IRA

[18]

FSS

CY7C43664AV/CY7C43684AV

WFF

SKEW1

SENH

SDH

WFF

Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

CLK

CLKA

FFA

CSA

/IRA

HIGH

CLKH

CLKL

ENS

ENStENH

ENH

W/RA

ENH

ENS

MBA

ENS

ENH

ENS

ENH

ENS

ENH

ENA

0–35

Notes:

17. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.

18. Programmable offsets are written serially to the SD input in the order AFA

19. Written to FIFO1.

[19]

offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).

Page 12

CY7C43644AV

CY7C43664AV/CY7C43684AV

Switching Waveforms

PRELIMINARY

(continued)

Port B Long-Word Write Cycle Timing for FIFO2 (CY Standard and FW FT Modes)

CLKH

CLK

CLKL

CLKB

/IRB

FFB

HIGH

ENS

ENH

CSB

ENH

ENS

W/RB

ENS

ENH

MBB

ENS

ENH

ENS

ENH

ENB

tDSt

0−35

[20]

ENStENH

Port B Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

CLKB

/IRB

FFB

HIGH

ENS

CSB

ENS

W/RB

ENStENH

ENS

MBB

ENS

ENH

ENS

ENB

0–17

Note:

20. Written to FIFO2.

DStDH

ENH

Page 13

CY7C43644AV

PRELIMINARY

Switching Waveforms

Port B Byte Write Cycle Ti ming for FIFO2 (CY Standard and FWFT Modes)

CLKB

/IRB

FFB

CSB

W/RB

MBB

ENB

0–8

HIGH

(continued)

ENS

ENH

CY7C43664AV/CY7C43684AV

ENH

ENS

Port B Long-Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes )

CLK

CLKH

CLKL

CLKB

EFB

/ORB

CSB

W/RB

MBB

ENS

ENH

ENS

ENH

ENB

0–35

(Standard Mode)

0–35

(FWFT Mode)

Note:

21. Read From FIFO1.

[21]

[21

MDV

Previous Data

]

ENStEN

No Operation

]

[21

]

[21

DIS

Page 14

CY7C43644AV

PRELIMINARY

Switching Waveforms

Port B Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

CLKB

/ORB

EFB

CSB

W/RB

MBB

ENB

0–8

(Standard Mode)

0–8

(FWFT Mode)

HIGH

(continued)

MDV

ENS

ENH

Previous Data

CY7C43664AV/CY7C43684AV

[22]

DIS

No Operation

Port B Byte Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

CLKB

/ORB

EFB

CSB

W/RB

MBB

ENH

ENS

ENB B

0–17

(Standard Mode)

0–17

(FWFT Mode)

Notes:

22. Unused word B

23. Unused bytes B

contains all zeroes for word-size reads.

18–35

, B

18–26

, and B

9–17

MDV

contain all zeroes for byte-size reads.

27–35

Previous Data

[23]

No Operation

DIS

Page 15

CY7C43644AV

PRELIMINARY

Switching Waveforms

Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

CLKA

/ORA

EFA

CSA

W/RA

MBA

ENA

0−35

(Standard Mode)

0−35

(FWFT Mode)

(continued)

CLKH

CLK

MDV

CLKL

ENS

ENH

Previous Data

[24]

CY7C43664AV/CY7C43684AV

[24]

ENS

ENH

ENStENH

No Operation

[24]

DIS

Note:

24. Read From FIFO2.

Page 16

CY7C43644AV

CY7C43664AV/CY7C43684AV

Switching Waveforms

PRELIMINARY

(continued)

ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)

CLK

CLKH

CLKL

CLKA

CSA W/RA

LOW

HIGH

ENS

MBA

ENS

ENA

FFA

0–35

CLKB

/IRA

HIGH

[26]

SKEW

CLKH

CLKL

[25]

REF

EFB

CSB

W/RB

MBB

/ORB

FIFO1 Empty

LOW

HIGH

LOW

CLK

ENB

0–35

Notes:

25. If Port B size is word or byte, EFB

26. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output

SKEW1

register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t load of the first word to the output register may occur one CLKB cycle later than shown.

Old Data in FIFO1 Output Register

is set LOW by the last word or byte read from FIFO1, respectively.

ENStENH

REF

, then the transition of ORB HIGH and

SKEW1

Page 17

CY7C43644AV

PRELIMINARY

Switching Waveforms

EFB Flag Timing and First Data Read F all Through when FIFO1 is Empty (CY Standard Mode)

CLKA

CSA

W/RA

MBA

ENA

FFA

0–35

CLKB

EFB

/IRA

/ORB

LOW

HIGH

FIFO1 Empty

(continued)

[25]

ENH

ENS

ENH

SKEW

[27]

CLKH

CLK

CLKL

REF

CLKH

CLK

CY7C43664AV/CY7C43684AV

CLKL

REF

CSB

W/RB

MBB

LOW

HIGH

LOW

ENB

0–35

Note:

27. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between

SKEW1

the rising CLKA edge and rising CLKB edge is less than t

ENS

ENH

, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

SKEW1

Page 18

CY7C43644AV

PRELIMINARY

Switching Waveforms

ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)

CLKB

CSB

W/RB

MBB

ENB

FFB

/IRB

0–35

CLKA

EFA

/ORA

[28]

LOW

HIGH

FIFO2 Empty

(continued)

ENS

ENH

ENS

SKEW1

[29

]

CLKHtCLKL

CLK

CLKHtCLKL

CY7C43664AV/CY7C43684AV

REF

CSA

W/RA

MBA

LOW

ENA

0–35

Notes:

28. If Port B size is word or byte, t

29. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output

SKEW1

register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than t load of the first word to the output register may occur one CLKA cycle later than shown.

Old Data in FIFO2 Output Register

is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

SKEW1

ENStENH

, then the transition of ORA HIGH and

SKEW1

Page 19

CY7C43644AV

Switching Waveforms

EFA

Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)

CLKB

CSB

W/RB

MBB

ENB

FFB

0–35

CLKA

EFA

/IRB

/ORA

LOW

HIGH

FIFO2 Empty

(continued)

ENH

ENS

ENH

ENS

SKEW1

PRELIMINARY

[30]

CLKHtCLKL

CLK

CLKHtCLKL

REF

CY7C43664AV/CY7C43684AV

[28]

REF

CSA

W/RA

MBA

LOW

ENA

0–35

Note:

30. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the

SKEW1

rising CLKB edge and rising CLKA edge is less than t

ENStENH

, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

SKEW1

Page 20

CY7C43644AV

PRELIMINARY

CLKH

(continued)

CLK

CLKL

ENS

ENH

SKEW1

Next Word From FIFO1

[31]

CLKHtCLKL

CLK

WFF

Switching Waveforms

IRA Flag Timing and First Availabl e Writ e when FIFO1 is Full (FWFT Mode)

CLKB

CSB

W/RB

MBB

ENB

EFB

0–35

CLKA

FFA

/ORB

/IRA

LOW

HIGH

Previous Word in FIFO1 Output Register

FIFO1 Full

CY7C43664AV/CY7C43684AV

[28]

WFF

CSA

W/RA

LOW

HIGH

MBA

ENA

0–35

Note:

31. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the

SKEW1

rising CLKB edge and rising CLKA edge is less than t

ENS

ENH

ENStENH

To FIFO1

, then IRA may transition HIGH one CLKA cycle later than shown.

SKEW1

Page 21

CY7C43644AV

CY7C43664AV/CY7C43684AV

Switching Waveforms

PRELIMINARY

(continued)

FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)

CLK

CLKH

CLKL

CLKB

CSB

W/RB

LOW

HIGH

MBB

ENStENH

ENB

/ORB

EFB

0–35

HIGH

Previ o us Word in FI FO1 Output Register

SKEW1

Next Word From FIFO1

[32]

CLKH

CLKL

CLKA

WFF

FFA

/IRA

FIFO1 Full

CLK

WFF

[28]

CSA

W/RA

LOW

HIGH

MBA

ENA

0−35

Note:

32. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the

SKEW1

rising CLKB edge and rising CLKA edge is less than t

ENH

ENS

ENH

tDHt

, then the transition of FFA HIGH may occur one CLKA cycle later than shown.

SKEW1

Page 22

CY7C43644AV

PRELIMINARY

CLK

(continued)

CLKL

ENS

ENH

SKEW1

Next Word From FIFO2

[34]

CLKH

CLK

CLKL

WFF

Switching Waveforms

IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)

CLKH

CLKA

CSA

W/RA

MBA

ENA

EFA

0–35

CLKB

FFB

/ORA

/IRB

LOW

HIGH

Previo us Word i n FIFO2 Out put Register

FIFO2 Full

CY7C43664AV/CY7C43684AV

[33]

WFF

CSB

W/RB

LOW

ENS

ENH

MBB

ENH

ENS

ENB

tDHt

0–35

To FIFO2

Notes:

33. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long-word, respectively.

34. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the

SKEW1

rising CLKA edge and rising CLKB edge is less than t

, then the transition of IRB HIGH may occur one CLKB cycle later than shown.

SKEW1

Page 23

CY7C43644AV

PRELIMINARY

CLK

(continued)

CLKL

Switching Waveforms

FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standa rd Mode)

CLKH

CY7C43664AV/CY7C43684AV

CLKA

CSA

W/RA

MBA

LOW

ENS

ENH

ENA

EFA

0–35

/ORA

HIGH

Previous Word in FIFO12 Output Register

SKEW1

Next Word From FIFO2

[36]

CLKH

CLKL

CLKB

WFF

FFB

/IRB

FIFO2 Full

CLK

WFF

[35]

CSB

W/RB

LOW

MBB

ENB

0–35

Notes:

35. If Port B size is word or byte, FFB

36. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the

SKEW1

rising CLKA edge and rising CLKB edge is less than t

is set LOW by the last word or byte write of the long-word, respectively.

ENS

ENH

ENStENH

tDHt

To FIFO2

, then the transition of FFB HIGH may occur one CLKB cycle later than shown.

SKEW1

Page 24

CY7C43644AV

Switching Waveforms

Timi ng for A E B

CLKA

ENA

CLKB

AEB

ENB

Timing for AEA

when FIFO2 is Almost Empty (CY Standard and FWFT Modes)

X1 Word in FIFO1

when FIFO2 is Almost Empty (CY Standard and FWFT Modes)

(continued)

ENS

PRELIMINARY

ENH

[39]

SKEW2

CY7C43664AV/CY7C43684AV

[37, 38]

PAE

ENH

PAE

(X1+1)Words in FIFO1

ENS

[40, 41]

CLKB

ENS

ENH

ENB

[42]

SKEW2

CLKA

AEA

X2 Word in FIFO2

PAE

(X2+1)Words in FIFO2

ENS

PAE

ENH

ENA

Notes:

37. FIFO1 Write (CSA

read from the FIFO.

38. If Port B size is word or byte, AEB

39. t

40. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been

41. If Port B size is word or byte, t

42. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between

SKEW2

the rising CLKA edge and rising CLKB edge is less than t read from the FIFO.

is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between

SKEW2

the rising CLKB edge and rising CLKA edge is less than t

= LOW , W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been

is set LOW by the last word or byte read from FIFO1, respectively.

, then AEB may transition HIGH one CLKB cycle later than shown.

SKEW2

is referenced to the rising CLKB edge that writes the last word or byte of the long-word, respectively.

SKEW2

, then AEA may transition HIGH one CLKA cycle later than shown.

SKEW2

Page 25

CY7C43644AV

PRELIMINARY

Switching Waveforms

Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)

CLKA

ENA

AFA

CLKB

ENB

Timing for AFB

CLKB

ENB

AFB

[D–(Y1+1)] Words in FIFO1

when FIFO2 is Almost Full (CY Standard and FWFT Modes)

[D–(Y2+1)] Words in FIFO2

(continued)

ENS

PAF

ENH

PAF

SKEW2

(D–Y1)Words in FIFO1

ENS

ENH

SKEW2

(D–Y2)Words in FIFO2

[45]

[47]

CY7C43664AV/CY7C43684AV

[41, 43, 44]

PAF

[40, 44, 46 ]

PAF

CLKA

ENS

ENH

ENA

Notes:

43. FIFO1 Write (CSA

read from the FIFO.

44. D = Maximum FIFO Depth = 1K for the CY7C43644AV, 4K for the CY7C43664AV, and 16K for the CY7C43684AV.

45. t

46. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long-word, respectively.

47. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the

SKEW2

rising CLKA edge and rising CLKB edge is less than t

is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between

SKEW2

the rising CLKB edge and rising CLKA edge is less than t

= LOW , W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been

, then AFA may transition HIGH one CLKB cycle later than shown.

SKEW2

, then AFB may transition HIGH one CLKA cycle later than shown.

SKEW2

Page 26

CY7C43644AV

Switching Waveforms

(continued)

Timing for Mail1 Register and MBF1

CLKA

CSA

W/RA

MBA

ENA

0–35

CLKB

MBF1

PRELIMINARY

Flag (CY Standard and FWFT Modes)

ENH

ENS

ENH

PMF

CY7C43664AV/CY7C43684AV

[48]

PMF

CSB

W/RB

MBB

ENB

FIFO1 Output Register

Note:

48. If Port B is configured for word size, data can be written to the Mail1 register using A

valid data (B inputs). In this second case, B

will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A

18–35

will have valid data (B

0–8

MDV

will be indeterminate).

9–35

PMR

ENS

W1 (Remains valid in Mail1 Register after read)

0–17

are “Don’t Care” inputs). In this first case B

18–35

ENH

0–8

DIS

0–17

are “Don’t Care”

9–35

will have

Page 27

CY7C43644AV

PRELIMINARY

Switching Waveforms

Timing for Mail2 Register and MBF2 Fla g (CY Standard and FWFT Modes)

CLKB

CSB

W/RB

MBB

ENB

0–35

CLKA

MBF2

(continued)

ENS

ENH

PMF

CY7C43664AV/CY7C43684AV

[49]

PMF

CSA

W/RA

MBA

ENS

ENH

ENA

MDV

PMR

W1 (Remains valid in Mail2 Register after read)

0-35

FIFO1 Retransmit Timing

FIFO2 Output Register

[50, 51, 52, 53]

RT1

PRT

RTR

ENB

EFB/FFA

Notes:

49. If Port B is configured for word size, data can be written to the Mail2 register using B

valid data (A inputs). In this second case, A

50. Retransmit is performed in the same manner for FIFO2.

51. Clocks are free running in this case.

52. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t

53. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t

will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B

18–35

will have valid data (A

0–8

will be indeterminate).

9–35

0–17

are “Don’t Care” inputs). In this first case A

18–35

to update these flags.

RTR

0–8

RTR

DIS

0–17

are “Don’t Care”

9–35

will have

Page 28

CY7C43644AV

PRELIMINARY

Signal Description

Master Reset (MRS1, MRS2)

Each of the t wo FIFO memories of the CY7C436X4AV undergoes a complete reset by taking its associated Master Reset

, MRS2) i nput LOW for a t least f our P ort A clock ( CLKA)

(MRS1 and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset inputs can s witch asynchro nously to the clocks. A Master Reset initializes the internal read and write pointers and forc es the Full /Input Read y flag (FF A the Empty/Output Ready flag (EF A Almost Empty flag (AEA (AFA

, AFB) HIGH. A Master Reset also f orces the Mailbo x flag

(MBF1

, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag is set HIGH after tw o cloc k cycles to beg in normal oper ati on. A Master Reset must be p erformed on the FIF O after po wer up , bef ore data is written to its memory.

A LOW-to-HIGH transition on a FIFO Master Reset (MRS1 MRS2

) input latches the value of the Big Endian (BE) input or determining the order by which bytes are transferred through Port B.

A LOW-to-HIGH transition on a FIFO reset (MRS1 input latches the values of the Flag select (FS0, FS1) and Serial Programming Mode (SPM Full and Almost Empty offset programming method (see Almost Empty and Almost Full fl ag offset programming below).

Partial Reset (PRS1

Each of the t wo FIFO memories of the CY7C436X4AV undergoes a limited reset by taking its associated Partial Reset (PRS1

, PRS2) input LO W fo r at l east four P ort A clock ( CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously to the clocks. A Partial Reset initializes the internal read and write pointers and forc es the Full /Input Read y flag (FF A the Empty/Output Ready flag (EF A Almost Empty flag (AEA (AFA

, AFB) HIGH. A Partial Reset also forces the Mailb o x flag

(MBF1

, MBF2) of the parallel mailbox register HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two cl ock cycles to begin normal oper ation.

Whatever flag offsets, programming method (parallel or serial), and timing mode (FWFT or CY Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will remain unchanged upon completion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be inconvenient.

Big Endian/First Word Fall Through (BE/FWFT

This is a dual-purpose pi n. At the time of Master Reset , the BE select function is active, permitting a choice of Big or Little Endian byte arrangement for data written to or read from Port B. This selection determines the order by which bytes (or words) of data ar e t ransferred th rough t his port. For t he f ollo wing illustrations, assume that a byte (or word) bus size has been selected for Port B. ( Note that when Port B is configured for a l ong word si ze, t he Big Endian function has no appli cation and the BE input is a “Don’t Care ”.)

A HIGH on the BE/FWFT and MRS2) inputs go from LOW to HIGH will select a Big En-

, AEB) LOW, and the Almost Full flag

) inputs f or choosing the Almost

, PRS2)

, AEB) LOW, and the Almost Full flag

input when the M aster Reset (M RS1

/IRA, FFB/IRB) LOW,

/ORA, EFB/ORB) LOW, the

, MRS2)

/IRA, FFB/IRB) LOW,

/ORA, EFB/ORB) LOW, the

)

CY7C43664AV/CY7C43684AV

dian arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the longword written to Port A will be read from Port B first; the least significant b y te (word) of the lo ng word written to Port A will be read from Por t B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be read from Port A as the most significant byte (word) of the long-word; the byte (word) written to Port B last will be read from Port A as the least significant byte (word) of the longword.

A LOW on the BE/FWFT and MRS2) inputs go from LOW to HIGH will select a Little Endian arrangement. When data is moving in the direction from Port A to Port B, the least significant byte (word) of the long word written to Port A will be read from Port B first; the most significant byte (word) of the long-word written to Port A will be read fr om Port B last. Whe n data i s mo ving in the direc tion from P ort B to P ort A, the b yte ( word) written to P ort B first will be read from port A as the least significant byte (word) of

the long-word; t he byte ( word) written to Port B last will be read from Port A as the most significant byte (word) of the longword.

After Master Reset, t he FWFT select func tion is activ e, permitting a choice between two possible timing modes: CY Standard mode or First-Word Fall-Through (FWFT) mode. Once the Master R eset (MRS 1 BE/FWFT CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Standard mode. This mode uses the Empty Flag function (EFA EFB the FIFO memory. It uses the Full Flag function ( FFA indicate whether or not the FIFO memory has any free space for writing. In CY Standard mode, every word read from the FIFO, including the first, must be requested using a formal read operation.

Once the Master Reset (MR S 1 on the BE/FWFT of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready function (ORA, ORB) to indicate whether or not there is valid data at the data outputs (A (IRA, IRB) to indicate whe ther or not the FIFO memory has any free space fo r writing. In the FWFT mode, t he first word written to an empty FIFO goes directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a f ormal r ead operation.

Followi ng Ma ster Reset, the level applied to the BE/FWFT put to choose the desired timing mode must remain static throughout the FIFO ope ration.

Programming the Almost Empty and Almost Full Flags

Four regi sters i n the CY7C436 X4A V are us ed to hold the offset values fo r the Almost Empty and Almost Ful l flags. The P ort B Almost Empty flag (AEB Port A Almost Empty flag (AEA The Port A Almost Full flag (AFA and the Port B Almost Full fl ag (AFB Y2. The index of each register name corresponds with preset values during the reset of a FIFO, programmed in parallel using the FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD) input ( see Table 1). T o l oad a FIFO’s Almost Empty flag and Almost Full flag offset registers with one of the three preset val ues list ed in Table 1, the Serial Pro-

input at the second LOW-to-HIGH transition of

) to indicat e whet her or not t here a re any wo rds present in

input during the next LOW -to-HI GH transi tion

or B

0–35

input when the Master Reset (MRS1

, MRS2) input is HIGH, a HIGH on the

, MRS2) input is HIGH, a LO W

). It also uses the Input Ready func tion

0–35

) offset register is labeled X1 and the

) offset register is labeled X2.

) offset register is label ed Y1

) offset register is l abeled

, FFB) to

in-

Page 29

CY7C43644AV

PRELIMINARY

gram Mode (SPM) and at least one of the flag-select inputs must be HIGH during t he LOW -to-HI GH transit ion of its Mast er Reset input (MRS1 set value of 64 into X1 and Y1, SPM HIGH when FIFO1 reset (MRS1 registers associated with FIFO2 are loaded with one of the preset values in the same way with Master Reset (MRS2 When using one of the preset values for the flag offsets, the FIFOs can be reset simultaneously or at dif ferent times.

To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master Reset on both FIFOs simultaneously with SPM HIGH and FS0 and FS1 LOW during the LOW-to-HIGH transition of MRS1 four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the offset registers are (A (A

), or (A

0–11

highest numbered input is used as the most significant bit of the binary number i n each ca se . Valid programming v alues f or the registers r ange from 1 to 1012 f or the CY7C436 44AV; 1 to 4092 for the CY7C43664A V; 1 to 16380 for the CY7C43684A V . After all the offset registers are programmed from Port A, the Port B Full/ Input Ready ( FFB begin normal operation.

To program the X1, X2, Y1, and Y2 registers s eria ll y, initiate a Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH during t he LO W - to-HI GH tr ans ition of M RS1 and MRS2. After this reset is complete, the X and Y register values are loaded bit-wise through the FS0/SD input on each LOW-toHIGH transition of CLKA that the FS1/SEN Thir ty -two, thir ty-six, forty, forty-eigh t, or fifty - si x b it w rites are needed to complete the programming for the CY7C436X4AV, respectiv ely. The four regist ers are written in the order Y1, X1, Y2, and, finally, X2. The first-bit write stores the most significant bit of the Y1 reg ister and the las t-bit write stores t he least significant bit of the X2 register. Each register value can be programmed from 1 to 1020 (CY7C43644AV), 1 to 4092 (CY7C43664AV), or 1 to 16380 (CY7C43684AV).

When the opt ion t o prog r am the o ffset r egist ers serial l y is chosen, the Port A Full/Input Ready ( FFA until all register bits are written. FFA LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO1 operation. The Port B Full/Input ready (FFB

/IRB) flag also remains LOW throughout the serial programming process, until all register bits are written. FFB is set HIGH by the LOW-to-HIGH transition of CLKB after the last bit is loade d to al low normal FIFO2 operation.

SPM

, FS0/SD, and FS1/SEN function the same way in both

CY Standard and FWFT modes.

FIFO Write/Read Operation

The state of the Port A data (A A Chip Select (CSA The A CSA

lines are in the high-impedance state when either

0–35

or W/RA is HIGH. The A

when bo th CSA Data is loa ded into FIFO1 fro m the A

HIGH transition of CLKA when CSA ENA is HIGH, MBA is LOW , and FF A from FIFO2 to the A of CLKA when CSA is LOW, and EFA

and MRS2). For example, to load the pre-

, FS0, and FS1 must be

) retur ns HIGH. Fl ag-offset

and MRS2. After this reset is complete, the first

), (A

), for the CY7C436X4AV, respectively. The

0–13

0–7

0–8

), (A

0–9

/IRB) is set HI GH and both FIF Os

input is LOW.

/IRA) flag remains LOW

/IRA is set HI GH by t he

/IRB

) lines is controlled by Port

0–35

) and Port A Write/Read Select (W/RA).

lines are active outputs

0–35

and W/RA are LOW.

inputs on a LOW -t o-

0–35

is LOW, W/RA is HIGH,

/IRA is HIGH. Data is read

outputs by a LOW -to-HIGH transition

0–35

is LO W , W/ RA is LO W , ENA is HIGH, MBA

/ORA is HIGH (see Table 2). FIFO reads and

CY7C43664AV/CY7C43684AV

writes on Port A are independent of any concurrent Port B operation.

The Port B contr ol signals are identi cal to those of Port A with the exception that the Port B Write/Read select (W inverse of the Port A Write/Read select (W/RA the Port B data (B

Select (CSB

) and Port B Write/Read select (W/RB) . The B

) lines is controlled by the Por t B Chip

0–35

lines are in the high-impedance state when either CSB is HIGH or W when CSB

Data is loaded into FIFO2 from the B HIGH transition of CLKB when CSB

/RB is LOW. The B

lines are active outputs

0–35

is LOW and W/RB is HIGH.

0–35

is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW , and FFB/IRB is HIGH. Data is read from FIFO1 to the B of CLKB when CSB

MBB is LOW , and EFB

outputs by a LOW -t o-HIGH transiti on

0–35

is LOW, W/RB is HIGH, ENB is HIGH,

/ORB is HIGH (see Table 3). FIFO reads and writes on Port B are independent of any concurrent Port A operation.

The set-up and hold t ime constraints to the port clocks for the port Chip Selects and Write/Read sel ects are onl y for ena bling write and read operations and are not related to high-impedance control of the data o utputs. If a port enabl e is LOW during a clock cycle, the p ort’s Chip Select and Write/Read select may change states during the set-up and hold ti me window of the cycle.

When operating the FIFO in FWFT mode and the Output Ready flag i s LOW, the next word written is automatically sent to the FIFO’s output register by the LOW-to -HIGH transition of the port clock that sets the Output Ready flag HIGH, data residing in the F IFO’s memory array is cloc k ed to t he output reg- ister only when a rea d is sel ec ted usi ng the p ort’s Chip Select , Write/Read select, Enable, and Mailbox select.

When operating the FIFO in CY Standar d mode , r egardle ss o f whether the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is clocked to the output register only when a read is selected using the port’s Chip Select, Write/ Read select, Enable, and Mailbo x select.

Synchronized FIFO Flags

Each FIFO is synchronized to its port clock through at least two flip-flop stages . This is done to improv e flag-sign al reliability by reducing the probability of the metastable events when CLKA and CLKB operate asynchr onously to one another . EF A ORA, AEA EFB

, FFA/IRA, and AFA are synchronized to CLKA.

/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Table 4 and Table 5 show the relat ionship of each port flag to FIFO1 and FIFO2.

Empty/Output Ready Fla gs (EFA

/ORA, EFB/ORB)

These are dual-purpose flags. In the FWFT mode, the Outpu t Ready (ORA, ORB) function is selected. When the Output Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word is prese nt in the FIFO output register and att empted FIFO reads are ignored.

In the CY Standard mode , the Empty Flag (EFA is selected. When the Empty Fl ag is HIGH, da ta is av ai lab le in the FIFO’s RAM memory for reading to the output register. When Empty Flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.

). The state of

inputs on a LOW-to-

, EFB) function

/RB) is the

0–35

Page 30

CY7C43644AV

PRELIMINARY

The Empty/Output Rea dy flag of a FIFO is sync hronized to the port clock that reads data from its array. For both the FWFT and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indic ates when the FIFO SRAM status is empty, empty+1, or empty+2.

In FWFT Mode, from the time a w ord is writte n to a FIFO , it ca n be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three cycles have not elapsed since the time the word was written. The Output Ready f lag of the FIFO remains LO W unti l the thir d LOW-to-HIGH transition of the synchronizing clock occurs, simultaneousl y f orc ing the Out put Ready f lag HIGH and s hift ing the word to the FIFO output register .

In the CY Standard mode , from the time a word is written to a FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in me mo ry is the next dat a to be sent to the FIFO output register and two cycles have not elapsed since the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occ urs, f or cing t he Empty Fl ag HIG H; onl y then can data be read.

A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizi ng clock begins the fir st synchronization cycle of a write if the clock transition occurs at time t after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycl e.

Full/Input Ready Flags (FFA

This is a dual-purpose flag. In FWFT mode, the Input Ready (IRA and IRB) functi on is selected. In CY Stand ard mode, the Full Flag (FFA modes, when the Full/Input Ready flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored.

The Full/Input Read y flag of a FIFO is synchr onized to t he port clock that writ es data to its arra y. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its write pointer is inc rement ed. The st ate machi ne that cont rols a Full/ Input Ready flag monitors a write pointer and read pointer comparator th at indicates when the FIFO SRAM sta tus is full, full–1, or full–2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/ Input Ready flag HIGH.

A LOW- to-HI GH transi tion on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t read. Otherwise, the subsequent clock cycle can be the first synchronization cycle.

and FFB) function is selected. For both timing

/IRA, FFB/IRB)

or greater after the

SKEW1

or greater

CY7C43664AV/CY7C43684AV

Almost Empty Flags (AEA

The Almost Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost Empty flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The Almost Empty state is defined by the contents of register X1 for AEB ed with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset progr ammi ng abo ve) . An Almost Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory.

Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost Empty flag to reflect the ne w le v el of fil l. Theref o re, t he Almost Full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) lev el. A LO W -to-HIGH tr ansition of an Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle.

Almost Full Flags (AFA

The Almost Full flag of a FIF O is sync hronized to the port cloc k that writes data t o it s arr a y. The state machine t hat cont rols an Almost Full f lag mon itor s a write po inter a nd read po inter c omparator that indicates when the FIFO SRAM status is almost full, a lmost full–1, or almost full–2. The Almost Full state is defined by t he contents of regi ster Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming abo ve). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024–Y), (4096–Y), or (16384–Y) for the CY7C436X4AV r espectively. An Almost Full flag is HIGH when the number of words in its FIFO is less than or equal to [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for the CY7C436X4AV respectively. Note that a data word prese nt in t he FIFO out put register has b een read from memory.

Two LOW-to-H IGH tr ansitions of th e Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing [1024/4096/16384–(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in mem ory to [102 4/4 096/16384 –(Y+1 )] . An A lm ost F ull flag is set HIGH by the second LOW-to-HIGH transition of its synchronizin g cloc k after the FI FO re ad that reduces t he num ber of words in memory to [1024/409 6/16384–(Y+1)]. A LOWto-HIGH transition of an Almost Full flag synchronizing clock begins the fi rst synchroni zation cy cle if i t occurs at time t or greater after the read that reduces the number of words in memory to [1024/4096/16384–(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle.

and regist er X2 for AEA. These re gister s are load -

, AEB)

, AFB)

or greater after

SKEW2

Page 31

CY7C43644AV

PRELIMINARY

Mailbox Registers

Each FIFO ha s a 36-b it b yp ass register t o pass c omma nd and control information between Port A and Port B without putting it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usabl e width of both the Mail1 and Mail 2 registers matc h es th e se le ct e d bus s ize for Port B.

A LOW-to-HIGH transition on CLKA writes A Mail1 Register whe n a Port A write is selected b y CSA and ENA with MBA HIGH. If the selected Port A bus size is also 36 bits, then the usable width of the Mail1 Register employs dat a lines A then the usab le widt h of t he Mail1 Re gister emplo ys data lines A

. (In this case, A

0–17

. If the selecte d Po rt A bus size is 18 bi ts,

0–35

are “Don’t Care” inputs.) If the se-

18–35

lected Port A bus size is 9 bits, then the usable width of the Mail1 Register em ploys data lines A “Don’t Care” inputs.)

. (In thi s case , A

0–8

A LOW-to-HIGH transition on CLKB writes B Mail2 Register when a Port B write is selected by CSB and ENB with MBB HIGH. If the selected Port B bus size is also 36 bits, then the usable width of the Mail2 Register employs dat a lines B

. If the selecte d Po rt B bus size is 18 bi ts,

0–35

then the usab le widt h of t he Mail2 Re gister emplo ys data lines B

. (In th is ca se , B

0–17

ed Port B bus size is 9 bit s, then the usable width of the Mail2 Register emplo ys da ta lines B care inputs .)

are don’t care in puts. ) If t he selec t-

18–35

. (In this ca se, B

0–8

Writing data to a mail register sets its corresponding flag (MBF1

or MBF2) LOW . At tempted writes t o a mail regist er are

ignored while the mail fl ag is LOW. When data outputs of a port are active, the data on the bus

comes from the FIFO output register when the port Mailbox Select input is LOW and from the mail register when the port Mailbox Select input is HIGH.

The Mail1 Register Flag (MBF1

) is set HIGH by a LOW-toHIGH transition on CLKB when a Port B read is selected by CSB

, W/RB, and ENB with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B size, 18 bit s of m ailbo x da ta are pl aced on B B

are indeterminate.) For a 9-bit bus size, 9 bits of mail-

18–35

box data are placed on B minate.)

The Mail2 register Flag ( MBF2

. (In this cas e, B

0–8

) is set HIGH by a LOW-to-HIGH

0–35

transition on CLKA when a Port A read is selected by CSA W/RA

, and ENA with MBA HIGH.

For a 36-bit bus size, 36 bits of mailbox data are placed on A

. For a n 18-b it bu s size , 18 bi ts of mailbo x dat a are pl aced

0–35

on A bus size, 9 bits of mailbox data are placed on A case, A

. (In this c ase, A

0–17

are indeterminate.)

9–35

are indeterminate.) For a 9-bit

18–35

The data in a mail register remains intact after it is read and changes only when new data is written to the register. The Endian Select feature has no effect on the mailbox data.

data to the

0–35

, W/RA,

are

9–35

data to the

0–35

9–35

, W/RB,

are don’t

. For an 18-bi t bus

. (In thi s case ,

0–17

are indeter-

9–35

. (In this

0–8

CY7C43664AV/CY7C43684AV

Bus Sizing

The Port B bus can be configured in a 36-bit long-word, 18- bit word, or 9-bit byte format for data read from FIFO1 or written to FIFO2. The levels applied to the Port B Bus Size Select (SIZE) and the Bus Match Select (BM) determine the Port B bus size. These levels should be stati c throughout FIFO operation. Both bus size selections are implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH.

Two different methods for sequencing data transfer are available for Port B when the bus size selection is either byte- or word-size . They are ref erred to as Bi g Endian (most signi ficant byte first) and Little Endian (least significant byte first). The level applied to the Big Endian Select (BE) input during the LOW - to- HIG H tr a nsi ti on of MRS1 an method that will be active during FIFO operation. BE is a “Don’t Care” input when t he bus size sel ected f or P ort B is long word. The endian met hod is impl emented at the com plet ion of Master Reset, by the time the Full/Input Ready flag is set HIGH.

Only 36-bit long-word data is written to or read from the two FIFO memories on the CY7C436X4AV. Bus-matching operations are done after data is read from the FIFO1 RAM and before data is wri tten to FIFO2 RAM . These b us-match ing operations are not available when transferring data via mailbox registers. Furthermore, both the word- and byte-size bus selections limit the width of the data b us that can be used for mail register opera ti ons. In thi s case , only t hose b yte l an es belong ing to the selected word- or byte-size bus can carry mailbox data. The remaining data outputs will be indeterminate. The remaining data inputs will be don’t care inputs. For example, when a word-size bus is selected, then mailbox data can be transmitted only between A bus is select ed, then mai lbo x dat a can be tr ansmit ted on ly between A

0–8

and B

0–8

Bus-Matching FIFO1 Reads

Dat a is read from t he FIFO 1 RAM in 36-b it long- word increments. If a long-w ord bus s ize i s im plement ed, th e ent ire long word immediatel y shifts to t he FIFO1 outpu t regis ter. If byt e or word size is implemented on Port B, only the first one or two bytes appear on the selected portion of the FIFO1 output register , with the re st of the l ong-word stor ed in aux iliary register s. In this case, subsequent FIFO1 reads output the rest of the long word to the FIFO1 output register .

When reading data from FIFO 1 in the b yte or word format, the unused B

outputs are indeterminat e.

0–35

Bus-Matching FIFO2 Writes

Data is written to the FIFO2 RAM in 36-bit long-word increments. Data written to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word of long-word to FIFO2 also st ores the entir e long word in FIFO2 RAM.

When reading data from FIFO2 in byte or word format, the unused B

outputs are LOW.

0–35

and MRS2 selects the endi -

0–17

and B

. When a byte-size

0–17

Page 32

CY7C43644AV

PRELIMINARY

Retransmit (RT1, RT2)

The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmi tted if necessary.

The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been re ad since the last reset cycle. A LO W pulse on RT1 er to the first physical location of the FIFO. CLKA and CLKB

, RT2 resets the internal read poin t-

CY7C43664AV/CY7C43684AV

may be fr ee running b ut must be disabl ed during an d t the retrans mit pulse. Wi th every v alid read cycle after retr ansmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated duri ng a retransmit cycle. Data written to the FIFO after activa tion of RT1 depth of the FIFO can be repeatedly retransmitted.

, RT2 are trans mitte d also. The full

RTR

after

Page 33

CY7C43644AV

PRELIMINARY

BYTE ORDER ON PORT A:

BE BM SIZE

XLX

BE BM SIZE

HHL

27–35

18–26

9–17

(a) LONG-WORD SIZE

18–26

9–17

18–26

9–17

CY7C43664AV/CY7C43684AV

0–8

Write to FIFO

Read from

FIFO

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

(b) WORD SIZE – BIG ENDIAN

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

BE BM SIZE

LHL

27–35

18–26

9–17

BE BM SIZE

HHH

BE BM SIZE

LHH

27–35

18–26

9–17

(d) BYTE SIZE – BIG ENDIAN

27–35

18–26

9–17

(e) BYTE SIZE – LITTLE ENDIAN

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

0–8

3rd: Read from

FIFO

0–8

4th: Read from

FIFO

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

0–8

3rd: Read from

FIFO

0–8

4th: Read from

FIFO

Page 34

CY7C43644AV

PRELIMINARY

CY7C43664AV/CY7C43684AV

Table 1. Flag Programming

SPM

FS1/ SEN

FS0/

SD MRS1 MRS2 X1 and Y1 Registers

[54]

X2 andY2 Registers

[55]

HHH↑ X64 X HHHX↑ X64 HHL↑ X16 X HHLX↑ X16 HLH↑ X8 X HLHX↑ X8 HLL↑↑Parallel programming via Port A Parallel programming via Port A

LHL↑↑ Serial programming via SD Serial progr amm ing via SD L HH↑↑ Reserved Reserved L LH ↑↑ Reserved Reserved L LL ↑↑ Reser ved Reserved

Table 2. Port A Enable Function

CSA

W/RA ENA MBA CLKA A

Outputs Port Functio n

0–35

H X X X X In high-impedance state None

L H L X X In high-impedance state None

LHHL↑ In high-impedance stat e FIFO1 write

LHHH↑ In high-impedance state Mail1 write

L L L L X Active, FIFO2 outp ut r egister None

LLHL↑ Active, FIFO2 output regi ster FIFO2 read

L L L H X Active, Mail2 register None

LLHH↑ Active, Mail2 register Mail2 read (set MBF2

HIGH)

Table 3. Port B Enable Function

CSB

W/RB ENB MBB CLKB B

Outputs Port Function

0–35

H X X X X I n high-impedance state None

L L L X X In hig h-impedance state None

LLHL↑ In high-impeda nce state FIFO2 write

LLHH↑ In high-impedance state Mail2 write

L H L L X Active , FIF O1 output register None

LHHL↑ Active, FIFO1 output register FIFO1 read

L H L H X Active, Mail1 register None

LHHH↑ Active, Mail1 register Mail1 read (set MBF1

Notes:

54. X1 register holds the offset for AEB

55. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.

; Y1 register holds the offset for AFA.

HIGH)

Page 35

CY7C43644AV

PRELIMINARY

CY7C43664AV/CY7C43684AV

T able 4. FIFO1 Flag Operation (CY Standard and FWFT modes)

Number of Words in FIFO Memory

[56, 57, 58, 59 ]

Synchronized to CLKA Synchronized to CLKB

CY7C43644AV CY7C43664AV CY7C43684AV EFB/ORB AEB AFA FFA/IRA

0 0 0 L L H H

1 TO X1 1 TO X1 1 TO X1 H L H H

(X1+1) to

[1024–(Y1+1)]

(1024–Y1) to 1023 (4096–Y1) to 4095 (16384–Y1) to

(X1+1) to

[4096–(Y1+1)]

(X1+1) to

[16384–(Y1+1)]

H H H H

H H L H

16383

1024 4096 16384 H H L L

T able 5. FIFO2 Flag Operation (CY Standard and FWFT modes)

Number of Words in FIFO Memory

[57, 58, 60, 61]

Synchronized to CLKA Synchronized to CLKB

CY7C43644AV CY7C43664AV CY7C43684AV EFB/ORB AEB AFA FFA/IRA

0 0 0 L L H H

1 TO X2 1 TO X2 1 TO X2 H L H H

(X2+1) to

[1024–(Y2+1)]

(1024–Y2) to 1023 (4096–Y2) to 4095 (16384–Y2) to

(X2+1) to

[4096–(Y2+1)]

(X2+1) to

[16384–(Y2+)1]

H H H H

H H L H

16383

1024 4096 16384 H H L L

T able 6. Data Size for Long-Word Writes to FIFO2

Size Mode

BM SIZE BE B

[62]

Data Written to FIFO2 Data Read From FIFO2

27–35

18–26

9–17

0–8

27–35

18–26

9–17

0–8

LXXABCDABCD

T able 7. Data Size for Word Writes to FIFO2

Size Mode

BM SIZE BE B

[62]

Write No. Data Written to FI FO2 Data Read From FIFO2

9–17

0–8

27–35

18–26

9–17

0–8

HLH1ABABCD

2CD

HLL1CDABCD

2AB

Notes:

56. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.

57. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

58. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.

59. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard mode.

60. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.

61. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard mode.quested to the output register (no read operation necessary), it is not included in the FIFO memory count.

62. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

Page 36

CY7C43644AV

PRELIMINARY

CY7C43664AV/CY7C43684AV

Table 8. Data Size for Byte Writes to FIFO2

Size Mode

[62]

Write No.

BM SIZE BE B

Data Wri tten to

FIFO2 Data Read From FIFO2

0–8

27–35

18–26

9–17

0–8

HHH1 A ABCD

2B 3C 4D

HHL1 D ABCD

2C 3B 4A

T able 9. Data Size for FIFO Long-W ord Reads from FIFO1

Size Mode

BM SIZE BE A

[62]

Data Written to FIFO1 Data Read From FIFO1

27–35

18–26

9–17

0–8

27–35

18–26

9–17

LXXABCDABCD

0–8

T able 10. Data Size for Word Reads from FIFO 1

Size Mode

[62]

BM SIZE BE A

27–35

Data Written to FIFO1 Read No.

18–26

9–17

0–8

Data Read From

FIFO1

9–17

0–8

HLHABCD1AB

2CD

HLLABCD1CD

2AB

Table 11. Data Size for Byte Reads from FIFO1

Size Mode

[62]

BM SIZE BE A

27–35

Data Written to FIFO1 Read No.

18–26

9–17

0–8

Data Read From

FIFO1

0–8

HHHABCD1 A

2B 3C 4D

HHLABCD1 D

2C 3B 4A

Page 37

CY7C43644AV

PRELIMINARY

CY7C43664AV/CY7C43684AV

Ordering Information

3.3V 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Speed

(ns) O rd ering C o de

7 CY7C43644AV–7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43644AV–10AC A128 128-Lead Thin Quad Flat Package Commercial 15 CY7C43644AV–15AC A128 128-Lead Thin Quad Flat Package Commercial

3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Speed

(ns) Orde r ing Co de

7 CY7C43664AV–7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43664AV–10AC A128 128-Lead Thin Quad Flat Package Commercial 15 CY7C43664AV–15AC A128 128-Lead Thin Quad Flat Package Commercial

3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Speed

(ns) Orde r ing Co de

7 CY7C43684AV–7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43684AV–10AC A128 128-Lead Thin Quad Flat Package Commercial 15 CY7C43684AV–15AC A128 128-Lead Thin Quad Flat Package Commercial 15 CY7C43684AV–15AI A128 128-Lead Thin Quad Flat P ackage Industrial

Shaded area contains advance information.

Package

Name

Package

Name

Package

Name

Package

Type

Package

Type

Package

Type

Operating

Range

Operating

Range

Operating

Range

Document #: 38–00777

Page 38

Package Diagram

PRELIMINARY

128-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A128

CY7C43664AV/CY7C43684AV

CY7C43644AV

51-85101

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Datasheet CY7C43644AV, CY7C43664AV, CY7C43684AV Datasheet (CYPRESS)

Specifications and Main Features

Frequently Asked Questions

User Manual