Datasheet CY7C43662-15AC, CY7C43662-10AC, CY7C43662-7AC, CY7C43682-7AC, CY7C43682-15AC Datasheet (Cypress Semiconductor)
...Page 1
6\QFKURQRXV ),)2 Z%XV 0DWFKLQJ
Features
• High-speed, l ow-power, bidirectional, F irst- In First-Out
(FIFO) memories
• 1Kx36x2 (CY7C43642)
• 4Kx36x2 (CY7C43662)
• 16Kx36x2 (CY7C43682)
• 0.35-micr on CMOS for optimum speed/power
• High speed 133-MHz oper ation (7.5-ns rea d/write cyc le
times)
• Low power
= 100 mA
—I
CC
—I
= 10 mA
SB
Logic Block Diagram
CY7C43642
CY7C43662
CY7C43682
... [ [ %LGLUHFWLRQDO
• Fully asynchronous and simultaneous rea d and writ e
operation permitted
• Mailbox bypass register for each FIFO
• Parallel Pr ogram m able Almost Full and Almost Empty
flags
• Retransmit function
• Standar d or FWFT mode user selectable
• 120-pin TQFP packaging
• Easily expandable in width and dept h
CLKA
CSA
W/RA
ENA
MBA
RT2
RST1
FFA/IRA
AFA
FS0
FS1
A
0–35
EFA/ORA
AEA
Port A
Control
Logic
FIFO1,
Mail1
Reset
Logic
Input
Register
Programmable
Flag Offset
Registers
Output
Register
Write
Pointer
Write
Pointer
Mail1
Register
1K/4K/16K
x36
Dual Ported
Memory
Status
Flag Logic
Status
Flag Logic
256/512/1K
4K/16K x36
Dual Ported
Memory
Read
Pointer
Timing
Mode
Read
Pointer
Input
Output
Register
MBF1
CLKB
Port B
Control
Register
Logic
FIFO2,
Mail2
Reset
Logic
CSB
W/RB
ENB
MBB
RT1
EFB/ORB
AEB
B
0–35
FWFT/STAN
FFB/IRB
AFB
RST2
Mail2
Register
MBF2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 28, 2000
Page 2
Pin Configuration
FWFT/STAN
RT2
A
A
A13A15A16A
14
12
27
28
29
30
31
GND
A
32
11
A
33
10
34
A
9
35
A
8
36
A
7
37
A
6
38
GND
A
39
5
40
A
4
41
A
3
42
V
CC
43
A
2
44
A
1
45
A
2
GND
GND
V
B
B
0
46
47
B
0
48
B
1
49
B
2
50
B
3
51
B
4
52
B
5
53
54
B
6
55
CC
56
B
7
57
B
8
58
B
9
59
10
60
11
64
63
62
61
GND
A18A19A20A
17
22
23
24
25
26
69
68
67
66
65
V
A23A24A25A26A
A
CC
21
22
12
13
14
15
16
17
18
19
20
21
CY7C43642
CY7C43662
CY7C43682
79
78
77
76
75
74
73
72
71
70
GND
A
A
27
28
29
11
82
81
80
V
A30A
A32A33A34A
CC
31
5
6
7
8910
86
85
84
83
35
1
234
120
GND
119
CLKA
118
ENA
117
W/RA
116
CSA
115
FFA/IRA
114
EFA/ORA
113
V
112
111
110
109
108
107
106
105
104
103
102
101
100
90
89
88
87
CC
AFA
AEA
MBF2
MBA
MRST1
Top View
FS0
GND
FS1
MRST2
MBB
TQFP
MBF1
V
CC
AEB
99
AFB
98
EFB/ORB
97
FFB/IRB
96
GND
95
CSB
94
W/RB
93
ENB
92
CLKB
91
V
CC
GND
B12B13B15V
B24B25RT1
B
B27B
26
28
B29B30B
31
GND
B32B33B34B
35
CY7C43682
CY7C43642
CY7C43662
GND
B
14
CC
B16B17GND
B18B19B20B21B
B
23
22
Page 3
CY7C43642
CY7C43662
CY7C43682
Functional Description
The CY7C436X2 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports clock fr equencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions.
The CY7C436X2 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All dat a transf ers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a
simple bidi rectional i nterfac e between microproces sors and/or
buses with synchronous contro l.
Communicat ion betw een ea ch port may b ypa ss the FIF Os vi a
two mailbox registers. The mailbox registers’ width matches
the selected P o rt B bus width. Each mailbo x registe r has a flag
(MBF1
and MBF2) to signal when new mail has been stored.
Master Reset initializes the read and write pointers to the first
location of the memory array, and selects parallel flag programming, or one of the three possible default flag offset settings, 8 , 16, o r 64. Eac h FIFO has it s ow n indep endent M aster
Reset pin, RST1
The CY7C436X2 have two modes of operation: In the CY
Standard Mode, the first word writt en to an empty FIFO is deposited into the memory array. A read operation is required to
access that word (along with all other words residing in memory). In the First-Word Fall-Through Mode (FWFT), the first
word (36-bi t wide) written to an emp ty FIFO appe ars auto matically on the output s, no read operatio n required (nev ertheless,
accessing subsequent words does necessitate a formal read
request). The state of the FWFT
operation determines the mode in use.
and RST2.
/STAN pin during FIFO
Each FIFO has a combined Empty/Output Ready Flag (EFA
ORA and EFB
(FFA
/IRA and FFB/IRB). The EF and FF func tions are selected
in the CY Standard Mode. EF
is full or not. The IR and OR functions are sele cted in the First Word F all -Through Mode . IR indicates whet her or not the FIFO
has av ail able memory locations. OR shows whether the FIFO
has data availab le for reading or not. It marks the presence of
valid data on the outputs. (See f ootnote #17.)
Each FIFO has a programmable Al m ost Empty flag (AEA
AEB
) and a programmable Almost Full flag (AFA and AFB).
AEA
and AEB indic ate when a sele cted num ber of w ords written to FIFO memory achieve a predetermined “almost empty
state.” AFA
words written t o the m emory achieve a predet ermined “almost
full sta te.” (See footnote #34.)
IRA, IRB, AFA
writes data into its array. ORA, ORB, AEA
chronized to th e port clock that reads data from its array. Programmable offset for AEA
parallel usi ng P ort A. Three def ault off set settings are also pro vided. The AEA
locations from the empty boundary and AFA
threshold can be set at 8, 16, or 64 locations from the full
boundary. All these choices are m ade using the FS0 an d FS1
inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If at any time the FIFO is not actively performing a
function, the chip will automatically power down. During the
power-down state, supply current consumption (I
minimum. Init iating a ny oper ati on (b y act iv ati ng con trol inputs )
will immediately take the device out of the power-do wn state.
The CY7C436X2 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is gr eater than 2001V, and latch -up is pre vented by the use of guard rings.
/ORB) and a combined Full/Input Ready Flag
indicates whether the memory
and
and AFB indicate when a selected number of
, and AFB are synchroni zed to the port clock that
, and AEB are syn-
, AEB, AFA, and AFB are loaded in
and AEB threshold can be set at 8, 16, or 64
and AFB
) is at a
CC
/
Selectio n Gu ide
CY7C43642/62/82
Maximum Frequency (MHz) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enabl e Hold ( ns) 0 0 0
Maximum Flag Delay (ns) 6 8 8
Active Power Supply
Current (I
Density 1K x 36 4K x 36 16K x 3 6
Package 120 TQFP 120 TQFP 120 TQFP
CC1
) (mA)
Commercial 100 100 100
Industrial 100
CY7C43642 CY7C43662 CY7C43682
-7
CY7C43642/62/82
-10
CY7C43642/62/82
-15
3
Page 4
CY7C43642
CY7C43662
CY7C43682
Pin Definitions
Signal Name Description I/O Function
A
0–35
AEA
AEB
AFA
AFB
B
0–35
/STAN B ig Endian/
FWFT
CLKA Port A Clock I CLKA is a co ntinuous clock t hat sy nchroniz es all data t ransf ers thr ough P ort A and can
CLKB Port B Clock I CLKB is a co ntinuous clock t hat sy nchroniz es all data t ransf ers thr ough P ort B and can
CSA
CSB
/ORA Port A Empty/
EFA
EFB
/ORB Port B Empty/
ENA Port A Enable I ENA must be HIGH to enab le a LOW -to-HIGH t ransi tion of CLKA to r ead or write dat a
ENB Port B Enable I ENB must be HIGH to enab le a LOW -to-HIGH t ransi tion of CLKB to r ead or write dat a
FFA
/IRA Port A Full/Input
/IRB Port B Full/Input
FFB
Port A Data I/O 36-bit bidirect ional data port for side A.
Port A Almost
Empty Flag
Port B Almost
Empty Flag
Port A Almost
Full Flag
Port B Almost
Full Flag
Port B Data I/O 36-bit bidirect ional data port for side B.
First-Word FallThrough Select
Port A Chip
Select
Port B Chip
Select
Output Ready
Flag
Output Ready
Flag
Ready Flag
Ready Flag
O Programmab le Almost Empt y flag sy nchronized to CLKA. It i s LOW when the nu mb er
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2. (See footnote #34 .)
O Programmab le Almost Empt y flag syn chronized t o CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1. (See footnote #34 .)
O Programmab le Almost Full flag synchronized to CLKA. It is LOW when the number of
empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1. (See f ootnote #34.)
O Programmab le Almost Full f lag synchronized to CLKB. It is LO W when the number of
empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2. (See f ootnote #34.)
I During Master Reset. A HIGH on FWFT
First-Wor d Fall-Through m ode. Once the timing mode has been selected, the le vel on
FWFT
/STA N m ust be static throughout devic e operation.
be asynchronous or coincident to CLKB. FFA
synchronized to the LOW-t o-HIGH transition of CLKA.
be asynchronous or coincident to CLKA. FFB
synchronized to the LOW-to-HIGH transition of CLKB.
ICSA must be LOW to enable a LOW- to HIGH transition of CLKA to read or write on
Port A. The A
ICSB must be LOW to enable a LOW- to HIGH transition of CLKB to read or write on
Port B. The B
O This is a dual-function pin. In the CY Standard Mode, the EFA
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A
able for reading. EFA
(See footnot e #17.)
O This is a dual-funct ion pin. In the CY Standard Mode, the EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B
able for reading. EFB
(See footnot e #17.)
on Port A.
on Port B.
O This is a dual-fun ction pin . In the CY Standar d Mode, the FFA function is selected . FF A
indicates whether or not t he FIFO1 me mory is full. In t he FWFT mode , the IRA function
is selected. IRA indicat es whether or not there is space av ailable f or writing to the FIFO1
memory. FFA
O This is a dual-function pin. In the CY Standard Mode, the FFB functio n is selected. FFB
indicates whether or not t he FIFO2 me mory is full. In t he FWFT mode , the IRB function
is selected. IRB indicat es whether or not there is space av ailable f or writing to the FIFO2
memory. FFB
outputs are in the high-im pedance state when CSA is HIGH.
0–35
outputs are in the high- impedance state when CSB is H IGH.
0–35
/ORA is synchronized to the LOW-to-HIGH tra nsition of CLKA.
/ORB is synchronized t o the LOW -t o-HIGH transition of CLKB.
/IRA is synchroniz ed to the LOW-to-HIGH transit ion of CLKA.
/IRB is synchronized to the LOW -to-HIGH transi tion of CLKB.
selects CY Standard mode, a LOW select s
/IRA, EFA/OR A, A FA, and AEA are all
/IRB, EFB /ORB, AFB, and AEB are all
function is selected. EFA
outputs, avail-
0–35
function is selected. EFB
outputs, avail-
0–35
4
Page 5
CY7C43642
CY7C43662
CY7C43682
Pin Definitions
Signal Name Description I/O Function
FS1 Flag Offset
FS0 Flag Offset
MBA P ort A Ma i lbox
MBB P ort B Ma i lbox
MBF1
MBF2
RT1
RT2
W/RA
RB Port B Write/
W/
(continued)
Select 1
Select 0
Select
Select
Mail1 Register
Flag
Mail2 Register
Flag
Retransmit
FIFO1
Retransmit
FIFO2
Port A Write/
Read Select
Read Select
I The LO W-to-HI GH transition of a FIFO’s reset i nput la tches the va lues of FS0 and F S1.
If either FS0 or FS1 is HIGH when a reset input goes HIGH, one of the three preset
values (8, 16, or 64) is sel ected as the offset f or the FIFO’s Almost Full and Almost
I
Empty flags. If both FIFOs are reset simul taneously and both FS0 and FS1 are LOW
when RST1 and RST2 go HIGH, the first fo ur writes to FIFO1 Almost Empty offsets f or
both FIFOs.
I A HIGH level on M BA chooses a mail box register for a Port A read or write operation.
When a read operatio n is perf ormed on Port A, a HIGH le v el on MBA select s data from
the Mail2 register for output and a LOW level selects FIFO2 out put r egister data for
output. When a write oper ati on is p erf ormed on Port A, a HIGH lev el on MBA wi ll writ e
the data into Mail1 register while a LOW level will write the data into FIFO1.
I A HIGH level on M BB chooses a mail box register for a Port B read or write operation.
When a read operatio n is perf ormed on Port B, a HIGH lev el on MBB select s data from
the Mail1 register for output and a LOW level selects FIFO1 out put r egister data for
output. When a write oper ati on is per f ormed on Port B, a HIGH l ev e l on MBB wil l write
the data into Mail2 register while a LOW level will write the data into FIFO2.
OMBF1 is set LOW by a LOW-to-HI G H transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1
HIGH by a LOW -to-HIGH transition of CLKB when a Port B read is s elected and MBB
is HIGH. MBF1
OMBF2 is set LOW by a LOW-to-HI G H transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2
HIGH by a LOW -to-HIGH transition of CLKA when a Port A read is s elected and MBA
is HIGH. MBF2
I A LO W st robe on t his pi n will r etransm it the d ata on FIFO1. Th is is achie ved by bringing
the read point er back to loca tion zero . The user will still need to perform re ad operations
to retransmit the dat a. Retransmit func tion applies to CY standard mo de only.
I A LOW strobe on this pin will retr ansmit data on FIFO2. This is achiev ed by bringing
the read point er back to loca tion zero . The user will still need to perform re ad operations
to retransmit the dat a. Retransmit func tion applies to CY standard mo de only.
I A HIGH selects a write operat ion and a LOW selects a read oper ation on P ort A f or a
LOW- to-HI GH tra nsi tion of CLKA. The A
when W/RA
I A LOW selects a write operation and a HIGH selects a read oper ation on Port B for a
LOW- to-HIGH tra nsition of CLKB. The B
when W
is set HIGH following either a Master or Partial Reset of FIFO1.
is set HIGH following either a Master or Partial Reset of FIFO2.
0–35
is HIGH.
0–35
/RB is LOW.
is LOW. MBF1 is set
is LOW. MBF2 is set
outputs are in the HIGH impedance state
outputs ar e in t he HIGH impeda nce state
5
Page 6
CY7C43642
CY7C43662
CY7C43682
Maximum Ratings
[1]
Static Discharge Voltage ............. .. ............ ............ ....>2001V
(per MIL-STD-883, Method 3015)
(Abov e which the useful life may be impaired. For user guidelines, not tested.)
Latch -U p Cu rre n t.............. .......... ......... .......... .......... . >200mA
Storage Temperature ....................................... −65°C to +150°C
Ambient Temperature with
Operating Range
Power Applied....................................................− 55°C to +125°C
Supply Voltage to Ground Pot ential..................−0.5V to +7.0V
DC Voltage Applied to Outp uts
in High Z State
DC Input Voltage
[2]
..........................................−0.5V to V
[2]
........................................−0.5V to V
CC
CC
+0.5V
+0.5V
Output C ur re n t in to O u tp u ts (LOW) ..... ......... .......... .....20 mA
Electrical Characteristics
Over the Operating Range
Parameter Description Te st Condi tions
V
V
V
V
I
IX
I
OZL
I
OZH
I
CC1
I
SB
OH
OL
IH
IL
[4]
[5]
Output HIGH Voltage VCC = 4.5V,
I
= −4.0 mA
OH
Output LOW Voltage VCC = 4.5V,
I
= 8.0 mA
OL
Input HIGH Voltage 2.0 V
Input LOW Voltage
Input Leakage Curren t V
Output OFF, High Z
Current
= Max. −10 +10 µA
CC
OE > VIH,
V
< VO< V
SS
Active Power Supply
Current
Average Standby
Current
Range
Ambient
Temperature
[3]
V
CC
Commercial 0°C to +70°C 5.0V ± 0.5V
Industrial
−40°C to +85°C
5.0V ± 0.5V
CY7C43642/62/82
2.4 V
0.5 V
CC
−0.5
−10
CC
0.8 V
+10
Com’l 100 mA
Ind 100 mA
Com’l 10 mA
Ind 10 mA
UnitMin. Max.
V
µA
[
Capacitance
]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Operating V
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
5. All inputs = V
6. Tested initially and after any design or process changes that may affect these parameters.
Range for -7 speed is 5.0V ± 0.25V.
CC
– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
CC
Input Capacit ance TA = 25°C, f = 1 MHz,
V
= 3.3V
Output Capacitance 8 pF
CC
4 pF
6
Page 7
AC Test Loads and Waveforms (-1 0 & -15)
R1=1.1k
5V
OUTPUT
INCLUDING
C
=30 pF
L
JIG AND
SCOPE
Ω
R2=680
Ω
AC Test Loads and Waveforms (-7)
3.0V
GND
≤
3ns
ALL INPUT PULSES
90%
10%
CY7C43642
CY7C43662
CY7C43682
90%
10%
3
ns
≤
50Ω
I/O
Switching Characteristics
=
Ω
Over the Operating Range
Parameter Description
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
RSTS
t
FSS
t
SDS
t
SENS
t
FWS
t
DH
Clock Frequency, CLKA or CLKB 133 100 67 MHz
Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
Pulse Duration, CLKA or CLKB LO W 3.5 4 6 ns
Set-Up Time, A
CLKB↑
before CLKA ↑ and B
0–35
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB
Set-Up Time, RST1 or RST2 LOW before CLKA↑ or
CLKB↑
, W/RB, ENB, and MBB bef or e CLK B↑
[7]
Set-Up Time, FS0 an d FS1 befor e RST1 and RST2
HIGH
Set-U p Tim e, F S0 b efor e CLK A ↑ 3 4 5 ns
Set-U p Tim e, F S1 b efor e CLK A ↑ 3 4 5 ns
Set-Up Time, FWFT bef ore CLKA↑ 0 0 0 ns
Hold Time, A
after CLKA↑ and B
0–35
CLKB↑
t
ENH
t
RSTH
Hold Time, CSA, W/RA, ENA, and MBA after
CLKA↑; CS B
Hold Time, RST1 or RST2, LOW after CLKA↑ or
CLKB↑
, W/RB, ENB, and MBB after CLKB↑
[7]
VCC/2
0–35
0–35
after
before
ALL INPUT PULSES
3.0V
GND
3ns
≤
CY7C43642/
62/82
-7
90%
10%
CY7C43642/
62/82
-10
90%
10%
≤
CY7C43642/
3
ns
62/82
-15
3 4 5 ns
3 4 5 ns
2.5 4 5 ns
6 7 7.5 ns
0 0 0 ns
0 0 0 ns
1 2 4 ns
UnitMin. Max. Min. Max. Min. Max.
7
Page 8
CY7C43642
CY7C43662
CY7C43682
Switching Characteristics
Over the Operating Range (continued)
CY7C43642/
62/82
-7
CY7C43642/
62/82
-10
CY7C43642/
62/82
-15
Parameter Description
t
FSH
Hold Time, FS0 and FS1 after RST1 and RST2
1 1 2 ns
HIGH
t
SDH
t
SENH
t
SPH
t
SKEW1
t
SKEW2
t
A
t
WFF
t
REF
t
PAE
t
PAF
t
PMF
Hold Time, FS0 after CLKA↑ 0 0 0 ns
Hold Time, FS1 after CLKA↑ 0 0 0 ns
Hold Time, FS1 HIGH after RST1 and RST2 HIGH 0 1 2 ns
[7]
Skew Ti m e betwe en CLK A ↑ and CLKB↑ for EFA/
ORA, EFB
[7]
Skew Ti m e betwe en CLK A ↑ and CLKB↑ for AEA,
AEB
Access Time, CLKA↑ to A
B
0–35
/ORB, FFA/IRA, and F F B/IRB
, AF A , AFB
0–35
and CLKB↑ to
Propagation Delay Time, CLKA↑ to FFA/IRA and
CLKB↑ to FFB
/IRB
Propagation Delay Time, CLKA↑ to EFA/ORA and
CLKB↑ to EFB
/ORB
Propagation Delay Time, CLKA↑ to AEA and
5 5 7.5 ns
7 8 12 ns
1 6 1 8 3 10 ns
1 6 1 8 2 8 ns
1 6 1 8 1 8 ns
1 6 1 8 1 8 ns
CLKB↑ to AEB
Propagation Dela y Time, CLKA↑ to AF A and CLKB↑
1 6 1 8 1 8 ns
to AFB
Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2
HIGH and CLKB↑ to MBF2 LOW or MBF1
0 6 0 8 0 12 ns
HIGH
t
PMR
t
MDV
t
RSF
Propagation Delay Time, CLKA↑ to B
CLKB↑ to A
0–35
[9]
Propagation Delay Time, MBA to A
MBB to B
0–35
valid
Propagation De lay Ti me, RST1 LOW to AEB LOW,
AFA
HIGH, FFA/IRA Low, EFB/ORB LOW, and
MBF1
HIGH and RST2 LOW to AEA LOW, AFB
HIGH, FFB
/IRB Low, EFA/ORA LOW, and MBF2
0–35
valid and
0–35
[8]
and
1 7 2 11 3 12 ns
1 6 2 9 3 11 ns
1 6 1 10 1 15 ns
HIGH
t
EN
t
DIS
t
PRT
t
RTR
Notes:
7. Ske w time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
8. Writing data to the Mail1 register when the B
9. Writing data to the Mail2 register when the A
10. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Enable Time, CSA or W/RA LOW to A
and CSB
LOW and W/RB HIGH to B
Disable Time, CSA or W/RA HIGH to A
Impedance and CSB
HIGH or W/RB LOW to B
at High Impedance
0–35
0–35
0–35
Active
Active
at High
0–35
1 6 2 8 2 10 ns
1 5 1 6 1 8 ns
Retransmit Pulse Width 60 60 60 ns
Retransmit Recovery Time 90 90 90 ns
outputs are active and MBB is HIGH.
0–35
outputs are active and MBA is HIGH.
0–35
UnitMin. Max. Min. Max. Min. Max.
8
Page 9
Switching Waveforms
CY7C43642
CY7C43662
CY7C43682
FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
CLKB
t
RST1
RSTS
FWFT/STAN
FS1, FS0
t
RSF
FFA
/IRA
t
EFB
/ORB
RSF
t
RSF
AEB
t
RSF
AFA
t
RSF
MBF1
[11]
t
FSS
t
RSTH
t
FSH
t
FWS
t
WFF
Note:
11. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
9
Page 10
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
Programming of the Almost- Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
(continued)
[12]
CLKA
RST1
, RST2
t
t
FSH
FSS
FS1, FS0
t
FFA/
IRA
WFF
t
ENStENH
ENA
t
A
DS
0−35
AFA Offset (Y1)
t
DH
AEB Offset (X1)
AFB Offset (Y2)
AEA Offset (X2)
CLKB
FFB
/IRB
t
SKEW1
[13]
First Word to FIFO1
t
WFF
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
t
CLK
t
CLKH
t
CLKL
CLKA
FFA/
IRA
HIGH
t
ENS
t
ENH
CSA
t
W/RA
ENS
t
ENStENH
t
ENH
MBA
ENA
A
0–35
Notes:
12. CSA
13. t
14. Written to FIFO1.
=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
SKEW1
edge of CLKA and rising edge of CLKB is less than t
t
ENS
t
DS
W1
SKEW1
t
ENH
t
DH
[14]
, then FFB/IRB may transition HIGH one cycle later than shown.
t
ENS
W2
[14]
t
ENH
t
ENS
t
ENH
10
Page 11
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
Port B Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
t
CLK
t
CLKH
t
CLKL
CLKB
/IRB
FFB
HIGH
t
ENS
t
ENH
CSB
t
ENS
t
ENH
W/RB
t
t
ENH
ENS
MBB
ENB
B
0−35
t
ENS
t
DS
W1
[15]
t
ENH
t
DH
t
ENS
Port B Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
W2
[17]
[15]
t
ENH
t
ENS
t
ENH
t
CLK
t
CLKH
t
CLKL
CLKB
EFB
/ORB
HIGH
CSB
W/RB
MBB
t
ENS
ENB
t
B
0–35
t
EN
(Standard Mode)
t
OR
B
0–35
EN
(FWFT Mode)
Notes:
15. Written to FIFO2.
16. Read from FIFO1.
17. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the
boundary flag (e.g., in bursts), use CY standard mode.
MDV
Previous Data
t
MDV
W1
[16]
t
ENH
t
A
W2
t
W2
ENS
[16]
[16]
t
ENH
t
A
t
A
t
ENS
No Operation
[16]
W2
[16]
W3
t
ENH
t
DIS
t
DIS
11
Page 12
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
t
CLK
t
CLKH
t
CLKL
CLKA
EFA
/ORA
HIGH
CSA
W/RA
MBA
ENA
A
0−35
(Standard Mode)
OR
A
0−35
(FWFT Mode)
t
ENS
t
t
EN
t
EN
MDV
Previous Data
t
MDV
W1
[18]
t
ENH
t
A
W2
W2
t
ENS
[18]
[18]
[17]
t
ENH
t
A
t
A
t
ENS
No Operation
[18]
W2
[18]
W3
t
ENH
t
DIS
t
DIS
Note:
18. Read From FIFO2.
12
Page 13
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
ORB Flag Timing and First Data Wor d Fall Through when FIFO1 is Empty (FWFT Mode)
t
CLK
t
t
CLKH
CLKL
CLKA
CSA
W/RA
LOW
HIGH
t
ENS
t
ENH
MBA
t
ENS
t
ENH
ENA
FFA
A
0–35
CLKB
EFB
/IRA
/ORB
HIGH
FIFO1 Empty
t
t
DS
DH
W1
[19]
t
t
t
SKEW1
CLKH
t
CLK
CLKL
t
REF
t
[17]
REF
CSB
W/RB
MBB
LOW
HIGH
LOW
ENB
t
A
B
0–35
Note:
19. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
SKEW1
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
load of the first word to the output register may occur one CLKB cycle later than shown.
Old Data in FIFO1 Output Register
t
ENS
t
ENH
W1
, then the transition of ORB HIGH and
SKEW1
13
Page 14
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
EFB Flag Timing and First Data Read F all Through when FIFO1 is
Empty (CY Standard Mode)
CLKA
CSA
W/RA
LOW
HIGH
t
ENS
t
ENH
MBA
t
ENS
t
ENH
ENA
/IRA
FFA
A
0–35
HIGH
t
t
DS
DH
W1
[20]
t
t
SKEW1
CLKH
t
CLKL
CLKB
t
REF
EFB
/ORB
FIFO1 Empty
t
CLK
t
CLKH
t
CLK
t
CLKL
t
REF
CSB
W/RB
MBB
LOW
HIGH
LOW
ENB
B
0–35
Note:
20. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between
SKEW1
the rising CLKA edge and rising CLKB edge is less than t
t
ENS
, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
SKEW1
t
ENH
t
A
W1
14
Page 15
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
ORA Flag Timing and First Data Word F all Through when FIFO2 is Empty
(FWFT Mode)
[21]
t
CLK
t
CLKHtCLKL
CLKB
CSB
W/RB
LOW
LOW
t
ENS
t
ENH
MBB
t
ENS
t
ENH
ENB
FFB
B
0–35
/IRB
HIGH
t
t
DH
DS
W1
[22]
t
SKEW1
t
CLKHtCLKL
CLKA
t
CLK
EFA
/ORA
FIFO2 Empty
t
REF
[17]
t
REF
CSA
W/RA
MBA
LOW
LOW
LOW
t
ENS
ENA
t
A
A
0–35
Notes:
21. t
22. t
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
SKEW1
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than t
load of the first word to the output register may occur one CLKA cycle later than shown.
Old Data in FIFO2 Output Register
t
ENH
W1
, then the transition of ORA HIGH and
SKEW1
15
Page 16
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
t
CLK
t
CLKHtCLKL
CLKB
CSB
W/RB
LOW
LOW
t
ENS
t
ENH
MBB
t
ENS
t
ENH
ENB
FFB
B
0–35
/IRB
HIGH
t
t
DS
DH
W1
[23]
t
SKEW1
t
CLKHtCLKL
CLKA
EFA
/ORA
FIFO2 Empty
t
t
CLK
REF
t
REF
CSA
W/RA
MBA
LOW
LOW
LOW
ENA
A
0–35
Note:
23. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the
SKEW1
rising CLKB edge and rising CLKA edge is less than t
t
ENS
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
SKEW1
t
ENH
t
A
W1
16
Page 17
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
t
CLK
t
t
CLKH
CLKL
CLKB
CSB
W/RB
MBB
LOW
HIGH
LOW
t
ENS
t
ENH
ENB
EFB
B
/ORB
0–35
HIGH
t
A
Previous Word in FIFO1 Output Register
t
SKEW1
Next Word From FIFO1
[24]
t
CLKH
t
CLKL
CLKA
t
WFF
FFA
/IRA
FIFO1 Full
t
CLK
t
WFF
CSA
W/RA
LOW
HIGH
MBA
ENA
A
0–35
Note:
24. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
SKEW1
rising CLKB edge and rising CLKA edge is less than t
t
t
ENS
ENH
To FIFO1
t
ENH
t
DH
t
ENS
t
DS
, then IRA may transition HIGH one CLKA cycle later than shown.
SKEW1
17
Page 18
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
FFA Flag Timing and First Available Write when FIFO1 is Full (CY St andard Mode)
t
CLK
t
t
CLKH
CLKL
CLKB
CSB
W/RB
MBB
LOW
HIGH
LOW
t
ENS
t
ENH
ENB
/ORB
EFB
B
0–35
HIGH
t
A
Previous Word in FIFO1 Output Register
t
SKEW1
Next Word From FIFO1
[25]
t
CLKH
t
CLKL
CLKA
t
WFF
FFA
/IRA
FIFO1 Full
t
CLK
t
WFF
CSA
W/RA
LOW
HIGH
MBA
ENA
A
0−35
Note:
25. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the
SKEW1
rising CLKB edge and rising CLKA edge is less than t
t
t
ENH
ENS
t
ENS
t
DS
, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
SKEW1
t
ENH
t
DH
18
Page 19
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
IRB Flag Timing and First Avai lable Write when FIFO2 is Full (FWFT Mode)
t
CLK
t
t
CLKL
CLKH
CLKA
CSA
W/RA
MBA
LOW
LOW
LOW
t
ENS
t
ENH
ENA
EFA
A
0–35
/ORA
HIGH
t
A
Previo us Word i n FIFO2 Out put Register
t
SKEW1
Next Word From FIFO2
[26]
t
CLKH
t
CLKL
CLKB
t
FFB
/IRB
FIFO2 Full
t
CLK
t
WFF
WFF
CSB
W/RB
LOW
LOW
MBB
ENB
B
0–35
Note:
26. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the
SKEW1
rising CLKA edge and rising CLKB edge is less than t
To FIFO2
t
t
ENH
ENH
t
DH
t
ENS
t
ENS
t
DS
, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
SKEW1
19
Page 20
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)
t
CLK
t
t
CLKH
CLKL
CLKA
CSA
W/RA
MBA
LOW
LOW
LOW
t
ENS
t
ENH
ENA
EFA
A
0–35
/ORA
HIGH
t
A
Previ o us Word in FIFO12 Outpu t Register
t
SKEW1
Next Word From FIFO2
[27]
t
CLKH
t
CLKL
CLKB
t
WFF
FFB
/IRB
FIFO2 Full
t
CLK
t
WFF
CSB
W/RB
LOW
LOW
MBB
ENB
B
0–35
Note:
27. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the
SKEW1
rising CLKA edge and rising CLKB edge is less than t
t
ENS
t
ENS
t
DS
, then the transition of FFB HIGH may occur one CLKB cycle later than shown.
SKEW1
To FIFO2
t
t
ENH
ENH
t
DH
20
Page 21
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
Timing for AEB
CLKA
ENA
CLKB
AEB
ENB
Timing for AEA
CLKB
ENB
CLKA
AEA
ENA
when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
X1 Word in FIFO1
when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
X2 Word in FIFO2
(continued)
t
ENS
t
ENS
t
ENH
t
SKEW2
t
ENH
t
SKEW2
[30]
[33]
t
PAE
t
PAE
[28, 29,34 ]
(X1+1)Words in FIFO1
t
ENS
[31, 32,34 ]
(X2+1) Wo rd s in FIFO2
t
ENS
t
PAE
t
ENH
t
PAE
t
ENH
Notes:
28. FIFO1 Write (CSA
read from the FIFO.
29. If Port B size is word or byte, AEB
30. t
31. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Read (CSA = LOW , W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been
32. If Port B size is word or byte, t
33. t
34. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 3 clock cycles for flag assertion and deassertion. Refer to
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
SKEW2
the rising CLKA edge and rising CLKB edge is less than t
read from the FIFO.
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
SKEW2
the rising CLKB edge and rising CLKA edge is less than t
“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
= LOW, W/RA = LOW, MBA = LOW), FIFO1 Read (CSB = LOW , W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
is set LOW by the last word or byte read from FIFO1, respectively.
, then AEB may transition HIGH one CLKB cycle later than shown.
SKEW2
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
SKEW2
, then AEA may transition HIGH one CLKA cycle later than shown.
SKEW2
21
Page 22
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
[37]
t
SKEW2
CLKA
t
ENS
t
ENH
ENA
t
AFA
[D–(Y1+1)] Words in FIFO 1
PAF
(D–Y1)Words in FIFO1
CLKB
t
ENB
Timing for AFB
CLKB
ENB
t
when FIFO2 is Almost Full (CY Standard and FWFT Modes)
t
t
ENS
ENH
ENS
ENH
t
SKEW2
[38]
[32,34, 35, 36]
[31,34, 36]
t
PAF
t
AFB
[D–(Y2+1)] Words in FIFO2
PAF
(D–Y2)Words in FIFO2
CLKA
t
t
ENA
Notes:
35. FIFO1 Write (CSA
been read from the FIFO.
36. D = Maximum FIFO Depth 1K for the CY7C43642, 4K for the CY7C43662, and 16K for the CY7C43682.
37. t
38. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
SKEW2
rising CLKA edge and rising CLKB edge is less than t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between
SKEW2
the rising CLKB edge and rising CLKA edge is less than t
= LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has
ENS
, then AFA may transition HIGH one CLKB cycle later than shown.
SKEW2
, then AFB may transition HIGH one CLKA cycle later than shown.
SKEW2
ENH
t
PAF
22
Page 23
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
Timing for Mail1 Register and MBF1
CLKA
CSA
t
W/RA
MBA
ENA
A
0–35
CLKB
MBF1
CSB
Flag (CY Standard and FWFT Modes)
ENS
t
ENS
t
t
DS
t
ENS
ENS
W1
t
t
ENH
ENH
t
ENH
t
ENH
t
DH
t
PMF
t
PMF
W/RB
MBB
ENB
B
0-35
t
EN
FIFO1 Output Register
t
MDV
t
PMR
t
ENS
W1 (Remains valid in Mail1 Register after read)
t
ENH
t
DIS
23
Page 24
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
(continued)
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
CLKB
CSB
t
ENS
t
ENS
t
ENH
t
ENH
W/RB
t
ENS
t
ENH
MBB
t
ENS
t
ENH
ENB
B
0–35
t
W1
DS
t
DH
CLKA
t
PMF
MBF2
CSA
t
PMF
W/RA
MBA
t
ENS
t
ENH
ENA
t
MDV
t
PMR
W1 (Remains valid in Mail2 Register after read)
A
0−35
FIFO1 Retransmit Timing
t
EN
FIFO2 Output Register
[39, 40, 41 , 42]
RT1
t
PRT
t
RTR
ENB
EFB/FFA
Notes:
39. Retransmit is performed in the same manner for FIFO2.
40. Clocks are free-running in this case. CY standard mode only.
41. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
42. For the AF
& AE flags, two clock cycles are necessary after t
to update the se flags .
RTR
RTR
t
DIS
.
24
Page 25
CY7C43642
CY7C43662
CY7C43682
Signal Description
Reset (RS T 1 , R ST2)
Each of the two FIFO memories of the CY7C436X2 undergoes
a complete re set b y taking it s associat ed Master Reset (RST1
RST2
) input LOW f or at le ast fo ur P ort A clock (CLKA) and four
Po rt B clock (CLKB) LO W- to-HIGH tr ansitions . The Master Reset inp ut s ca n swit ch asy nc hr on ous ly t o th e cl ocks. A Ma ste r
Reset initial izes the int ernal read and write pointer s and for ces
the Full/Input Ready flag (FF A
Output Ready flag (EFA
Empty flag (AEA
AFB
) HIGH. A Master Reset also forces the Mailbox flag
(MBF1
, MBF2) of the parallel mailbox register HIGH. After a
, AEB) LOW, and the Almost Full flag (AFA,
Master Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation. A Master
Reset must be performed on the FIFO after power-up, before
data is written to its memory.
A LOW -to-HIGH transi tion on a FIFO reset (RST1
latches the values of the Flag select (FS0, FS1) for choosing
the Almost Full and Almos t Empty offset prog rammi ng method
(see Almost Empty and Almost Full flag offset programming
below).
First-Word Fall-Through (FWFT
After M aster R eset, the FWFT sele ct fu nctio n is ac tiv e, permitting a choice between two possible timing modes: CY
Standard Mode or First-Word Fall-Through (FWFT) Mode.
Once the Master Reset (RST1
on the FWFT
/STAN input during the next LOW-to-HIGH transition of CLKA ( for FIFO 1) and CLKB (f or FIFO 2) will select CY
Standard Mode. This mode uses the Empty Flag function
(EFA
, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA
, FFB) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested using a formal read operation.
Once the Master Reset (RST1
on the FWFT
/STAN input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
FWFT Mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at
the data outputs (A
0–35
uses the Input Ready function (IRA, IRB) to indicate whether
or not the FIFO memory has any free space for writi ng. In the
FWFT mode, the first word written to an empty FIFO goes
directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read
operation.
Following Master Reset, the level applied to the FWFT
input to choose the desired timing mode must remain static
throughout th e FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X2 are used to hold the offset
values f or the Almos t Empty and Almost Full flags . The P ort B
Almost Empty flag (AEB
Port A Almost Empty flag (AEA
The Port A Almost Full flag (AFA
and the Port B Almost Full flag (AFB
Y2. The index of each register name corresponds with preset
/IRA, FFB/IRB) LO W , the Empty/
/ORA, EFB/ORB) LOW, the Almost
, RST2) input
/STAN)
, RST2) input is HIGH, a HIGH
, RST2) input is HIGH, a LOW
or B
). (See footnote #17) It also
0–35
/STD
) offset register is labeled X1 and the
) offset register is labeled X2.
) offset register is la beled Y1
) offset register is labe led
values during the reset of a FIFO, programmed in parallel using the FIFO’s Port A data inputs (see Tabl e 1).
To program the X1, X2, Y1, and Y2 registers from P ort A, perform a Master Reset on both FIFOs simultaneously with FS0
and FS1 LOW during the LOW -to-HIGH tran sition of RST1
,
RST2
. After this reset is complete, the first four writes to FIFO1
do not store data in RAM but load the offset registers in the
order Y1, X1, Y2, X2. The P ort A data inputs us ed by the of fset
registers are (A
0–9
), (A
0–11
), or (A
), for the CY7C436X2,
0–13
respectiv ely. The highest numbered input is used as th e mos t
significant bit of the binary number in each case. Valid programming v alues fo r th e register s r ange from 0 to 1023 f or the
CY7C43642; 0 to 4095 for the CY7C43662; 0 to 16383 for the
CY7C43682. (See footnote #34) After all the offset registers
are programmed from Port A, the Port B Full/Input Ready
(FFB
/IRB) is set HIGH and both FIFOs begin normal opera-
tion.
FS0 and FS1 f unction the sam e way in both CY Standard and
FWFT modes.
FIFO Write/Read Operation
The state of the Po rt A data (A
A Chip Select (CSA
The A
CSA
lines are in the high-impedance state when either
0–35
or W/RA is HIGH. The A
when both CSA
) and Port A Write/Read Select (W/RA).
and W/RA are LOW.
Data is loaded into FIFO1 from the A
HIGH transition of CLKA when CSA
ENA is HIGH, MBA is LOW, and FF A
from FIFO2 to the A
of CLKA when CSA
is LOW, and EFA
outputs by a LOW-to-HIGH transition
0–35
is LOW, W/RA is LOW, ENA is HIGH, MBA
/ORA is HIGH (see Table 2). FIFO reads and
) lines is controlled by Port
0–35
lines are active outputs
0–35
inputs on a LOW -to-
0–35
is LOW, W/RA is HIGH,
/IRA is HIGH. Data is read
writes on Port A are independent of any concurrent Port B
operation.
The Port B contr ol signals are id enti cal to those of Port A with
the exception that the Port B Write/Read select (W
inverse of the Port A Write/Read Select (W/RA
the Port B data (B
Select (CSB
) and P ort B Write/ Read Sel ect (W /RB).The B
) lines is controlled by the Port B Chip
0–35
). The state of
lines are in the high-impedance state when either CSB is
HIGH or W
when CSB
Data is loaded into FIFO2 from the B
HIGH transition of CLKB when CSB
ENB is HIGH, MBB is LOW , and FFB
from FIFO1 to the B
of CLKB when CSB
MBB is LOW, and EFB
/RB is LOW. The B
is LOW and W/RB is HIGH .
lines are active outputs
0–35
0–35
/IRB is HIGH. Data is read
outputs by a LOW-to-HIGH transition
0–35
is LOW, W/RB is HIGH, ENB is HIGH,
/ORB is HIGH (see Table 3). FIFO reads
inputs on a LOW -to-
is LOW, W/R B is LOW,
and writes on Port B are independent of any concurrent Por t
A operation.
The set-up and hold t ime constraints to the port clocks for the
port Chip Selects and Write/Read Selects are only f or enabli ng
write and read operations and are not related to high-impedance control of the data o utputs. If a port enable is LOW during
a clock cycle, the port’s Chip Select and Write/Read select
may change states during the set-up and hold ti me window of
the cy cle.
When operating the FIFO in FWFT Mode and the Output
Ready flag is LOW, the next wor d written is automatic ally sent
to the FIFO’s output regi ster by the LOW-t o-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data re-
and
/RB) is the
0–35
25
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CY7C43642
CY7C43662
CY7C43682
siding in the FIFO’s mem ory arra y i s cloc ked to the ou tpu t register only when a r ead is s elect ed us ing th e port’s Chip Select,
Write/Read Select, Enable, and Mailbox select.
When operat ing t he FIFO i n CY Standard Mode , rega rdless of
whether the Empty Flag is LOW or HIGH, data residing in th e
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select, Write/
Read Select, Enab le, and Mailbox Select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least
two fli p-flop st age s . This is don e to i mpro ve fl ag-si gnal r elia bility by reducing the probability of the metastable events when
CLKA and CLKB operate asynchr onously to one another . EF A
ORA, AEA
EFB
CLKB. Table 4 and Ta ble 5 show the relationship of each port
flag to FIFO1 and FIFO2.
Empty/Output Ready Flags (EFA
These are dual-purpose flags. In the FWFT Mode, the Output
Ready (ORA, ORB) function is selected. When the OutputReady flag is HIGH, new data is present in the FIFO output
register. When the Output Ready flag is LOW, the previous
data word is pr esent in the FIFO outp ut regist er and attempte d
FIFO reads are ignor ed. (See footnote #17)
In the CY Standard Mode , the Empty Fl ag (EF A
is selected. Wh en the Empty Flag i s HIGH, data is av a ilab le i n
the FIFO’s RAM memory for reading to the output register.
When the Empty Flag is LOW, the previous data word is
present in the FIFO outp ut regi ster and at tempted FI FO reads
are ignored.
The Empty/Output Rea dy flag of a FIFO is sync hronized to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer compar ator that indicate s when
the FIFO SRAM status is empty, empty+1, or empty+2.
In FWFT Mode, from the time a w ord is writte n to a FIFO , it ca n
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three cycles hav e not elaps ed since the t ime the wor d was written. Th e
Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH tr ansition of the synchronizing clock occurs, simultaneousl y f orc ing the Output Ready flag HIGH and shiftin g
the word to the FIFO output register.
In the CY Standard Mode , from the time a word is writt en to a
FIFO, the Empty flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty flag
synchronizing clock. Therefore, an Empty Flag is LOW if a
word in memo ry is the next dat a to be sent t o the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty flag HIGH; only then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizi ng clock begins the fir st synchroni zation cycle of a
, FFA/IRA, and AFA are synchronized to CLKA.
/ORB, AEB, FFB/IRB, and AFB are synchronized to
/ORA, EFB/ORB)
, EFB) function
write if the clock transition occurs at time t
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FFA
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IRA and IRB) functio n is selected. In CY Standard Mode, the
Full Flag (FFA
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FIFO are ign ored.
The Full/Input Ready f lag of a FIFO is sync hronized to the port
clock that writes data to its arra y. For both FWFT and CY Stan-
/
dard modes, each time a word is written to a FIFO, its write
pointer is incr ement ed. The st ate machin e that co ntrol s a Full /
Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is full,
full–1, or full–2. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next memory write location has been
read. The second LOW-to-HIGH transition on the Full/Input
Ready flag synchronizing clock after the read sets the Full/
Input Ready flag HIGH.
A LOW- to-HIGH tr ansi tion on a Ful l/Input Ready flag sync hro nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time t
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AEA
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The Almost Empty state is defined by the contents of register
X1 for AEB
ed with preset values during a FIFO reset, programmed from
Port A, or programmed serially (see Almost Empty flag and
Almost Full flag offset progr ammi ng abov e) . An Almost Empty
flag is LOW when its FIFO contains X or less words and is
HIGH when its FIFO contains (X+1) or more words . (See f oot note #34)
Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost
Empty flag to reflect the new level of fill. Therefore, the Almost
Full flag of a FIFO containing (X+1) or more words remains
LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to the (X+1) l ev el. A LO W- to-HIGH tr ansition of an
Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t
the write that fills the FI FO to (X+1) word s. Otherwise , the subsequent synchronizing clock cycle may be the first synchronization cycle.
and FFB) function is selected. For both timing
and regist er X2 for AEA. These regis ters ar e load-
/IRA, FFB/IRB)
SKEW1
, AEB)
SKEW1
or greater after the
or greater after
SKEW2
or grea ter
26
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CY7C43642
CY7C43662
CY7C43682
Almost Full Flags (AFA
, AFB)
The Almost Ful l flag of a FI FO is sy nchroniz ed to the po rt clock
that writes data to it s arr a y. The state machine that c ontrol s an
Almost Full flag moni tors a write pointer and r ead pointer comparator that indicates when the FIFO SRAM status is almost
full, alm ost full–1, or almost full–2. The Almost Full state is
defined by the contents of register Y1 for AFA
for AFB
. These registe rs are loaded with pr eset values durin g
and register Y2
a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024–Y),
(4096–Y), or (16384–Y) for the CY7C436X2 respectively. An
Almost Full flag is HIGH whe n the n umber of wor ds in i ts FI FO
is less than or equal to [1024–(Y+1)], [4 096–(Y+1)], or [16384–
(Y+1)], for the CY7C436X2 respectively. (See footnote #34)
Two LOW-to-HIGH transitions of the Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [1024/4096 /16384–(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizi ng clo c k aft er the FIFO read th at redu ces t he num ber of words in memory to [1024/40 96/16384–(Y+1)] . A LOWto-HIGH transition of an Almost Full flag synchronizing clock
begins the f irst sync hroniza tion cycle i f it occ urs at time t
or greater after the read that reduces the number of words in
SKEW2
memory to [1024/4096/16384–(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle.
Mailbox Registers
Each FIFO has a 36-b it b yp ass reg ister t o pass c ommand an d
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation . The usab le width of both the Mai l1 and Mail 2 registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A
Mail1 Register whe n a Port A write is selected b y CSA
data to the
0−35
, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
emplo ys data lines A
bits, then the usabl e width of the Mail 1 Register employs data
lines A
. (In this case, A
0−17
. If the selected Port A bus size is 18
0−35
are don’t care inputs.) If the
18−35
selected Port A bus size is 9 bits, then the usable width of the
Mail1 Register emp loys data lines A
don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B
Mail2 Register when a Port B write is select ed by CSB
. (In this c ase, A
0−8
0–35
are
9−35
data to the
, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
employs data l ines B
bits, then the usable width of the Mail2 Register emplo ys data
lines B
. (In this ca se, B
0–17
. If the selected Port B bus size is 18
0–35
are don’t care inputs.) If the
18–35
selected Port B bus size is 9 bits , then the usable width of the
Mail2 Register emplo ys data lines B
don’t care inputs.)
. (In this case, B
0−8
9−35
are
Writing data to a mail register sets its corresponding flag
(MBF1
or MBF2) LOW. Attempted writes to a mail regist er are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register flag (MBF1
) is set HIGH by a LOW-toHIGH transition on CLKB when a Port B read is selected by
CSB
, W/RB, and ENB with MBB HIGH. For a 36-bit bus size,
36 bits of mailbox data are placed on B
size, 18 bits of mail bo x dat a ar e plac ed on B
B
are indeterminate.) For a 9-bit bus size, 9 bits of mail-
18–35
box data are placed on B
minate.)
The Mail2 Register flag (MBF2
. (In this case, B
0–8
) is set HIGH by a LOW-to-
. For an 18-bit bus
0–35
. (In this case,
0–17
are indeter-
9–35
HIGH transition on CLKA when a Port A read is selected by
CSA
, W/RA, and ENA with MBA HIGH.
For a 36-bi t b us s ize , 36 bi ts of mai lbo x data a re pla ced on A
. For an 18-bit bus size, 18 bits of mailbox data are placed
35
on A
bus size, 9 bits of mailbox data are placed on A
case, A
. (In this case, A
0–17
are indeterminate.)
9–35
are indeterminate.) For a 9-bit
18–35
. (In th is
0–8
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Retransmit (RT1
, RT2)
The retransmit f eat ure is benefi cial when tra nsferring pac k ets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit function applies to CY standar d mo de only.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have occurred and at least o ne wor d has be en read si nce the l ast rese t
cycle. A LOW pulse on RT1
, (RT2) resets the internal read
pointer to the first physical location of the FIFO. CLKA and
CLKB may be free running b ut ENB (ENA) must be deasserted
during and t
after the retransmit pulse. With every valid
RTR
read cycle after retransmit, previously accessed data is read
and the read poi nter i s incr emented u ntil it i s equal to th e write
pointer . Flags are go verned by the relat ive locat ions of the read
and write pointers and are updated during a retransmit cycle.
Data written to the FIFO after activation of RT1
, (RT2) are
transmitt ed also.
0–
27
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CY7C43642
CY7C43662
CY7C43682
Table 1. Flag Prog ramm ing
FS1 FS0 RST1 RST2 X1 and Y1 Registers
H H
H H X
H L
H L X
L H
L H X
L L
[34]
↑
↑
↑
↑ ↑
[43]
X2 and Y2 Registers
X 64 X
↑
X 64
X 16 X
↑
X 16
X 8 X
↑
X 8
Programming via Port A Programming vi a Port A
Table 2. Port A Enable Functi on
CSA
W/RA ENA MBA CLKA A
Outputs Port Function
0–35
H X X X X In high-impedance state None
L H L X X In high-impedance state None
LHHL↑ In high-impedance state FIFO1 write
LHHH↑ In high-impedance state Mail1 write
L L L L X Active, FIFO2 output register None
LL HL↑ Active, FIFO2 output register FIFO2 read
L L L H X Active, Mail2 register None
LL HH↑ Active, Mail2 register Mail2 read (set MBF2
[44]
HIGH)
Table 3. Port B Enable Functi on
CSB
W/RB ENB MBB CLKB B
Outputs Port Function
0–35
H X X X X In high-impedance state None
L L L X X In high-impedance state None
LLHL↑ In high-impedance state FIFO2 write
LL HH↑ In high-impedance state Mail2 write
L H L L X Active, FIFO1 output register None
LH HL↑ Active, FIFO1 output register FIFO1 read
L H L H X Active, Mail1 register None
LH HH↑ Active, Mail1 register Mail1 read (set MBF1
Notes:
43. X1 register holds the offset for AEB
44. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
; Y1 register holds the offset for AFA.
HIGH)
28
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CY7C43642
CY7C43662
CY7C43682
Table 4. FIFO1 Flag Operation (CY Standard and FWFT modes)
Number of Words in FIFO Memory
[45, 46, 47 , 48]
[34]
Synchronized to CLKB Synchronized to CLKA
CY7C43642 CY7C43662 CY7C43682 EFB/ORB AEB AFA FFA/IRA
0 0 0 L L H H
1 TO X1 1 TO X1 1 TO X1 H L H H
(X1+1) to [1024–
(Y1+1)]
(X1+1) to [4096–
(Y1+1)]
(X1+1) to [16384–
(Y1+1)]
H H H H
(1024–Y1) to 1023 (4096–Y1) to 4095 (16384–Y1) to 16383 H H L H
1024 4096 16384 H H L L
Table 5. FIFO2 Flag Operation (CY Standard and FWFT modes)
Number of Words in FIFO Memory
[46, 47, 48 , 49]
CY7C43642 CY7C43662 CY7C43682 EFA
[34]
Synchronized to CLKA Synchronized to CLKB
/ORA AEA AFB FFB/IRB
00 0LLHH
1 TO X2 1 TO X2 1 TO X2 H L H H
(X2+1) to [1024–
(Y2+1)]
(X2+1) to [4096–
(Y2+1)]
(X2+1) to [16384–
(Y2+)1]
HHHH
(1024–Y2) to 1023 (4096–Y2) to 4095 (16384–Y2) to 16383 H H L H
1024 4096 16384 H H L L
Notes:
45. X1 is the Almost Empty offset for FIFO1 used by AEB
or port A programming.
46. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
47. Data in the output register does not count as a “word in FIFO memory.” Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the
output register (no read operation necessary), it is not included in the FIFO memory count.
48. The ORA and IRB functions are active during FWFT mode; the EFA
49. X2 is the Almost Empty offset for FIFO2 used by AEA
or port A programming.
. Y1 is the Almost Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset
and FFB functions are active in CY Standard Mode.
. Y2 is the Almost Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset
29
Page 30
Ordering Information
1K x36 x2 Bidirectional Synchronous FIFO
CY7C43642
CY7C43662
CY7C43682
Speed
(ns) Ordering Code
7 CY7C43642–7AC A120 120-Lead Thin Quad Fl at Package Commercial
10 CY7C43642–10AC A120 120-Lead Thin Quad Flat Package Commercial
15 CY7C43642–15AC A120 120-Lead Thin Quad Flat Package Commercial
4K x36 x2 Bidirectional Synchronous FIFO
Speed
(ns) Ordering Code
7 CY7C43662–7AC A120 120-Lead Thin Quad Fl at Package Commercial
10 CY7C43662–10AC A120 120-Lead Thin Quad Flat Package Commercial
15 CY7C43662–15AC A120 120-Lead Thin Quad Flat Package Commercial
16K x36 x2 Bidirectional Synchronous FIFO
Speed
(ns) Ordering Code
7 CY7C43682–7AC A120 120-Lead Thin Quad Fl at Package Commercial
10 CY7C43682–10AC A120 120-Lead Thin Quad Flat Package Commercial
15 CY7C43682–15AC A120 120-Lead Thin Quad Flat Package Commercial
15 CY7C43682–15AI A120 120-Lead Thin Quad Flat Package Industrial
Document #: 38-00698-D
Package
Name
Package
Name
Package
Name
Package
Type
Package
Type
Package
Type
Operating
Range
Operating
Range
Operating
Range
30
Page 31
Package Diagram
CY7C43642
CY7C43662
CY7C43682
120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) A120
51-85100
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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