Datasheet CY7C43686-7AC, CY7C43686-15AC, CY7C43686-10AC, CY7C43646-7AC, CY7C43646-15AC Datasheet (Cypress Semiconductor)

...

Page 1

1K/4K/16K x36/x18x2 Tri Bus FIFO

Features

• High-speed, low-power , first-in first-out (FIFO) memories w/ three indepen dent po rts (one bidire cti onal x36, and two unidirectional x18)

• 1K x36/x18x2 (CY7C43646)

• 4K x36/x18x2 (CY7C43666)

• 16K x36/x18x2 (CY7C43686)

• 0.35-micron CMOS for optimum speed/power

• High speed 133-MHz operati on (7.5-ns read /write cyc le times)

•Low power

—I

= 100 mA

= 10 mA

—I

Logic Block Diagram

CY7C43646 CY7C43666

CY7C43686

• Fully asynchronous and simultaneous read and write operation permitted

• Mailbox bypass register for each FIFO

• Parallel and Serial Programmable Almost Full and Almost Empty flags

• Retransmit function

• Standar d or FW FT mod e user selectable

• Partial Reset

• Big or Little Endian f ormat for word or byte bus sizes

• 128-pin TQFP packaging

• Easily expandable in width and depth

CLKA

CSA

W/RA

ENA

MBA

RT2

MRS1

PRS1

FFA/IRA

AFA

SPM

FS0/SD

FS1/SEN

0−35

EFA/ORA

AEA

MBF2

Port A Control Logic

FIFO1, Mail1 Reset Logic

Input

Programmable Flag Offset Registers

Output

Write Pointer

Read Pointer

Mail1 Register

1K/4K/16K

x36 Dual Ported Memory

Status Flag Logic

256/512/1K 4K/16K x36 Dual Ported Memory

Mail2 Register

Read Pointer

Timing Mode

Write Pointer

Input

Bus Matching

Output

Bus Matching

Output

Input

MBF1

0−17

CLKB

Port B Control Logic

Common Port Logic (B and C)

FIFO2, Mail2 Reset Logic

Port C Control Logic

RENB CSB SIZEB MBB RTI

EFB/ORB AEB

BE/FWFT

FFC/IRC AFC

MRS2

PRS2

0−17

CLKC WENC

SIZEC MBC

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 28, 2000

Page 2

Pin Configuration

W/RA

ENA

CLKA

GND

A A A A

A A

GND

A A A A A A A

BE/FWFT

GND

A A A A

GND

A A A A A

RT2

GND

A A

CY7C43646 CY7C43666 CY7C43686

TQFP

Top View

CSB

GND

MBF2

AEA

AFA

VCCPRS1

EFA/ORA

FFA/IRA

CSA

128

127

126

125

124

123

1 2 3

122

121

MBA

120

MRS1

119

FS0/SD

118

CLKC

117

GND

116

FS1/SEN

115

MRS2

114

MBB

113

112

VCCMBF1

111

4 5

33 32

8 9

13 14

27 26

18 19

20 21

27 28

33 34

35 36

CY7C43646 CY7C43666 CY7C43686

39404142434445464748495051525354555657585960616263

A6A7A8A

GND

A3A4A

SPM

A0A

GND

AEB

110

AFC

109

EFB/ORB

108

FFC/IRC

107

106

105

WENC

104

102 101 100

RENB

103

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

72 71 70 69 68 67 66 65

CLKB PRS2 V

GND MBC C

RT1 C

SIZEB GND C

GND B

SIZEC

GND B

B5B4B3B2B

GND

B9B8B

Page 3

CY7C43646 CY7C43666 CY7C43686

Functional Description

The CY7C436X6 is a monolithic, high-speed, low-power, CMOS Bidirectional Synchronous (clocked) FIFO memory which supports clock fr equencies up to 133 MHz and has read access times as fast as 6 ns. Two independent 1K/4K/16K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit f ormats wit h a choice of Big or Little Endian configurations.

The CY7C436X6 is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transf ers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidi rectional i nterfac e between microproces sors and/or buses with synchronous control.

Communicat ion betw een ea ch port may b ypa ss the FIF Os vi a two mailbox registers. The mailbox registers’ width matches the selected P o rt B bus width. Each mailbo x registe r has a flag (MBF1

and MBF2) to signal when new mail has been stored.

Two kinds of reset are available on the CY7C436X6: Master Reset and P artial Reset. Mast er Reset init iali zes t he read and write pointers to the first location of the memory array, configures the FIFO for Big or Little Endian byte arrangement and selects serial f lag programmi ng, parallel flag programming , or one of the three possible default flag offset settings, 8, 16, or

64. Each FIFO has its own independent Master Reset pin, MRS1 and MRS2.

Partial Reset also sets the read and write pointers to the first location of the mem ory. Unlike Master Reset, any settings existing prior to P artial Reset ( i.e., pr ogr amming method a nd partial flag default offsets) are retained. Partial Reset is useful since it permits fl ushing of the FI FO memory witho ut chang in g any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1

The CY7C436X6 have two modes of operation: In the CY Standard Mode, the first word writt en to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First-Word Fall-Through Mode (FWFT), the first long-word ( 36-bit-wide) written t o an empty FIFO appears au-

and PRS2.

tomatically on the outputs, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/FWFT operation det ermines th e mod e in use.

Each FIFO has a combined Empty/Output Ready flag (EFA ORA and EFB (FFA

/IRA and FFC/IRC). The E F and FF functions are selected in the CY Standard Mode. EF ory is full or not. The IR and OR functions are selected in the First-Wo rd Fall-Thr ough Mode . IR i ndica tes whet her or not the FIFO has av ailable m em ory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. (See footnote #24)

Each FIFO has a programmable Alm ost Empty flag (AEA AEB

) and a programmable Almost Full flag (AFA and AFC).

AEA

and AEB indic ate when a sele cted num ber of w ords written to FIFO memory achieve a predetermined “almost empty state.” AFA words written t o the m emory achieve a predet ermined “almost full sta te.” (See footnote #47)

IRA, IRC, AFA that w rit es da ta in to its array. ORA, ORB, AE A synchronized to the port clock that reads data from its array. Programmabl e offs et f or AEA in parallel using Port A or in serial via the SD input. Three default offset settings are also provided. The AEA threshold can be set at 8, 16, or 64 locations from the empty boundary and AFA 64 locations from the full boundary. All these choi ces are m ade using the FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider data paths. Such a width expansi on requires no additional external components.

If at any tim e the FIFO is not ac tive ly perf orming a funct ion, the chip will automatically power down. During the power-down state, suppl y current consumption (I ating any operation (by activating control inputs) will immed iately take the device out of the power-down state.

The CY7C436X6 are characterized for operation from 0°C to 70°C commercial, and from –40°C to 85°C industrial. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.

/ORB) and a combined Full/Input Ready flag

indicates whether the mem-

and AFC indicate when a selected number of

, and AFC are synchronized to the port clock

, AEB, AFA, and AFC are loaded

and AFC threshold can be set at 8, 16, or

pin during F IFO

and

, and AEB are

and AEB

) is at a minimum. Initi-

Selectio n Gu ide

CY7C43646/66/86

Maximum Frequency (MHz) 133 100 66.7 Maximum Access Time (ns) 6 8 10 Minimum Cycle Time (ns) 7.5 10 15 Minimum Data or Enable Set-Up (ns) 3 4 5 Minimum Data or Enabl e Hold ( ns) 0 0 0 Maximum Flag Delay (ns) 6 8 8 Active Power Supply

Current (I

Density 1K x 36 4K x 36 16K x 36 Package 128 TQFP 128 TQFP 128 TQFP

CC1

) (mA)

Commercial 100 100 100 Industrial 100

CY7C43646 CY7C43666 CY7C43686

-7

CY7C43646/66/86

-10

CY7C43646/66/86

-15

Page 4

CY7C43646 CY7C43666 CY7C43686

Pin Definitions

Signal Name Description I/O Function

0–35

AEA

AEB

AFA

AFC

0–17

BE/FWFT

0–17

CLKA Port A Clock I CLKA is a continuous clock t hat synchr onizes al l data t ransf ers thr ough P ort A and can

CLKB Port B Clock I CLKB is a continuous clock t hat synchr onizes al l data t ransf ers thr ough P ort B and can

CLKC P ort C Clock I CLKC is a con tinuous clock that sync hronizes all dat a trans fers through Port C and can

CSA

CSB

EFA

/ORA Port A Empty/

EFB

/ORB Port B

ENA Port A Enable I ENA must be HIGH to enable a LO W - to-HIGH t ransi tion of CLKA to read or write data

ENB Port B Enable I ENB must be HIGH to enable a LO W - to-HIGH t ransi tion of CLKB to read or write data

Port A Data I/O 36-bit bidirect ional data port for side A. Port A Almost

Empty Flag

O Programmab le Almost Empt y flag synchronized to CLKA. It i s LOW when the numb er

of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register, X2. (See footnote #47.)

Port B Almost Empty Flag

O Programmab le Almost Empt y flag syn chronized to CLKB. It is LOW when the number

of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register, X1. (See footnote #47.)

Port A Almost Full Flag

O Programmab le Almost Full fl ag synchronized to CLKA. It is LOW when the number of

empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset register, Y1. (See f ootnote #47.)

Port C Almost Full Flag

O Programmab le Almost Full flag synchronized to CLKC . It is LOW when the number of

empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset

First-Word FallThrough Select

I This is a dual-purpose pin. During Master Reset, a HIG H on BE will selec t Big Endian

operation. In thi s case, depe nding on the bus size, the most signi ficant byt e or word on

Port A is transf erred to P ort B first fo r A-to-B data flow. For data flowing from P ort C to

Port A, the first word/ byte written to Port C will come out as the most significant wo rd/

byte on Port A. On the other hand a LOW on BE will selec t Li ttle Endian oper ation. In

this case, the least sig nif icant byte or word on Port A is tr ansferred to Port B first f or A

to B data flow . Simila rly , t he first word/b yte written into P ort C will come out as the least

significant wo rd/byt e on P ort A for C-t o-A data flow. After Master Reset, this p in select s

the timing mode. A HIGH on FWFT

selects CY Standard Mode, a LOW selects FirstWord Fall-Throu gh Mod e. Once the timing mode has been selected, the le vel on this pin must be static throughout dev ice operation.

Port B Data I 18-bit input data port for port C.

be asynchronous or coincident to CLKB. FFA synchronized to the LOW-t o-HIGH transition of CLKA.

be asynchronous or coincident to CLKA. EFB the LOW-to-HIGH transit ion of CLKB.

be asynchronous or coincident to CLKA. FFC the LOW-to-HIGH transit ion of CLKC.

Port A Chip Select

Port B Chip Select

ICSA must be LOW to enable a LOW- to HIGH transition of CLKA to read or write on

Port A. The A

outputs are in the high-impedance state when CSA is HIGH.

0−35

ICSB must be LOW to enable a LOW- to HIGH transition of CLKB to read or write on

Port B. The B

outputs are in the high- impedance state when CSB is HIGH.

0–17

O This is a dual-function pin. In the CY Standard Mode, the EFA function is sel ected. EFA Output Ready Flag

indicates whether or not the FIFO2 memory is empty. In the FWFT Mode, the ORA function is selected. ORA indicat es the presence of valid data on A able for reading. EFA

/ORA is synchronized to the LOW-to-HIGH tra nsition of CLKA.

(See footnot e #24.)

O This is a dual-funct ion pin. In the CY Standard Mode, the EFB function is selected. EFB Empty/Output Ready Flag

indicates whether or not the FIFO1 memory is empty. In the FWFT Mode, the ORB function is selected. ORB indicat es the presence of valid data on B able for reading. EFB

/ORB is synchronized t o the LOW -t o-HIGH transition of CLKB.

(See footnot e #24.)

on Port A.

on Port B.

/IRA, EFA/ORA , A FA, and AEA are all

/ORB and AEB are all synchronized to

/IRC, and AFC are all synchronized to

outputs, avail-

0−35

outputs, avail-

0–17

Page 5

CY7C43646 CY7C43666 CY7C43686

Pin Definitions

Signal Name Description I/O Function

FFA

/IRA Port A Full/Input

/IRC Port C Full/Input

FFC

FS1/SEN

FS0/SD Flag Offset

MBA P ort A Ma i lbox

MBB P ort B Ma i lbox

MBC Port C Mailbox

MBF1

MBF2

MRS1

MRS2

PRS1

PRS2

(continued)

Ready Flag

Flag Offset Select 1/Serial Enable

Select 0/Serial Data

Select

Select Mail1 Register

Flag

Mail2 Register Flag

FIFO1 Master Reset

FIFO2 Master Reset

FIFO1 Partial Reset

FIFO2 Partial Reset

O This is a dual-fun ction pin . In the CY Standar d Mode, the FFA function is selected . FF A

indicates whether or not t he FIFO1 me mory is full. In t he FWFT mode , the IRA function is selected. IRA indicat es whether or not there is space av ailable f or writing to the FIFO1 memory. FFA

O This is a dual-funct ion pin. In the CY Standard Mode , the FFC functio n is selected. FFC

indicates whether or not the FIFO2 memory i s full. In the FWFT mod e, the IRC functi on is selected. IRC indicat es whether or not there is space available f or writing to the FIFO2 memory. FFC

I FS1/SEN and FS0/SD are dual-purpose input s used for flag offset register prog ram-

ming. During Master Reset, FS1/SEN offset program ming method. Three offs et register progr amming methods are a vailab le: automatically load one of three preset values (8, 16, or 64), parallel l oad from Port A,

or serial load. When serial load is selected for flag offset register programming, FS1/ SEN

is used as an enab le synchron ous to the LO W- to-HIGH tr ansition of CLKA. When FS1/SEN and Y registers . The numbe r of bi t writes r equi red t o progr am t he off set re gister s is 3 2 for the CY7C43626, 36 for the CY7C43636, 40 for the CY7C43646, 48 for the CY7C43666, and 56 for the CY7C43686. The first bit write stores the Y-register MSB and the last bit write stores the X-r egister LSB.

I A HIGH lev el on MBA chooses a mai lbox register for a Port A read or write operation.

When a read operatio n is perf ormed on Port A, a HIGH le v el on MBA select s data from the Mail2 register for output and a LOW level selects FIFO2 output r egister data for output. When a write operation is performed on Port A, a High level on MBA wil l write the data into Mail 1 register, while a Low l evel will write the data into FIFO 1.

I A HIGH lev el on MBB chooses a mail box regi ster for a Port B read operation. When a

read operation is per formed on Port B, a HIGH level on MBB selects data from the Mail1 register f or out put and a LO W l evel sel ects F IFO1 output regis ter dat a f o r o utput.

I When a write operat ion is perf ormed on Port C , a HIGH level o n M BC wri tes data into

Mail2 register, and a LOW level writes into FIFO2.

OMBF1 is set LOW by a LOW-to-HI G H tr ansition of CLKA that writes data to the Mail 1

register. Writes to the Mail1 register are inhibited whil e MBF1 HIGH by a LOW -t o-HIGH transit ion of CLKB when a Port B read is selected and MBB is HIGH. MBF1

OMBF2 is set LOW by a LOW-to-HI G H tr ansition of CLKB that writes data to the Mail 2

register. Writes to the Mail2 register are inhibited whil e MBF2 HIGH by a LOW -t o-HIGH transit ion of CLKA when a Port A read is selected and MBA is HIGH. MBF2

I A LOW on this pin initiali zes the FIFO1 read and write pointers to the first location of

memory and sets the P ort B output register to al l zeroes . A LOW puls e on MRS1 the programmi ng method (serial or parallel ) and one of three p rogrammab le flag def ault offsets f or FIFO1. It al so confi gures Port B for bus si z e and endian arran gement . F our LOW-to-HIGH transi tions of CLKA and four LO W-to-HIGH transitions of CLKB must occur while MRS1

I A LOW on this pin initiali zes the FIFO2 read and write pointers to the first location of

memory and sets the P ort A output register to al l zeroes . A LOW puls e on MRS2 one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitio ns of CLKB must occur while MRS2 LOW.

I A LOW on this pin initiali zes the FIFO1 read and write pointers to the first location of

memory and sets the Port B output register to all zeroes . During Partial Reset, the currently selected bus siz e, endian arrangement, program ming method (serial or parallel), and progr am m able flag sett ings are all retained.

I A LOW on this pin initiali zes the FIFO2 read and write pointers to the first location of

memory and sets the Port A output register to all zeroes . During Partial Reset, the currently selected bus siz e, endian arrangement, program ming method (serial or parallel), and progr am m able flag sett ings are all retained.

/IRA is synchroniz ed to the LOW-to-HIGH transit ion of CLKA.

/IRC is synchroniz ed to t he LOW- to- HIGH transition of CLKB.

and FS0/SD , together with SPM, sel ect the flag

is LOW, a rising edge on CLKA load the bit pr esent on FS0/SD into the X

is LOW. MBF1 is set

is set HIGH following either a Master or Partial Reset of FIFO1.

is LOW. MBF2 is set

is set HIGH following either a Master or Partial Reset of FIFO2.

selects

is LOW.

selects

Page 6

CY7C43646 CY7C43666 CY7C43686

Pin Definitions

(continued)

Signal Name Description I/O Function

RENB Port B Read

Enable

RT1

FIFO1 Retransmit

I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on

Port B.

I A LOW strobe on this pin will retransmit data on FIFO1. This is achieved by bringing

the read point er back to loca tion zero . The user will still need to perform re ad operations to retransmit the dat a. Retransmit func ti on applies to CY standard mode only.

RT2

FIFO2 Retransmit

I A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing

the read point er back to loca tion zero . The user will still need to perform re ad operations to retransmit the dat a. Retransmit func ti on applies to CY standard mode only.

SIZEB Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW

on this pin when BM is HIGH s elects w ord (18-bi t) b us si z e. SIZEB work s with BM and BE to select the bus siz e and end ian arrang ement f or Port B. The lev el of SIZEB must be static throughout device operation.

SIZEC Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port C. A LOW

on this pin when BM i s HIG H sele cts w ord (18-bit ) bus si ze. SIZEC w orks with BM and BE to select the bus si z e and endian arrange ment f or P ort B. The le v el of SIZEC must be static throughout device operation.

SPM

W/RA

WENC Port C Write

Serial Programming

Port A Write/ Read Select

Enable

I A LOW on this pin se lects serial p rogrammin g of partial flag offs ets. A HIGH on t his pin

selects paral lel programming or default offsets (8, 16, or 64).

I A HIGH selects a write operation and a LOW selects a read operation on Port A for a

LOW-to-HIGH trans it ion of CLKA. The A when W/RA

is HIGH.

outputs are in the high-impedance state

0−35

I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on

Port C.

Maximum Ratings

[1]

(Abov e which the useful lif e m ay be impaired. For user guidelines, not tested.)

Storage Temperature .......................................−65

C to +150°C

Ambient Temperature with

Power Applied....................................................−55

C to +125°C

Supply Voltage to Ground Potential..................−0.5V to +7.0V

DC Voltage Applied to Outp uts in High Z State

DC Input Voltage

Notes:

1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

3. Op erating V

[2]

..........................................−0.5V to V

[2]

.......................................−0.5V to V

Range for -7 speed is 5.0V ±0.25V.

CC CC

+0.5V +0.5V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage ....................... .. ............ .. ....>2001V

(per MIL-STD-883, Method 3015)

Latch -U p Cu rre n t.............. .......... ......... .......... .......... . >200mA

Operating Range

Ambient

Range

Temperature

Commercial 0°C to +70°C 5.0V±0.5V Industrial

−40°

C to +85°C 5.0V±0.5V

[3]

Page 7

CY7C43646 CY7C43666 CY7C43686

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

OZL

OZH

[4]

CC1

[5]

Capacitance

Output HIGH Voltage VCC = 4.5V., IOH = −4.0 mA 2.4 V Output LOW Voltage VCC = 4.5V., IOL = 8.0 mA 0.5 V Input HIGH Voltage 2.0 V Input LOW Voltage Input Leakage Current V Output OFF, High Z

= Max. −10 +10 µA

VSS < VO< V

Current Active Power Supply

Current Average Standby

Current

[6]

Parameter Description Test Conditions Max. Unit

OUT

Input Capacitance TA = 25°C, f = 1 MHz ,

= 5.0V

Output Capacitance 8 pF

AC Test Loads and Waveforms (-10 & -15)

7C43646/66/86

UnitMin. Max.

µA

−0.5

−10

0.8 V

+10

Com’l 100 mA Ind 100 mA Com’l 10 mA Ind 10 mA

4 pF

OUTPUT

INCLUDING

=30 pF

JIG AND

SCOPE

R1=1.1 K

Ω

R2=680

ALL INPUT PULSES

3.0V

Ω

GND

≤

3ns

90%

10%

90%

10%

≤

AC Test Loads and Waveforms (-7)

VCC/2

50Ω

I/O

Notes:

4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded.

5. All inputs = V

6. Tested initially and after any design or process changes that may affect these parameters.

– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.

= 

Ω

3.0V

GND

≤

3ns

ALL INPUT PULSES

90%

10%

90%

10%

≤

Page 8

CY7C43646 CY7C43666 CY7C43686

Switching Characteristics

Over the Operating Range

7C43646/

66/86

-7

7C43646/

66/86

-10

7C43646/

66/86

-15

Parameter Description

CLK

CLKH

CLKL

Clock Frequency, CLKA,CLKB, or CLKC 133 100 67 MHz Clock Cycle Time, CLKA,CLKB, or CLKC 7.5 10 15 ns Pulse Duration, CLKA,CLKB, or CLKC HIGH 3.5 4 6 ns Pulse Duration, CLKA,CLKB, or CLKC LOW 3.5 4 6 ns Set-Up Time, A

CLKB↑, and C Set-Up Time, CSA, W/RA, ENA, and MBA bef ore

before CLKA↑ B

0–35

before C LKC↑

0–17

before

3 4 5 ns

CLKA↑; RENB and MBB before CLKB↑ and WENC

ENS

RSTS

FSS

BES

SPMS

SDS

SENS

FWS

and MBC before CLKC↑ Set-Up Time, MRS1, MRS2, PRS1, or PRS2 LOW

before C LKA↑ or CL K B↑

[7]

Set-Up Time, FS0 and FS1 b ef ore MRS1 and MRS2

2.5 4 5 ns

6 7 7.5 ns

HIGH Set-Up Time, BE/FWFT before MRS1 and MRS2

5 7 7.5 ns

HIGH Set-Up Time, SPM before MRS1 and MRS2 HI GH 5 7 7.5 ns Set-Up Time, FS0/SD before CLKA↑ 3 4 5 ns Set-Up Time, FS1/SEN before CLKA↑ 3 4 5 ns Set-Up Time, FWFT before CLKA↑ 0 0 0 ns Hold Time, A

and C

0–17

Hold Time, CSA, W/RA , ENA, and MBA before

before CLKA ↑ B

0–35

before CLKC↑

before CLKB↑,

0–17

0 0 0 ns

CLKA↑ RENB and MBB before CLKB↑ and WENC

ENH

RSTH

FSH

BEH

SPMH

SDH

SENH

SPH

[8]

SKEW1

[8]

SKEW2

WFF

Notes:

7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

8. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

and MBC before CLKC↑ Hold Time, MRS1, MRS2, PRS1, or PRS2 LO W after

CLKA↑ or CLKB↑

[7]

Hold Time, FS0 and FS1 after MRS1 and MRS2

1 2 4 ns

1 1 2 ns

HIGH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 1 1 2 ns Hold Time, SPM after MRS1 and MRS2 HIGH 1 1 2 ns Hold Time, FS0/SD after CLKA↑ 0 0 0 ns Hold Time, FS1/SEN after CLKA↑ 0 0 0 ns Hold Time, FS1/SEN HIGH after MRS1 and MRS2

0 1 2 ns

HIGH Ske w Time between CLKA↑ and CLKB↑ for EFA/

ORA, EFB

/ORB, FFA/IRA, and FFC/IRC

Ske w Time between CLKA↑ and CLKB↑ for AEA, AEB

, AFA, AFC

Access Time, CLKA↑ to A

and CLKB↑ to B

0–35

0–17

Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to FFC

/IRC

5 5 7.5 ns

7 8 12 ns

1 6 1 8 3 10 ns 1 6 1 8 2 8 ns

UnitMin. Max. Min. Max. Min. Max.

Page 9

CY7C43646 CY7C43666 CY7C43686

Switching Characteristics

Over the Operating Range (continued)

Parameter Description

Propagation Delay Time, CLKA↑ to EFA/ORA and

REF

CLKB↑ to EFB

/ORB

Propagation Delay Time , CLKA↑ to AEA and CLKB↑

PAE

to AEB Propagation Dela y Time, CLKA↑ to A FA and CLKC↑

PAF

to AFC Propagation Delay Time, CLKA↑ to MBF1 LOW or

MBF2

HIGH and CLKB↑ to MBF2 LOW or MBF1

PMF

PMR

HIGH Propagation Delay Time, CLKA↑ to B

CLKB↑ to A

0–35

[10]

Propagation Delay Time, MBA to A

MDV

MBB to B

0–17

Valid

Propagation Delay Time, MRS1 or PRS1 LOW to AEB

LOW, AFA HIGH, FFA/IRA LOW, EFB/ORB

RSF

LOW and MBF1 AEA

LOW, AFC HIGH, FFC/IRC LOW, EFA/ORA

LOW and MBF2

HIGH and MRS2 or PRS2 LOW to HIGH

Enable Ti me, CSA or W/RA LO W to A

CSB LOW and RENB HIGH to B Disable Time, CSA or W/RA HIGH to A

DIS

PRT

RTR

Notes:

9. Writing data to the Mail1 register when the B

10. Writing data to the Mail2 register when the A

at High Impedance Retransmit Pulse Width 60 60 60 ns Retransmit recovery Time 90 90 90 ns

Impedance and CSB

HIGH or RENB LOW to B

outputs are active and MBB is HIGH.

0–17

outputs are active and MBA is HIGH.

0–35

0–17

Valid and

0–35

Active

0–35

[9]

and

Active a nd

at High

0–17

7C43646/

66/86

-7

7C43646/

66/86

-10

7C43646/

66/86

-15 UnitMin. Max. Min. Max. Min. Max.

1 6 1 8 1 8 ns

0 6 0 8 0 12 ns

1 7 2 11 3 12 ns

1 6 2 9 3 11 ns

1 6 1 10 1 15 ns

1 5 2 8 2 10 ns

1 5 1 6 1 8 ns

Page 10

Switching Waveforms

FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight

CLKA

CLKB

RSTS

MRS1

BE/FWFT

SPM

FS1/SEN, FS0/SD

FFA

/IRA

EFB

/ORB

RSF

BES

SPMS

FSS

[11, 12]

RSTH

BEH

SPMH

FSH

FWS

CY7C43646 CY7C43666 CY7C43686

WFF

RSF

AEB

AFA

RSF

MBF1

Notes:

11. PRS1

12. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.

and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.

Page 11

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

FIFO2 Master Reset Loading X1 and Y1 with a Preset Value of Eight

CLKC

CLKA

RSTS

MRS2

BE/FWFT

SPM

FS1/SEN, FS0,SD

FFC

/IRC

EFA

/ORA

RSF

AEA

AFC

RSF

BES

SPMS

FSS

[13, 14]

RSTS

BEH

SPMH

FSH

FWS

WFF

RSF

MBF2

Notes:

13. PRS2

14. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than the case where BE/FWFT is LOW.

and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.

Page 12

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

FIFO1 Partial Reset (CY Standard and FWFT Modes)

CLKA

CLKB

RSTS

PRS1

RSF

FFA/IRA

EFB

/ORB

RSF

AEB

RSF

AFA

RSF

MBF1

[12, 15]

RSTH

WFF

FIFO2 Partial Reset (CY Standard and FWFT Modes)

CLKC

CLKA

RSTS

PRS2

RSF

FFC/IRC

EFA

/ORA

RSF

AEA

RSF

AFC

RSF

MBF1

Notes:

15. MRS1

16. MRS2 must be HIGH during Partial Reset.

must be HIGH during Partial Reset.

[14, 16]

RSTH

WFF

Page 13

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

Parallel Program ming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset

(CY Standard and FWFT Modes)

(continued)

[17]

CLKA

MRS1

, MRS2

FSStFSH

SPM

FSS

FSH

FS1/SEN, FS0/SD

FFA/

IRA

WFF

ENS

ENH

ENA

AEB Offset (X1)

AFC

Offset (Y2)

AEA

Offset (X2)

0−35

AFA Offset (Y1)

CLKC

FFC

/IRC

SKEW1

First Word to FIFO1

[18]

WFF

Notes:

17. CSA

18. t

=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.

is the minimum time between the rising CLKA edge and a rising CLKB for FFC/IRC to transition HIGH in the next cycle. If the time between the rising

SKEW1

edge of CLKA and rising edge of CLKC is less than t

, then FFC/IRC may transition HIGH one cycle later than shown.

SKEW1

Page 14

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

Serial Programming of the Almost -Full Flag and Almost-Empty Flag Offset Values (CY Standard and FWFT Modes)

[19]

CLKA

MRS1

, MRS2

FSStFSH

SPM

FFA/IRA

FSS

SPH

SENS

SENH

FS1/SEN

FS0/SD

[21]

SDS

AFA Offset (Y1) MSB

SDH

SDS

CLKC

FFC/

IRC

SKEW1

SENH

SENS

SDH

AEA Offset (X2) LSB

[20]

WFF

Notes:

19. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.

20. t

21. Programmable offsets are written serially to the SD input in the order AFA

is the minimum time between the rising CLKA edge and a rising CLKC for FFC/IRC to transition HIGH in the next cycle. If the time between the rising

SKEW1

edge of CLKA and rising edge of CLKC is less than t

, then FFC/IRC may transition HIGH one cycle later than show.

SKEW1

offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).

Page 15

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

CLK

CLKH

CLKL

CLKA

FFA

/IRA

CSA

HIGH

ENS

ENH

W/RA

ENStENH

MBA

ENS

ENH

ENS

ENH

ENA

0–35

[22]

Port C Word Write Cyc le Timing for FIFO2 (CY Standard and FWFT Modes)

ENS

ENH

CLKC

/IRC

FFC

MBC

WENC

0–17

Note:

22. Written to FIFO1.

HIGH

ENStENH

ENS

ENH

DStDH

ENS

ENH

Page 16

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

Port C Byte Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

CLKC

/IRC

FFC

HIGH

ENStENH

MBC

ENStENH

WENC

0–8

Port B Byte Read Cycle Timing for FIFO1 (CY Standar d and FWFT Modes)

CLKB

[23, 24]

ENS

ENH

/ORB

EFB

HIGH

CSB

MBB

ENS

ENH

RENB

DIS

No Operation

MDV

0–8

(Standard Mode)

0–8

MDV

(FWFT Mode)

Note:

23. Unused bytes B

24. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the boundary flag (e.q. in bursts), use CY standard mode.

contain all zeroes for byte-size reads.

9–17

Previous Data

Page 17

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

Port B W ord Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

CLKB

/ORB

EFB

CSB

MBB

ENH

ENB

0–17

(Standard Mode)

0–17

(FWFT Mode)

MDV

Previous Data

[24]

No Operation

DIS

DIS

Port A Byte Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

CLKA

EFA

/ORA

CLKH

CLK

CLKL

CSA

W/RA

MBA

ENS

ENH

ENS

ENA

[25]

0−35

(Standard Mode)

0−35

(FWFT Mode)

Note:

25. Read From FIFO2.

MDV

ENH

[24]

ENStENH

No Operation

[25]

DIS

Page 18

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)

CLK

CLKH

CLKL

CLKA

CSA W/RA

LOW

HIGH

ENS

ENH

MBA

ENS

ENH

ENA

FFA

0–35

CLKB

EFB

/IRA

/ORB

HIGH

FIFO1 Empty

[27]

SKEW1

CLKHtCLKL

CLK

REF

[26]

CSB

MBB

LOW

RENB

0–17

Notes:

26. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO2, respectively.

27. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output

SKEW1

register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t load of the first word to the output register may occur one CLKB cycle later than shown.

Old Data in FIFO1 Output Regist er

ENStENH

, then the transition of ORB HIGH and

SKEW1

Page 19

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

EFB Flag Timing and First Data Read F all Through when FIFO1 is Empty (CY Standard Mode)

CLK

CLKHtCLKL

CLKA

CSA

W/RA

LOW

HIGH

ENS

ENH

MBA

ENS

ENH

ENA

/IRA

FFA

0–35

CLKB

EFB

/ORB

HIGH

FIFO1 Empty

SKEW1

[29]

CLKHtCLKL

CLK

REF

[28]

CSB

MBB

LOW

RENB

0–17

Notes:

28. If Port B size is word or byte, EFB

29. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between

SKEW1

the rising CLKA edge and rising CLKB edge is less than t

is set LOW by the last word or byte read from FIFO1, respectively.

ENS

ENH

, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

SKEW1

Page 20

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)

CLK

CLKH

CLKL

CLKC

ENH

ENS

MBC

WENC

ENH

ENS

FFC

/IRC

0–17

HIGH

[31]

SKEW1

CLKHtCLKL

CLKA

REF

EFA

CSA

/ORA

FIFO2 Empty

LOW

CLK

REF

[30]

W/RA

MBA

LOW

ENA

0–35

Notes:

30. If Port B size is word or byte, t

31. t

is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output

SKEW1

register in three CLKA cycles. If the time between the rising CLKC edge and rising CLKA edge is less than t load of the first word to the output register may occur one CLKA cycle later than shown.

Old Data in FIFO2 Output Register

is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.

SKEW1

ENStENH

, then the transition of ORA HIGH and

SKEW1

Page 21

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

EFA Flag Timing and First Dat a Read when FIFO2 is Empty (CY Standard Mode)

CLK

CLKHtCLKL

CLKC

ENH

ENS

MBC

ENH

ENS

WENC

/IRC

FFC

0–17

HIGH

SKEW1

[33]

CLKH

CLKL

CLKA

REF

EFA

CSA

/IRA

FIFO2 Empty

LOW

CLK

REF

[32]

W/RA

MBA

LOW

ENA

0–35

Notes:

32. If Port C size is word or byte, t

33. t

is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between

SKEW1

the rising CLKC edge and rising CLKA edge is less than t

is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.

SKEW1

ENStENH

, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

SKEW1

Page 22

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)

CLK

CLKL

CLKH

CLKB

CSB

MBB

LOW

ENS

ENH

RENB

/ORB

EFB

0–17

HIGH

Previous Word in FIFO1 Output Register

SKEW1

Next Word From FIFO1

[35]

CLKH

CLKL

CLKA

WFF

FFA

/IRA

FIFO1 Full

CLK

WFF

[34]

CSA

W/RA

LOW

HIGH

MBA

ENA

0–35

Notes:

34. If Port B size is word or byte, t

35. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the

SKEW1

rising CLKB edge and rising CLKA edge is less than t

is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.

SKEW1

ENH

ENS

ENStENH

To FIFO1

, then IRA may transition HIGH one CLKA cycle later than shown.

SKEW1

Page 23

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

FFA Flag Timing and Fi rst Available Write when FIFO1 is Full (CY Standard Mode)

CLK

CLKL

CLKH

CLKB

CSB

MBB

LOW

ENH

ENB

/ORB

EFB

0–17

HIGH

Previous Word in FIFO1 Output Register

SKEW1

Next Word From FIFO1

[36]

CLKHtCLKL

CLKA

WFF

FFA

/IRA

FIFO1 Full

CLK

WFF

[34]

CSA

W/RA

LOW

HIGH

MBA

ENA

0−35

Note:

36. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the

SKEW1

rising CLKB edge and rising CLKA edge is less than t

ENH

ENS

ENH

, then the transition of FFA HIGH may occur one CLKA cycle later than shown.

SKEW1

Page 24

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)

CLK

CLKL

CLKH

CLKA

CSA

W/RA

MBA

LOW

ENStENH

ENA

EFA

/ORA

0–35

HIGH

Previous Word in FIFO2 Output Register

SKEW1

Next Word Fro m FIFO2

[38]

CLKHtCLKL

CLKC

WFF

FFC

/IRC

FIFO2 Full

CLK

WFF

[37]

ENH

ENS

MBC

ENH

ENS

WENC

tDHt

0–17

To FIFO2

Notes:

37. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively.

38. t

is the minimum time between a rising CLKA edge and a rising CLKC edge for IRC to transition HIGH in the next CLKB cycle. If the time between the

SKEW1

rising CLKA edge and rising CLKC edge is less than t

, then the transition of IRC HIGH may occur one CLKC cycle later than shown.

SKEW1

Page 25

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

FFC Flag Timing and Fir st Available Write when FIFO2 is Full (CY Standard Mode)

CLK

CLKL

CLKH

CLKA

CSA

W/RA

MBA

LOW

ENS

ENH

ENA

EFA

/ORA

0–35

HIGH

Previous Word in FIFO2 Output Register

SKEW1

Next Word From FIFO2

[40]

CLKHtCLKL

CLKC

ENS

ENH

WFF

FFC

/IRC

FIFO2 Full

CLK

WFF

MBC

ENH

ENS

WENC

0–17

To FIFO2

[39]

Notes:

39. If Port C size is word or byte, FFC

40. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for FFC to transition HIGH in the next CLKB cycle. If the time between

SKEW1

the rising CLKA edge and rising CLKC edge is less than t

is set LOW by the last word or byte write of the long word, respectively.

, then the transition of FFC HIGH may occur one CLKC cycle later than shown.

SKEW1

Page 26

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

Timi ng for A E B

CLKA

ENA

CLKB

AEB

RENB

Timing for AEA

when FIFO2 is Almost Empty (CY Standard and FWFT Modes)

X1 Word in FIFO1

when FIFO2 is Almost Empty (CY Standard and FWFT Modes)

(continued)

ENS

ENH

SKEW2

[43]

PAE

[41, 42, 47 ]

(X1+1)Words in FIFO2

ENS

[44, 45, 47]

PAE

ENH

CLKC

ENS

ENH

WENC

[46]

SKEW2

CLKA

PAE

ENH

AEA

X2 Word in FIFO2

PAE

(X2+1) Words in FIFO2

ENS

ENA

Notes:

41. FIFO1 Write (CSA read from the FIFO.

42. If Port B size is word or byte, AEB

43. t

44. FIFO2 Write (MBB = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.

45. If Port C size is word or byte, t

46. t

47. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 3 clock cycles for flag assertion and deassertion. Refer to

is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between

SKEW2

the rising CLKA edge and rising CLKB edge is less than t

is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between

SKEW2

the rising CLKC edge and rising CLKA edge is less than t “Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.

= LOW, W/RA = LOW, MBA = LOW), FIFO1 Read (CSB = LOW , W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been

is set LOW by the last word or byte read from FIFO1, respectively.

, then AEB may transition HIGH one CLKB cycle later than shown.

SKEW2

is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.

SKEW2

, then AEA may transition HIGH one CLKA cycle later than shown.

SKEW2

Page 27

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)

[51]

CLKA

ENA

AFA

ENS

PAF

ENH

[D–(Y1+1)] Words in FIFO1

(D–Y1)Words in FIFO1

SKEW2

CLKB

RENB

Timing for AFC

when FIFO2 is Almost Full (CY Standard and FWFT Modes)

ENS

ENH

[47, 48, 49, 50 ]

[44, 47, 49, 52]

PAF

[53]

CLKC

WENC

AFC

ENS

ENH

PAF

[D–(Y2+1)] Words in FIFO2

(D–Y2)Words in FIFO2

SKEW2

CLKA

ENA

Notes:

48. FIFO1 Write (CSA the FIFO.

49. D = Maximum FIFO Depth = 1K for the CY7C43646, 4K for the CY7C43666, and 16K for the CY7C43686.

50. If Port B size is word or byte, t

51. t

52. If Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.

53. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the

SKEW2

rising CLKA edge and rising CLKB edge is less than t

is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between

SKEW2

the rising CLKC edge and rising CLKA edge is less than t

= LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from

is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

SKEW2

ENS

, then AFA may transition HIGH one CLKB cycle later than shown.

SKEW2

, then AFC may transition HIGH one CLKA cycle later than shown.

SKEW2

ENH

PAF

Page 28

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

Timing for Mail1 Register and MB F1

CLKA

CSA

W/RA

MBA

ENA

0–35

CLKB

MBF1

CSB

ENS

Flag (CY Standard and FWFT Modes)

ENH

ENS

ENH

PMF

[54]

PMF

MBB

RENB

0–17

Note:

54. If Port B is configured for word size, data can be written to the Mail1 register using A valid data). If Port B is configured for byte size, data can be written to the Mail1 Register using A will have valid data (B

will be indeterminate).

9–17

FIFO1 Output Register

MDV

PMR

ENS

W1 (Remains valid in Mail1 Register after read)

0–17

are “don’t care” inputs). In this first case B

18–35

0–8

9–35

ENH

are “don’t care” inputs). In this second case, B

DIS

0–17

will have

0–8

Page 29

CY7C43646 CY7C43666 CY7C43686

Switching Waveforms

(continued)

Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)

CLKC

MBC

ENH

ENS

WENC

0–17

CLKA

PMF

MBF2

CSA

W/RA

MBA

ENS

[55]

ENH

PMF

ENA

MDV

PMR

W1 (Remains valid in Mail2 Register after read)

0−35

FIFO1 Retransmit Timing

[56, 57, 58 , 59]

FIFO2 Output Register

RT1

PRT

RTR

RENB

EFB/FFA

Notes:

55. If Port C is configured for word size, data can be written to the Mail2 register using C indeterminate). If Port C is configured for byte size, data can be written to the Mail2 Register using B

will have valid data (A

0–8

56. Retransmit is performed in the same manner for FIFO2.

57. Clocks are free-running in this case. CY standard mode only.

58. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t

59. For the AF & AE flags, two clock cycles are necessary after t

will be indeterminate).

9–35

to update these flags.

RTR

. In this first case A

0–17

0–8

will have valid data (A

0–17

are “don’t c ar e” inputs). In this second case,

9–17

RTR

DIS

will be

18–35

Page 30

CY7C43646 CY7C43666 CY7C43686

Signal Description

Master Reset (

Each of the two FIFO memories of the CY7C436X6 undergoes a complete reset by taking its associated Master Reset (MRS1

, MRS2) i nput LOW for a t least f our P ort A clock ( CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset inputs can s w it ch asynchron ously to the clocks. A Master Reset initializes the internal read and write pointers and for ces the Fu ll/Inp ut Ready f lag (FF A the Empty/Output Ready flag (EF A Almost Empty flag (AEA (AFA

, AFC) HIGH. A Master Reset also for ces the Mailb ox fla g

(MBF1

, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag is set HIGH after tw o cloc k cycle s to begin normal oper ati on. A Master Reset must be perf ormed on the FIFO after power- up, bef ore data is written to its memory.

A LOW-to-HIGH transition on a FIFO Master Reset (MRS1 MRS2

) input latches t he value of the Big Endian (BE) input or determines the order by which bytes are transferred through Port B.

A LOW-to-HIGH transition on a FIFO reset (MRS1 input latches the values of the Flag select (FS0, FS1) and Serial Programming Mode (SPM Full and Almost Empty offset programming method (see Almost Empty and Almost Full flag offset programming below).

Partial Reset (

Each of the two FIFO memories of the CY7C436X6 undergoes a limited reset by taking its associated Partial Reset (PRS1 PRS2

) input LO W f or at least four Port A clock ( CLKA) and f our Po rt B clock (CLKB) LOW -to-HIGH trans itions. The Partial Reset inputs can switch asynchronously to the clocks. A Partial Reset initial izes the int ernal read and write pointer s and for ces the Full/Input Ready flag (FFA ty/Output Ready flag (EFA Empty flag (AEA AFC

) HIGH. A Partial Reset also forces the Mailbox flag

(MBF1

, MBF2) of the parallel mailbox register HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two cl ock cycles to begin normal oper ation.

Whatev er flag offset s, progr amming method (paral lel or serial), and timing mode (FWFT or CY Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will remain unch anged upon c ompletion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be i nconvenient.

Big Endian/First-Word Fall-Through (BE/FWFT

This is a dual-purpose pin. At the time of Master Reset , the BE select function is active, permitting a choice of Big or Little Endian byte arrangement for data written to or read from Port B. This selection determines the order by which bytes (or words) of data are tr ansferred th roug h this port. F or th e f ol lowing illustrations, assume that a byte (or word) bus size has been selected for Port B. (Note that when Port B is config ured for a long-wor d siz e, the Big En dian func tion has no appli cation and the BE input is a “don’t care.”)

A HIGH on the BE/FWFT and MRS2) inputs go f rom LOW to HIGH will select a Big Endian arrangement. When data is moving in the direction from

056

056

356

, AEB) LOW, and the Almost Full flag (AFA,

)

/IRA, FFC/IRC) LOW ,

/ORA, EFB/ORB) LO W, the

, AEB) LOW, and the Almost Full flag

, MRS2)

) inputs f or choosing the Almost

356

)

/IRA, FFC /IRC) LOW, the Emp-

/ORA, E F B/ORB) LOW, the Almost

)

input when the M aster Reset (M RS1

Port A to Port B, the most significant byte (word) of the longword written to P ort A will be transferred to P ort B first; the least significant b yte (word) of the lon g-word written to P ort A will be transf erred t o P ort B la st. When dat a is mo vi ng in th e direc tion from Port C to P ort A, th e b yte (w or d) writ ten t o Port C first w i ll be transferred to Port A as the most significant byte (word) of the long-word; the byte (word) written to Port C last will be transferred to Port A as the least significant byte (w ord) of the long- word.

A LOW on the BE/FWFT and MRS2) inputs go from LOW to HIGH will select a Little Endian arrangement. When data is moving in the direction from Port A to Port B, the least significant byte (word) of the long-word written to Port A will be transferred to Port B first; the most signi ficant b yte (wor d) of the long -word writ ten to P ort A will be transferred to Port B last. When data is m oving in the direction from Port C to Port A, the byte (word) written to Port C first will be transferred to port A as the least significa nt byte (word) of the long-word; the byte (word) written to Port C last

will be transf er red to P ort A as the most signif icant byt e (word ) of the long- word.

After Master Reset, t he FWFT select func tion is activ e, permitting a choice between two possible timing modes: CY Standard Mode or First-Word Fall-Through (FWFT) Mode. Once the Master R eset (MRS 1 BE/FWFT CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Standard Mode. This mode uses the Empty Flag function (EFA EFB the FIFO memory. It uses the Full Flag function (FFA indicate whether or not the FIFO memory has any free space

for writing. In CY Standard Mode, every word read from the FIFO, including the first, must be requested using a formal read operation.

Once the Master Reset (MRS1 on the BE/FWFT of CLKA (for FIFO1) and CLKC (for FIFO2) will select FWFT Mode. This mode uses the Output Ready function (ORA, ORB) to indicate whether or not there is valid data at the data outputs (A (IRA , IRC ) to ind icate wheth er or no t the F IFO me mor y has any free space for writing. In the FWFT mode, the first word written to an empty FIF O goes direct ly to data o utputs, no read request necessary. Subsequent words must be accessed by performing a f ormal r ead operation.

Following Master Reset, the level applied to the BE/FWFT put to choose the desired timing mode must remain static throughout the FIFO ope ration.

Programming the Almost Empty and Almos t Full Flags

Four registers in the CY7C436X6 are used to hold the offset values for the Almost Empty and Almost Full flags. The Port B Almost Empty flag (AEB Port A Almost Empty flag (AEA The Port A Almost Full flag (AFA and the Port C Almost Full flag (AF C Y2. The index of each register name corresponds with preset values during the reset of a FIFO, programmed in parallel using the FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1).

To load a FIFO’s Almost Empty fla g and Almost Full flag of fset registers with one of the three preset values listed in Table 1 ,

input during the next LOW-to-HIGH transition of

) to indicat e whether or not t here ar e a ny wo rds present in

or B

0–35

input when the Master Reset (MRS1

, MRS2) input is HIGH, a HIGH on the

input at the second LOW-to-HIGH transition

). It also uses the Input Ready func tion

0–17

, MRS2) input is HIGH, a LO W

) offset register is labeled X1 and the

) offset register is labeled X2.

) offset register is labeled Y1

) offset register is l abeled

, FFC) to

in-

Page 31

CY7C43646 CY7C43666 CY7C43686

the Serial Program Mode (SPM

) and at least one of the flagselect inputs m ust be HIGH during the LOW -to-HI GH transition of its Master Reset input (MRS1 load the preset val ue of 64 into X1 and Y1, SPM must be HIGH when FIFO1 r eset (MRS1

and MRS2). For example, to

, FS0, and F S1

) returns H IG H. Fl agoffset registers associated with FIFO2 are loaded with one of the preset v alues i n the same w ay wi th Master Reset (MRS2 When using one of the preset values for the flag offsets, the FIFOs can be reset simultaneously or at dif ferent times.

To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master Reset on both FIFOs simultaneously with SPM HIGH and FS0 and FS1 LO W during t he LO W - to-HIGH t ransi tion of MRS1

and MRS2. After this re s e t is co m p l et e, t he fi rs t four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the offset registers are (A (A

), for the CY7C436X6, respectively. The highest num-

0–13

bered input is used as the most significant bit of the binary

0–9

), (A

0–11

), or

number in ea ch case. Valid programming values for the registers range fro m 0 to 1023 f or the CY7C43646 ; 1 to 4095 for the CY7C43666; 0to 16383 f or th e CY7C43686. Afte r all the offset registers are programmed from Port A, the Port C Full/Input Ready (FFC

/IRC) is set HIGH and both FIFOs begin normal

operation. To program the X1, X2, Y1, and Y2 registers seriall y, initiate a

Master Reset with SPM

LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW -to-HI GH transiti on of MRS1 and MRS2. After this reset is complete, the X and Y register values are loaded bit-wise through the FS0/SD input on each LOW-toHIGH transition of CLKA that the FS1/SEN

input is LOW. 40, 48, or 56 bit writes are needed to complete the programming for t he CY7C436X6 , respectiv ely. The four regist ers are written in the order Y1, X1, Y2, and, finally, X2. The first-bit write stores the most significant bit of the Y1 register and the lastbit write stores the leas t significant bi t of the X2 register. Each register value can be programmed from 0 to 1023 (CY7C43646), 0 to 4095 (CY7C43666), or 0 to 16383 (CY7C43686).

When the opt ion t o prog r am the off set r egist ers se riall y is chosen, the Port A Full/Input Ready (F FA until all register bits are written. FFA

/IRA) flag remains LOW

/IRA is set HI GH by t he LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO1 operation. The Port C Full/Input ready (FFC

/IRC) flag also remains LOW throughout the serial pro-

gramming process, until all register bits are written. FFC

/IRC is set HIGH by the LOW-to-HIGH transition of CLKC after the last bit is loade d to al low normal FIFO2 operation.

SPM

, FS0/SD, and FS1/SEN function the same way in both

CY Standard and FWFT modes.

FIFO Write/Read Operation

The state of the Port A data (A A Chip Select (CSA The A CSA

lines are in the high-impedance state when either

0–35

or W/RA is HIGH. The A

when bo th CSA

) and Port A Write/Read Select (W/RA).

and W/RA are LOW.

Data is load ed into FIFO1 from t he A HIGH transition of CLKA when CSA ENA is HIGH, MBA is LOW , and FF A from FIFO2 to the A of CLKA when CSA is LOW, and EFA

outputs by a LOW -to-HIGH transi tion

0–35

is LOW, W/RA is LOW, ENA is HIGH, MBA

/ORA is HIGH (see Table 2). FIFO reads and

) lines is controlled by Port

0–35

lines are active outputs

0–35

inputs on a LOW -to-

0–35

is LOW, W/RA is HIGH,

/IRA is HIGH. Data is read

writes on Port A are independent of any concurrent Port B operation.

The state of the Port B data (B Port B Chip Select (CSB B

lines are in the high-impedance state when either CSB

0–17

is HIGH or RENB is LOW. The B

when CSB

is LOW and RENB is HIGH.

Data is load ed into FIFO2 from the C

) and P ort B Read select (RENB). The

) lines is controlled by the

0–17

lines are active outputs

0–17

inputs on a LOW -to-

0–17

HIGH transition of CLKC when WENC is LOW, MBC is LOW, and FFC

/IRC is HIGH. Data is read from FIFO1 to the B outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, RENB is HIGH, MBB is LOW, and EFB

/ORB is HIGH (see Table 3 ). FIFO reads on Port B and writes to Port C are independent of any concurrent Port A operation.

The set-up and hold t ime constraints to the port clocks for the port Chip Selects and Write/Read Selects are only f or enabli ng write and read operations and are not related to high-impedance control of the data o utputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and Write/Read Select may change states during the set-up and hold ti me window of the cy cle.

When operating the FIFO in FWFT Mode with the Output Ready flag LOW, the next word written is automat ical ly sent to the FIFO’s output register by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH, data residing in the FI FO’s memory array is cloc ked to the output reg- ister only when a read is sel ected usi ng the p ort’s C hip Select , Write/Read Select, Enab le, and Mailbox Select.

When operating the FIFO in CY Standar d Mode , r egardle ss o f whether the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is clocked to the output register only when a read is selected using the port’s Chip Select, Write/ Read Select, Enable, and Mailbo x Select.

Synchronized FIFO Fl ags

Each FIFO is synchronized to its port clock through at least two flip-fl op st ages . Thi s is d one t o impr ov e f lag-s ignal re liabil ity by reducing the probability of the metastable events when CLKA, CLKB, and CLKC operate asynchronously to one another . EFA CLKA. EFB IRC and AFC

/ORA, AEA, FF A/IRA, and AFA are synchronized to

/ORB and AEB are synchronized to CLKB. FFC/

are synchronized to CLKC. Table 5 and Table 6

show the relationship of each port flag to FIFO1 and FIFO2.

Empty/Output Ready Fla gs (EFA/ORA, EFB/ORB)

These are dual-purpose flags. In the FWFT M ode, the Output Ready (ORA, ORB) function is selected. When the Output Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word is prese nt in the FIFO output register and att empted FIFO reads are ignored.(See footn ote #24)

In the CY Standard Mode , the Empty Flag (EFA

, EFB) function is selected. When the Empty fl ag is HIGH, data is av ailable in the FIFO’s RAM memory for reading to the output register. When Empty flag is LOW, the previous data w ord is pres ent in the FIFO output register and attempted FIFO reads are ignored.

The Empty/Output Ready f lag of a FIFO is synchr onized to the port clock that reads data from its array. For both the FWFT and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The

0–17

Page 32

CY7C43646 CY7C43666 CY7C43686

state machine that controls an Output Ready flag monitors a write pointer and read pointer compar ator that indicate s when the FIFO SRAM status is empty, empty+1, or empty+2.

In FWFT Mode, from the time a w ord is writte n to a FIFO , it ca n be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three cycles hav e not elaps ed since the t ime the wor d was written. Th e Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH tr ansition of the synchronizing clock occurs, simultaneousl y f orc ing the Output Ready flag HIGH and shiftin g the word to the FIFO output register.

In the CY Standard Mode , from the time a word is writt en to a FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memo ry is the next dat a to be sent to the FIFO output register and two cycles have not elapsed since the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock oc cur s, f or cing the Empty Fl ag HIG H; onl y then can data be read.

A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizi ng clock begins the fir st synchronization cycle of a write if the clock transition occurs at time t after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycl e.

Full/Input Ready Flags (FFA

This is a dual-purpose flag. In FWFT Mode, the Input Ready (IRA and IRC) f unction is selec ted. In CY Standard Mode, the Full Flag (FFA modes, when the Full/Input Ready flag is HIGH, a memory location is free in the SRAM to receiv e new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored.

The Full/Input Read y flag of a FIFO is synchr onized to the port clock that writes data to its arra y. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its write pointer is inc rement ed. The st ate machi ne that cont rols a Full/ Input Ready flag monitors a write pointer and read pointer comparator t hat indicates when the FIFO SRAM sta tus is full, full–1, or full–2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/ Input Ready flag HIGH.

A LOW-to-HIGH transiti on on a Full/I nput Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t read. Otherwise, the subsequent clock cycle can be the first synchronization cycle.

Almost Empty Flags (AEA

The Almost Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost Empty flag monitors a write pointer and

and FFC) function is selected. For both timing

/IRA, FFC/IRC)

SKEW1

, AEB)

or greater after the

SKEW1

or greater

read pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The Almost Empty state is defined by the contents of register X1 for AEB ed with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset progr ammi ng abov e) . An Almost Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words . (See f oot note #47)

Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost Empty flag to reflect t he new level of fill. Therefore, the Almost Empty flag of a FIFO containing (X+1) or more w ords remai ns LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) l ev el. A LO W- to-HIGH tr ansition of an Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t the write that fills the FI FO to (X+1) word s. Otherwise , the subsequent synchronizing clock cycle may be the first syn chronization cycle.

Almost Full Flags (AFA

The Almost Full flag of a FIF O is sync hronized to the port cloc k that writes data t o its array. The state machine that contr ols an Almost Full f lag mon itor s a write po inter a nd read po inter c omparator that indicates when the FIFO SRAM status is almost full, a lmost full–1, or almost full–2. The Almost Full state is defined by t he contents of register Y1 for AFA for AFC a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming abo ve). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024–Y), (4096–Y), or (16384–Y) for the CY7C436X6 respectively. An Almost Full fl ag is HIG H when the n umber of wo rds in its F IFO is less than or equal to [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)] f or the CY7C436 X6 respect iv el y. (See footnote #47)

Two LOW-to-HIGH tr ansitions of the Alm ost Full flag synchronizing clock are required after a FIFO read for its Almost Full flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing [1024/4096/16384–(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in mem ory to [102 4/40 96/16384–(Y+1)] . A n Al most F ull flag is set HIGH by the second LOW-to-HIGH transition of its synchronizin g cloc k after the FI FO read t hat reduces the n umber of words in memory to [1024/4096/16384–(Y+1)]. A LOWto-HIGH transition of an Almost Full flag synchronizing clock begins the fi rst synchroni zation cy cle if i t occurs at time t or greater after the read that reduces the number of words in memory to [1024/4096/16384–(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle.

Mailbox Registers

Each FIFO has a 36-bit bypass regist er to pass command and control information between Port A and Port B/Port C without putting it in queue. The Mailbox Select (MBA, MBB, MBC) in-

and regist er X2 for AEA. These regis ters ar e load-

or greater after

SKEW2

, AFC)

. These regist ers are loaded wit h preset values during

and register Y2

SKEW2

Page 33

CY7C43646 CY7C43666 CY7C43686

puts choose bet ween a mai l register and a FIFO f or a port dat a transfer operation. The usable width of both the Mail1 and Mail2 registers matches the selected bus size for Port C.

A LOW-to-HIGH transition on CLKA writes A Mail1 Register whe n a Port A write is selected b y CSA

data to the

0−35

, W/RA,

and ENA with MBA HIGH. When sending data from P o rt C to P ort A via the Mail2 register ,

the following is the case: A LOW-to-HIGH transition on CLKC writes C selected by WENC with MBC HIGH. If t he selec ted Port C bus

data to the Mail2 register when a Port C write is

0−17

size is also 18 bits, then the usable widt h of the Mail2 register employs data lines C bits, then the usable width of the Mail2 register employs data lines C

. (In this cas e, C

0−8

. If the selected Port C bus size is 9

0–17

are “don’t care” inputs.)

9−17

Writing data to a mail register sets its corresponding flag (MBF1

or MBF2) LOW. At tempted writes t o a mail register are

ignored while the mail fl ag is LOW. When data outputs of a port are active, the data on the bus

comes from the FIFO output register when the port Mailbox Select input is LOW and from the mail register when the port Mailbox Select input is HIGH.

The Mail1 Register flag (MBF1

) is set HIGH by a LOW-toHIGH transition on CLKB when a Port B read is selected by CSB

, RENB, and ENB with MBB HIGH. F o r an 18- bit bus s ize , 18 bits of mailbox data are placed on B size, 9 bits of mailbox data are placed on B B

are indeterminate.)

9–17

The Mail2 Register flag (MBF2

) is set HIGH by a LOW-to-

. For a 9-bit bus

0–17

. (In this case,

0–8

HIGH transition on CLKA when a Port A read is selected by CSA

, W/RA, and ENA with MBA HIGH. The data in a mail register remains intact after it is read and

changes only when new data is written to the register. The Endian Select feature has no effect on the mailbox data.

Bus Sizing

The Po rt B and Port C buses can be configured in a 18-bit wor d or 9-bit byte format for data read from FIFO1 or written to FIFO2. The levels applied to the Port B Bus Size Select (SIZEB) and the P ort C Bus Size Select (SIZEC) determine the width of the b uses. The b us size can be se lected inde pendently for Ports B and C. These levels should be static throughout FIFO operation. Both bus size selections are implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set H IGH.

Two different methods for sequencing data transfer are available for Port B when the bus size selection is either byte or word-siz e . The y are ref er red t o as Big End ian ( most si gn ificant byte first) and Little Endian (least significant byte first). The level applied to the Big Endian Select (BE) input during the LOW -to- HIGH tran si tion of MRS1

and MRS2 selects the endian method that will be active during FIFO operation. BE is a “don’t care” input when the bus size sel ected f or P ort B is longword. The endia n metho d is impl emented at the comp letion of Master Reset, by the time the Full/Input Ready flag is set HIGH.

Only 36-bit long-word data is written to or read from the two FIFO memories on the CY7C436X6. Bus-mat ching oper ations are done after data is read from the FIFO1 RAM and before data is writte n to F IFO2 RAM. These b us -matchi ng oper ati ons are not available when transferring data via mailbox registers. Furthermore, both the word- and by te-si z e bus s ele ctions limi t the width of the data bus that can be used for mail register operations . I n thi s case, on ly t hose byt e lanes bel onging to t he selected word- or byte-size bus can carry mailbox data. The remaining data outputs will be indeterminate. The remaining data inputs will be “don’t care” inputs. For example, when a word-size bus is selected, then mailbox data can be transmitted only between A

0–17

and B

. When a byte-size bus is

0–17

selected, then mailbox data can be transmitted only between A

0–8

and B

0–8

Bus-Matching FIFO1 Reads

Data is written to the FIFO1 RAM in 36-bit long-word increments. If b yte or word size is im plemented on Port B, only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the long-word stored in auxiliary registers. In this case, subsequent FIFO1 reads output the rest of the long-word to the FIFO1 output register .

When reading data from FIFO1 as byt e, the unused B puts are indeterminate.

9–17

out-

Bus-Matching FIFO2 Writes

Data is written to the FIFO2 RAM in 18-bit word increments. Data written to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. The CLKC rising edge that writes the word t o FIFO2 also st ores t he enti re long word in FIFO2 RAM.

When reading data from FIFO2 in byte format, the unused C

outputs are LOW.

8–17

Retransmit (RT1

, RT2)

The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. Retransmit function applies to CY standar d mo de only.

The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least o ne wor d has be en read si nce the l ast rese t cycle. A LOW pulse on RT1

, (RT2) resets the internal read pointer to the first physical location of the FIFO. CLKA and CLKB may be fr ee run ning bu t RENB & (ENA) must be di sabled during and t valid read cycle after retransmit, previously accessed data is

after the retransmit pulse. With every

RTR

read and the read pointer is incr emented unt il i t is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT1 (RT2)

are transmitted also.

The full depth of the FIFO can be rep eatedly retransmi tted.

Page 34

BYTE ORDER ON PORT A:

PORT B BUS SIZING

27–35

18–26

9–17

CY7C43646 CY7C43666 CY7C43686

0–8

Write to FIFO1

%( 6,=(%

9–17

0–8

1st: Read from FIFO1

2nd: Read from FIFO1

(A) WORD SIZE – BIG ENDIAN

9–17

0–8

1st: Read from FIFO1

2nd: Read from FIFO1

(B) WORD SIZE – LITTLE ENDIAN

9–17

0–8

1st: Read from FIFO1

2nd: Read from FIFO1

3rd: Read from FIFO1

4th: Read from FIFO1

%( 6,=(%

9–17

0–8

1st: Read from FIFO1

2nd: Read from FIFO1

3rd: Read from FIFO1

4th: Read from FIFO1

(D) BYTE SIZE – LITTLE ENDIAN

Page 35

PORT C BUS SIZING

CY7C43646 CY7C43666 CY7C43686

BYTE ORDER ON PORT A:

%( 6,=(&

27–35

9–17

18–26

9–17

0–8

(A) WORD SIZE – BIG ENDIAN

9–17

0–8

(B) WORD SIZE – LITTLE ENDIAN

9–17

0–8

9–17

0–8

9–17

0–8

9–17

0–8

Read from FIFO2

1st: Write to FIFO2

2nd: Write to FIFO2

1st: Write to FIFO2

2nd: Write to FIFO2

1st: Write to FIFO2

2nd: Write to FIFO2

3rd: Write to FIFO2

4th: Write to FIFO2

%( 6,=(&

9–17

0–8

1st: Write to FIFO2

2nd: Write to FIFO2

3rd: Write to FIFO2

4th: Write to FIFO2

(D) BYTE SIZE – LITTLE ENDIAN

Page 36

CY7C43646 CY7C43666 CY7C43686

Table 1. Flag Program m ing

SPM FS1/SEN FS0/SD MRS1 MRS2 X1 and Y1 Registers

H H H H H H X H H L H H L X H L H H L H X H L L

L H L L H H L L H L L L

[47]

↑

↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑

[60]

X2 and Y2 Registers

X 64 X

↑

X 64

X 16 X

↑

X 16

X 8 X

↑

X 8

Par allel programming via P ort A Parallel programming via Port A

Serial programming via SD Serial program ming via SD

Reserved Reserved Reserved Reserved Reserved Reserved

Table 2. Port A Enable Function Table

CSA

W/RA ENA MBA CLKA A

OUTPUTS PORT FUNCTION

0–35

H X X X X In high-impedance state None

L H L X X In high-impedance state None LHHL↑ In high-impedance state FIFO1 write LHHH↑ In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None LLHL↑ Active, FIFO2 output register FIFO2 read L L L H X Active, Mail2 register None LLHH↑ Active, Mail2 register Mail2 r ead (set MBF2

[61]

HIGH)

Table 3. Port B Enable Function Table

CSB

RENB MBB CLKB B

OUTPUTS PORT FUNCTION

0–17

H X X X In high-impedance state None

L L L X Active, FIFO1 output register None LH L ↑ Active, FIFO1 output register FIFO1 read L L H X Active, Ma il1 register None LHH ↑ Active, Mail1 register Mail1 read (set MBF1

Table 4. Port C Enable Function Table

WENC MBC C LKC C

INPUTS PORT FUNCTION

0–17

HL ↑ In high-impedance state FIFO2 write HH ↑ In high-impedance state Mail2 write

L L X In high-impedance state None L H X Active, Mail1 regis ter None

Notes:

60. X1 register holds the offset for AEB

61. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.

; Y1 register holds the offset for AFA.

HIGH)

Page 37

CY7C43646 CY7C43666 CY7C43686

Table 5. FIFO1 Flag Operation (CY Standard and FWFT modes)

Number of Words in FIFO Memory

[62, 63, 64 , 65]

[47]

Synchronized to CLKB Synchronized to CLKA

CY7C43646 CY7C43666 CY7C43686 EFB/ORB AEB AFA FFA/IRA

0 0 0 L L H H

1 TO X1 1 TO X1 1 TO X1 H L H H

(X1+1) to

[1024–(Y1+1)]

(X1+1) to

[4096–(Y1+1)]

(X1+1) to [16384–

(Y1+1)]

H H H H

(1024–Y1) to 1023 (4096–Y1) to 4095 (16384–Y1) to 16383 H H L H

1024 4096 16384 H H L L

Table 6. FIFO2 FLAG OPERATION (CY Standard and FWFT modes)

Number of Words in FIFO Memory

[63, 64, 66 , 67]

[47]

Synchronized to CLKA Synchroni zed to CLKC

CY7C43646 CY7C43666 CY7C43686 EFA/ORA AEA AFC FFC/IRC

0 0 0 L L H H

1 TO X2 1 TO X2 1 TO X2 H L H H

(X2+1) to

[1024–(Y2+1)]

(X2+1) to

[4096–(Y2+1)]

(X2+1) to

[16384–(Y2+1)]

H H H H

(1024–Y2) to 1023 (4096–Y2) to 4095 (16384–Y2 ) to 16383 H H L H

1024 4096 16384 H H L L

Table 7. Data Size for Word Writes to FI FO 2

Size Mode

BM SIZE BE C

[68]

Write No. Data Written to FIFO2 Data Read From FIFO2

9–17

0–8

27–35

18–26

9–17

0–8

HLH1ABABCD

2CD

HLL1CDABCD

2AB

Notes:

62. X1 is the Almost Empty offset for FIFO1 used by AEB or port A programming.

63. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

64. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.

65. The ORB and IRA functions are active during FWFT mode; the EFB

66. X2 is the Almost Empty offset for FIFO2 used by AEA. Y2 is the Almost Full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.

67. The ORA and IRC functions are active during FWFT mode; the EFA and FFC functions are active in CY Standard mode.

68. BE is selected at Master Reset. SIZEC must be static throughout device operation.

. Y1 is the Almost Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset

and FFA functions are active in CY Standard mode.

Page 38

CY7C43646 CY7C43666 CY7C43686

Table 8. Data Size for Byte Writes to FIFO2

Size Mode

>@

Write No.

BM SIZE BE C

HHH1 A ABCD

2B 3C 4D

HHL1 D ABCD

2C 3B 4A

Table 9. Data Size for Word Reads from FIFO1

Size Mode

BM SIZE BE A

>@

27–35

HLHABCD1AB

HLLABCD1CD

Data Wri tten to

FIFO2 Data Read From FIFO2

0–8

27–35

18–26

Data Written to FIFO1 Read No.

18–26

9–17

0–8

2CD

2AB

9–17

Data Read From

FIFO1

9–17

0–8

Table 10. Data Size for Byte Reads fr om FIFO1

Size Mode

>@

BM SIZE BE A

27–35

Data Written to FIFO1 Read No.

18–26

9–17

0–8

Data Read From

FIFO1

HHHABCD1 A

2B 3C 4D

HHLABCD1 D

2C 3B 4A

0–8

Page 39

CY7C43646 CY7C43666 CY7C43686

Ordering Informat ion

1K x36/18x2 Tri Bus Synchr onous FIFO

Speed

(ns) Ordering Code

7 CY7C43646-7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43646-10AC A128 128-Lead Thin Quad Flat Package Commercial 15 CY7C43646-15AC A128 128-Lead Thin Quad Flat Package Commercial

4K x36/18x2 Tri Bus Synchr onous FIFO

Speed

(ns) Ordering Code

7 CY7C43666-7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43666-10AC A128 128-Lead Thin Quad Flat P ackage Commercial 15 CY7C43666-15AC A128 128-Lead Thin Quad Flat P ackage Commercial

16K x36/18x2 Tri Bus Synchr onous FIFO

Speed

(ns) Ordering Code

7 CY7C43686-7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43686-10AC A128 128-Lead Thin Quad Flat Pac kage Commercial 15 CY7C43686-15AC A128 128-Lead Thin Quad Flat Pac kage Commercial 15 CY7C43686–15AI A128 128-Lead Thin Quad Fl at Package Industrial

Package

Name

Package

Name

Package

Name

Package

Type

Package

Type

Package

Type

Operating

Range

Operating

Range

Operating

Range

Document #: 38-00701-C

Page 40

Package Diagram

CY7C43646 CY7C43666

CY7C43686

128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128

51-85101-A

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Datasheet CY7C43686-7AC, CY7C43686-15AC, CY7C43686-10AC, CY7C43646-7AC, CY7C43646-15AC Datasheet (Cypress Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual