Datasheet CY7C43683-7AC, CY7C43663-7AC, CY7C43663-15AC, CY7C43663-10AC, CY7C43683-15AC Datasheet (Cypress Semiconductor)

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Page 1

Synchronous FIFO w/ Bus Matching

Features

• High-speed, lo w-power, Unidirectional, First-in Firstout (FIFO) memories w/bus matching capabili ties

• 1Kx36 (CY7C43643)

• 4Kx36 (CY7C43663)

• 16Kx36 (CY7C43683)

• 0.35-micron CMOS for optimum speed/power

• High-speed 133-MH z operation (7.5 ns read /write cyc le times)

•Low power

—I

= 100 mA

= 10 mA

—I

Logic Block Diagram

CY7C43643 CY7C43663

CY7C43683

1K/4K/16K x36 Unidirectional

• Fully asynchronous and simultaneous read and write operation permitted

• Mailbox bypass register for each FIFO

• Parallel and Serial Programmable Almost Full and Almost Empty flags

• Retransmit func tion

• Standard or FWFT mode user selectable

• Partial Reset

• Big or Little Endian f ormat for word or byte bus sizes

• 128-pin TQFP packaging

• Easily expandable in width and depth

CLKA

CSA

W/RA

ENA

MBA

MRS1

MRS2

PRS

FF/IR

SPM

FS0/SD

FS1/SEN

0–35

MBF2

Port A Control Logic

FIFO, Mail1 Mail2 Reset Logic

Input

Write Pointer

Programmable Flag Offset Registers

Mail1 Register

1K/4K/16K

x36 Dual Ported Memory

Status Flag Logic

Timing Mode

Mail2 Register

Read Pointer

Bus Matching

Output

MBF1

CLKB

Port B Control

Logic

CSB W/RB ENB MBB BE

BM SIZE

EF/OR AE

0–35

BE/FWFT

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 28, 2000

Page 2

CY7C43643 CY7C43663

CY7C43683

Pin Configuration

BE/FWFT

W/RA

ENA

CLKA

GND

A A A A

A A

GND

A A A A A A A

GND

A A A A

GND

A A A A A

GND

A A

TQFP

Top View

CSB

GND

CSA

FF/IR

128

127

126

1 2 3

125

MBF2NCAF

FS0/SD

FS1/SEN

GND

MRS1

VCCPRS

124

MBA

123

122

121

120

119

118

117

116

115

VCCMBF1

MRS2

MBB

114

113

112

111

4 5

33 32

8 9

13 14

27 26

18 19

20 21

27 28

35 36

CY7C43643 CY7C43663 CY7C43683

39404142434445464748495051525354555657585960616263

A6A7A8A

GND

A3A4A

SPM

A0A

GND

EF/OR

110

109

108

107

ENB

W/RB

106

105

104

103

102

CLKB

101

100

GND

94 93

87 86

84 83

GND

GND B

SIZE

GND

B5B4B3B2B

GND

B9B8B

Page 3

CY7C43643 CY7C43663

CY7C43683

Functional Description

The CY7C436x3 is a monolithic, high-speed, low-power, CMOS Unidirectional Synchronous (clocked) FIFO memory which supports clock fr equencies up to 133 MHz and has read access times as fast as 6 ns. Two independent 1K/4K/16K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be output in 36bit, 18-bit, or 9-bit formats with a choice of Big or Little Endian configurations.

The CY7C436x3 is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data tran sfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple unidirectional interface between microprocessors and/ or buses with synchronous control.

Communicat ion betw een ea ch port may b ypa ss the FIF Os vi a two mailbox registers. The mailbox registers’ width matches the selected P o rt B bus width. Each mailbo x registe r has a flag (MBF1

and MBF2) to signal when new mail has been stored.

Two kinds of reset are available on the CY7C436x3: Master Reset and P artial Reset. Mast er Reset init iali zes t he read and write pointers to the first location of the memory array, configures the FIFO for Big or Little Endian byte arrangement and selects serial f lag programming, parallel flag prog ramming, or one of the three possible default flag offset settings, 8, 16, or

64. The FIFO also has two Master Reset pins, MRS1 MRS2

Partial Reset also sets the read and write pointers to the first location of the mem ory. Unlike Master Reset, any settings existing prior to P artial Reset ( i.e., pr ogr amming method a nd partial flag default offsets) are retained. Partial Reset is useful since it permits fl ushing of the FI FO memory witho ut chang in g any configuration settings. The FIFO has its own i ndependent Partial Reset pi n, PRS

The CY7C436x3 have two modes of o peratio n: In t he CY Standard Mode, the fir st word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In

and

the First-Word F all-Through Mode (FWFT), the first long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation required (nevertheless, accessing subsequent words does necessitat e a f ormal read re quest). The state of the BE/FWFT determines the mode in use.

The FIFO has a combined Empty/Output Ready flag (EF and a combi ned Full/Input Ready flag (FF functions a re selected in the CY Standard Mode. EF indicat es whether the memory is full or not. The IR and OR funct ions are selected in the First-Word Fall-Through Mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has dat a av ai labl e f or readi ng or not. It marks the presence of valid data on the outputs. (See footnote #18)

The FIFO has a programm able Almost Empty flag (AE programmab le Almost Full flag (AF lected number of words written to FIFO memory achieve a predetermined “almost empty state.” AF lected number of words written to the memory achieve a predetermined “almost full state.” (See footnote #34)

IR and AF into its array. OR and AE that reads data fro m its arr a y. Pro grammab l e offs et f or AE AF SD input. Three default offset settings are also provided. The AE empty boundary and AF locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider data paths. If any time the FIFO is not actively performing a function, the chip will automatically power down. During the power-down state, supply current consumption (I minimum. Init iating a ny oper ati on (b y act iv ati ng con trol inputs ) will immediately take the device out of t he power-down state .

The CY7C436x3 are characterized for operation from 0°C to 70°C commercial, and from –40°C to 85°C industrial. Input ESD protection is gr eater than 2001V, and latch-up is pr evented by the use of guard rings.

are synchronized to the port clock that writes data

are synchronized to the port clock can be loaded in parallel using Port A or i n serial via the threshold can be set at 8, 16, or 64 locations from the

threshold can be set at 8, 16, or 64

pin during FIFO operation

) is at a

/OR)

) and a

and

/IR). The EF and FF

). AE indicates when a se-

indicates when a se-

Selectio n Gu ide

CY7C43643/63/83

Maximum Frequency (MHz) 133 100 66.7 Maximum Access Time (ns) 6 8 10 Minimum Cycle Time (ns) 7.5 10 15 Minimum Data or Enable Set-Up (ns) 3 4 5 Minimum Data or Enabl e Hold ( ns) 0 0 0 Maximum Flag Delay (ns) 6 8 8 Active Power Supply

Current (I

Density 1K x 36 4K x 36 16K x 36 Package 128 TQFP 128 TQFP 128 TQFP

CC1

) (mA)

Commercial 100 100 100 Industrial 100

–

CY7C43643 CY7C43663 CY7C43683

CY7C43643/63/83

–10

CY7C43643/63/83

–

Page 4

CY7C43643 CY7C43663

CY7C43683

Pin Definitions

Signal Name Description I/O Function

0–35

BE/FWFT

BM Bus Match

CLKA Port A Clock I CLKA is a continu ous cloc k that sy nchroniz es al l data tr ansfer s through P ort A and can

CLKB Port B Clock I CLKB is a continuous clock t hat synchr onizes al l data t ransf ers thr ough P ort B and can

CSA

CSB

/OR Empty/Output

ENA Port A Enable I ENA must be HIGH to enable a LOW- to-HIGH tr ansit ion of CLKA t o read or write data

ENB Port B Enable I ENB must be HIGH to enable a LOW- to-HIGH tr ansit ion of CLKB t o read or write data

/IR Port B Full/Input

FS1/SEN

FS0/SD Flag Offset

Port A Data I 36-bit unidirectional data port for side A. Almost Empty

Flag (Port B)

Almost Full Flag O Progr am m able Almost Full flag synchroniz ed to CLKA. It is LOW when the num ber of

Port B Data O 36-bit unidirectional data port for side B. Big Endian/

First-Word FallThrough Select

Select (Port B)

Port A Chip Select

Port B Chip Select

Ready Flag (Port B)

Ready Flag

Flag Offset Select 1/Serial Enable

Select 0/Serial Data

O Programmab le Almost Empty flag synchronized to CLKA. It is LO W when the numb er

of words in the FIFO2 is less than or equal to the value in the Almost Empty A offset register, X. (See foot note #.)

empty locations in t he FIFO is less tha n or equal to the v alue in t he Almost Full A off set register, Y. (See f ootnote #.)

I This is a dual-purpose pin. During Master Reset, a HIG H on BE will selec t Big Endian

operation. In thi s case, depe nding on the bus size, the most signi ficant byt e or word on Port A is transf err ed to P ort B first. A LO W on BE will select Little Endi an opera tion. In this case, the l eas t signif icant b yte or w ord on Port A is transferred to P ort B fir st. Af ter Master Reset, this pin select s the timing mode. A HI GH on FWFT Mode, a LO W sel ects Fi rst- W ord Fall-Thr ough Mo de. Onc e th e timi ng mode h as been selected, the level on FWFT

I A HIGH on this pin enables eith er byt e or w ord bus width on Port B, depending on the

state of SIZE. A LOW select s long-word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. The level of BM must be static throughout device operation.

be asynchronous or coincident to CLKB. FF to-HIGH transition of CLKA.

be asynchronous or coincident to CLKA. FB nized to the LO W-to-HIGH tran sition of CLKB.

ICSA must be LOW to enable a LOW-t o HIGH tr ansition of CLKA to read or write on

Port A. The A

ICSB must be LOW to enable a LOW-t o HIGH tr ansition of CLKB to read or write on

Port B. The B

O This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF

indicates whether or not the FIFO memory is empty . In the FWFT mode, the OR function is selected. OR indicates the presence of valid data on A reading. EF #34.)

on Port A.

on Port B.

O This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF

indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indi cates whet her or not there is spac e a v aila ble f or writing to the FIFO memory. FF

I FS1/SEN and FS0/SD are dual-purpose input s used for flag offset regi ster program-

ming. During Master Reset, FS1/SEN offset program ming method. Three offs et register progr amming methods are a vailab le: automatically load one of three preset v alues (8, 16, or 64), par allel load from Port A,

and serial load. When serial load i s select ed f or flag offs et regi ster pr ogr amming , FS1/ SEN

is used as an enab le synchron ous to the LO W- to-HIGH tr ansition of CLKA. When FS1/SEN and Y registers . The numbe r of bi t writes r equi red t o progr am t he off set re gister s is 2 0 for the CY7C43643, 24 for the CY7C43663, and 28 for the CY7C43683. The first bit write stores the Y-register MSB and the last bit write stores t he X-register LSB.

is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X

outputs are in the high-im pedance state when CSA is HIGH.

0–35

outputs are in the high- impedance state when CSB is HIGH.

0–35

/OR is synchr onized t o the LO W -to-HIGH t ransit ion of CLKB . (See f o otnote

/IR is synchronized to the LOW-to-HIGH transit ion of CLKA.

must be static throughout device operation.

/IR and AF are all synchronize d to the LO W-

/IR, EF /OR, AF, and AE are all synchro-

and FS0/SD , together with SPM, sel ect the flag

selects CY Standar d

outputs, available for

0–35

Page 5

CY7C43643 CY7C43663

CY7C43683

Pin Definitions

Signal Name Description I/O Function

MBA P ort A Mailbox

MBB P ort B Mailbox

MBF1

MBF2

MRS1

MRS2 PRS

SIZE Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) si ze on Port B. A LOW

SPM

W/RA

RB Port B Write/

(continued)

Select

Mail1 Register Flag

Mail2 Register Flag

Master Reset I A LOW on this pin initializes the FIFO read and write pointers to the fi rst location of

Master Reset I A LOW on this pin initiali zes the Mail2 register. Partial Reset I A LOW on this pin initializes the FIFO read and write pointers to the first location of

Retransmit I A LOW str obe o n thi s pin will retran smit data on t he FIFO. This is achi e v ed b y bringing

Serial Programming

Port A Write/ Read Select

Read Select

I A HIGH lev el on MBA chooses a mail box register for a Port A read or write operation.

I A HIGH lev el on MBB chooses a mail box register for a Port B read or write operation.

When a read operatio n is perf ormed on Port B, a HIGH lev el on MBB select s data from the Mail1 register for output and a LOW level selec ts FIFO output register data for output. Data can only be written into Mail 2 reg ister through Port B (MBB HIGH) and not into the FIFO memory.

OMBF1 is set LOW by a LOW-to-HIGH tr ansition of CLKA that writes data to the Mail1

register. Writes to the Mail1 register are inhibited while MBF1 HIGH by a LOW-to-HIGH transitio n of CLKB when a Port B read is selected and MBB is HIGH. MBF1

OMBF2 is set LOW by a LOW-to-HIGH tr ansition of CLKB that writes data to the Mail2

register. Writes to the Mail2 register are inhibited while MBF2 HIGH by a LOW-to-HIGH transitio n of CLKA when a Port A read is selected and MBA is HIGH. MBF2

memory and sets the P ort B output register to al l zeroes . A LOW puls e on MRS1 the programmi ng method (serial or parallel ) and one of three p rogrammab le flag def ault offsets. It al so configures Port B for bus size and endian arrangement. Four LOW -toHIGH transitio ns of CLKA and f our LO W-t o-HIGH tr ansitions of CLKB m ust occur while MRS1

is LOW.

memory and sets the Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or par allel), and progr am m able flag settings are all retained.

the read pointer bac k to loc ation zer o . The user will still need to perf orm read operat ion to retransmit the dat a. Retransmit function applies to CY standard mode only.

on this pin when BM is HIGH selec ts word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation.

I A LOW on this pin se lects serial p rogrammin g of partial flag offs ets. A HIGH on t his pin

selects paral lel programming or default offsets (8 , 16, or 64).

I A HIGH selects a write operation and a LOW selects a read operat ion on Port A for a

LOW-to-HIGH transition of CLKA. The A when W/RA

I A LOW selects a write operation and a HIGH selects a read operation on Port B for a

LOW-to-HIGH transit ion of CLKB. The B when W

is set HIGH following either a Master or Partial Reset.

is set HIGH following either a Master or P arti al Reset of FIFO2.

outputs are in the high-impedance state

is HIGH.

/RB is LOW.

0–35

outputs are in the high-impedance state

0–35

is LOW. MBF1 is set

is LOW. MBF2 is set

selects

Page 6

CY7C43643 CY7C43663

CY7C43683

Maximum Ratings

[1]

(Abov e which the useful life may be impaired. F or user guidelines, not tested.)

Storage Temperature ............. .......... ... .........–65

C to +150°C

Ambient Temperature with

Power Applied ...............................................–55

C to +125°C

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage.......... ............. .. ..................>2001V

(per MIL-STD-883, Method 3015)

Latch -U p Cu rre n t....... ......... .......... .......... ......... ......... >200mA

Operating Range

Supply Voltage to Gr o u nd Potent ia l ..... ......... . –0.5V to +7.0V

DC Voltage Applied to Outputs in High Z State

DC Input Voltage

Electrical Characteristics

[2]

......................................–0.5V to VCC+0.5V

[2]

...................................–0.5V to VCC+0.5V

Over the Operating Range

Parameter Description Te st Condi tions

V V I

OZL

OZH

CC1

IH IL

[4]

[5]

Output HIGH Voltage VCC = 4.5V,

= –4.0 mA

Output LO W Voltage VCC = 4.5V,

= 8.0 mA

Input HIGH Voltage 2.0 V Input LOW Vol tage –0.5 0.8 V Input Leakage Curr ent V Output OFF, High Z

Current

= Max. –10 +10 µA

OE > VIH, V

< VO< V

Active Power Supply Current

Average Standb y Current

Range

Ambient

Temperature V

[3]

Commercial 0°C to +70°C 5.0V ± 0.5V Industrial –40°C to +85°C 5. 0V ± 0.5V

CY7C43643/63/83

2.4 V

0.5 V

–10 +10

Com’l 100 mA Ind 100 mA Com’l 10 mA Ind 10 mA

UnitMin. Max.

µA

Capacitance

[6]

Parameter Description Te st Condi tions Max. Unit

OUT

Notes:

1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

3. Operating V

4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded.

5. All inputs = V

6. Tested initially and after any design or process changes that may affect these parameters.

range for -7 speed is 5.0V ±0.25V.

– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.

Input Capacitance TA = 25°C, f = 1 MHz,

= 3.3V

Outp u t C a pacit a nce 8 pF

4 pF

Page 7

AC Test Loads an d Waveforms (-1 0 & -15)

CY7C43643 CY7C43663

CY7C43683

OUTPUT

INCLUDING

=30 pF

JIG AND

SCOPE

R1=1.1K

Ω

R2=680

Ω

AC Test Loads and Waveforms (-7)

VCC/2

50Ω

I/O

Switching Characteristics

Parameter Description

CLK

CLKH

CLKL

ENS

RSTS

FSS

BES

SPMS

SDS

SENS

FWS

ENH

RSTH

Note:

7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

Clock Frequency, CLKA or CLKB 133 100 67 MHz Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns Pulse Duration, CLKA or CLKB LO W 3.5 4 6 ns Set-Up Time, A

before CLKB↑ Set-Up Time, CSA, W/RA, ENA, and MBA before

CLKA↑; CSB CLKB↑

Set-Up Time, MRS1/MRS2 or PRS LOW before CLKA↑ or CLKB↑

Set-Up Time, FS0 and FS1 before MRS1/MRS2 HIGH

Set-Up Time, BE/FWFT before MRS1/MRS2 HIGH

Set-Up Time, SPM before MRS1/MRS2 HIGH 5 7 7.5 ns Set-Up Time, FS0/SD before CLKA↑ 3 4 5 ns Set-Up Time, FS1/SEN before CLK A↑ 3 4 5 ns Set-Up Time, FWFT before CLKA↑ 0 0 0 ns Hold Time, A

CLKB↑ Hold Time, CSA, W/RA, ENA, and MBA after

CLKA↑; CSB Hold Time, MRS1/MRS2 or PRS LOW after

CLKA↑ or CLKB↑

= 

Ω

Over the Operating Range

before CLKA↑ and B

0–35

, W/RB, ENB, and MBB before

[7]

after CLK A↑ and B

0–35

after

, W/RB, ENB, and MBB after CLKB↑

[7]

ALL INPUT PULSES

3.0V

GND

≤

90%

10%

3ns

90%

10%

≤

ALL INPUT PULSES

3.0V

GND

3ns

≤

CY7C43643/

63/83

–7

90%

10%

CY7C43643/

63/83

–10

90%

10%

3 ns

≤

CY7C43643/

63/83

–15

3 4 5 ns

2.5 4 5 ns

6 7 7.5 ns

5 7 7.5 ns

0 0 0 ns

1 2 4 ns

UnitMin. Max. Min. Max. Min. Max.

Page 8

CY7C43643 CY7C43663

CY7C43683

Switching Characteristics

Over the Operating Range (continued)

CY7C43643/

63/83

–7

CY7C43643/

63/83

–10

CY7C43643/

63/83

–15

Parameter Description

FSH

BEH

SPMH

SDH

SENH

SPH

SKEW1

SKEW2

Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH 1 1 2 ns Hold Time, BE/FWFT after MRS1/MRS2 HIGH 1 1 2 ns Hold Time, SPM after MRS1/MRS2 HIGH 1 1 2 ns Hold Time, FS0/SD after CLKA↑ 0 0 0 ns Hold Time, FS1/SEN after CLKA↑ 0 0 0 ns Hold Time, FS1/SEN HIGH after MRS1/MRS2

0 1 2 ns

HIGH

[8]

Skew Time between CLKA↑ and CLKB↑ for EF / OR and FF

[8]

Skew Time between CLKA↑ and CLKB↑ for AE

/IR

5 5 7.5 ns

7 8 12 ns

and AF

WFF

REF

PAE

PAF

PMF

PMR

MDV

RSF

DIS

PRT

RTR

Notes:

8. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB cycle.

9. Writing data to the Mail1 register when the B

10. Writing data to the Mail2 register when the A

Access Time, CLKA↑ to A B

0–35

and CLKB↑ to

0–35

1 6 1 8 3 10 ns

Propagation Delay Time, CLKA↑ to FF/IR 1 6 1 8 2 8 ns Propagation Delay Time, CLKB↑ to EF/OR 1 6 1 8 1 8 ns Propagation Delay Time, CLKB↑ to AE 1 6 1 8 1 8 ns Propagation Delay Time, CLKA↑ to AF 1 6 1 8 1 8 ns Propagation Delay Time, CLKA↑ to MBF1 LOW

or MBF2 MBF1

Propagation Delay Time, CLKA↑ to B CLKB↑ to A

Propagation Dela y Time, MBA to A MBB to B

HIGH and CLKB↑ to MBF2 LOW or

HIGH

0–35

Valid

[10]

[9]

and

V alid an d

Propagation Delay Time, MRS1/MRS2 or PRS LOW to AE LOW and MBF1

Enable Time, CSA or W/RA LOW to A and CSB

Disable Time, CSA or W/RA HIGH to A High Impedance and CSB B

0–35

LOW, AF HIGH, FF/IR LOW, EF/OR

/MBF2 HIGH

LOW and W/RB HIGH to B

HIGH or W/RB LOW to

at High Impedance

0–35

Active

0–35

0 6 0 8 0 12 ns

1 7 2 11 3 12 ns

1 6 2 9 3 11 ns

1 6 1 10 1 15 ns

1 6 2 8 2 10 ns

1 5 1 6 1 8 ns

Retransmit Pulse W idt h 60 60 60 ns Retransmit Recovery Time 90 90 90 ns

outputs are active and MBB is HIGH.

0–35

outputs are active and MBA is HIGH.

0–35

UnitMin. Max. Min. Max. Min. Max.

Page 9

Switching Waveforms

Master Reset Loading X and Y with a Preset Value of Eight

CLKA

CLKB

MRS1 MRS2

BE/FWFT

SPM

FS1/SEN, FS0/SD

/IR

/OR

RSTS

RSF

[11]

SPMS

BES

FSS

RSTH

BEH

SPMH

FSH

FWS

CY7C43643 CY7C43663

CY7C43683

WFF

MBF1

Note:

11. PRS

RSF

must be HIGH during Master Reset.

Page 10

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

(continued)

Partial Reset (CY Standard and FWFT Modes)

CLKA

CLKB

RSTS

PRS

RSF

FF/IR

RSF

EF/

RSF

MBF1

[12]

RSTH

WFF

Parallel Program ming of the Almost Full Flag and Almost Empty Flag Offset Values after Reset

(CY Standard and FWFT Modes)

[13]

CLKA MRS1

MRS2

FSS

FSH

SPM

FSS

FSH

FS1/SEN, FS0/SD

FF/

WFF

ENS

ENH

ENA

AE Offset (X)

First Word to FIFO

0−35

Notes:

12. MRS1

13. CSA

14. t

/MRS2 must be HIGH during Partial Reset

=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.

is the minimum time between the rising CLKA edge and a rising CLKB for FF/IR to transition HIGH in the next cycle. If the time between the rising

SKEW1

edge of CLKA and rising edge of CLKB is less than t

AF Offset (Y)

, then FF/IR may transition HIGH one cycle later than shown.

SKEW1

[14]

Page 11

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

Serial Programming of the Almost Full Flag and Almost Empty Flag Offset Values (CY Standard and FWFT Modes)

(continued)

[15]

CLKA

MRS1

, MRS2

FSS

FSH

SPM

FF/IR

FSS

SPH

SENS

SENH

SENS

SENH

FS1/SEN

FS0/SD

[16]

SDS

AF Offset (Y) MSB

SDH

SDS

AE Offset (X) LSB

SDH

Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)

CLK

CLKH

CLKL

CLKB

[18]

WFF

/OR

CSB

W/RB

MBB

ENS

ENH

ENS

ENH

ENS

ENB

[17]

offset (Y) then AE offset (X).

[17]

MDV

0–35

(Standard Mode)

0–35

MDV

Previous Data

(FWFT Mode)

Notes:

15. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.

16. Programmable offsets are written serially to the SD input in the order AF

17. Read from FIFO.

18. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the boundary flag (e.g., in bursts), use CY standard mode.

No Operation

[17]

DIS

Page 12

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

(continued)

Port B W ord Read Cycle Timing for FIFO (CY Standard and FWFT Modes)

CLKB

/OR

CSB

W/RB

MBB

ENH

MDV

ENS

Previous Data

ENB

0–17

(Standard Mode)

0–17

(FWFT Mode)

Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes)

[18, 20]

[18, 19]

No Operation

DIS

CLKB

/OR

CSB

W/RB

MBB

ENB

0–8

(Standard Mode)

0–8

(FWFT Mode)

Notes:

19. Unused bytes B

20. Unused word B

HIGH

ENS

MDV

Previous Data

MDV

, B

9–17

18–35

, and B

18–26

contains all zeroes for word-size reads.

contain all zeroes for byte-size reads.

27–35

ENH

DIS

No Operation

Page 13

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

(continued)

OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)

CLK

CLKH

CLKL

CLKA

CSA W/RA

LOW

HIGH

ENS

ENH

MBA

ENS

ENH

ENA

/IR

0–35

CLKB

/OR

HIGH

FIFO Empty

[22]

SKEW1

CLKHtCLKL

CLK

REF

[18, 21]

CSB

W/RB

MBB

LOW

HIGH

LOW

ENB

0–35

Notes:

21. If Port B size is word or byte, EF

22. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output

SKEW1

register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t of the first word to the output register may occur one CLKB cycle later than shown.

Old Data in FIFO Output Register

is set LOW by the last word or byte read from the FIFO, respectively.

ENStENH

SKEW1

, then the transition of OR HIGH and load

Page 14

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

(continued)

EF Flag Timing and First Data Read F all Through when FIFO is Empty (CY Standard Mode)

CLK

CLKH

CLKL

CLKA

CSA

W/RA

LOW

HIGH

ENS

ENH

MBA

ENS

ENH

ENA

/IR

0–35

HIGH

[23]

SKEW

CLKH

CLKL

CLKB

REF

/OR

FIFO Empty

CLK

REF

[21]

CSB

W/RB

MBB

LOW

HIGH

LOW

ENB

0–35

Notes:

23. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the

SKEW1

rising CLKA edge and rising CLKB edge is less than t

ENS

ENH

, then the transition of EF HIGH may occur one CLKB cycle later than shown.

SKEW1

Page 15

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

(continued)

IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)

CLK

CLKL

CLKH

CLKB

CSB

W/RB

LOW

HIGH

MBB

ENH

ENS

ENB

/OR

0–35

HIGH

Previous Word in FIFO Output Register

SKEW1

Next Word From FIFO

[25]

CLKHtCLKL

CLKA

WFF

/IR

FIFO Full

CLK

[24]

WFF

CSA

W/RA

LOW

HIGH

MBA

ENA

0–35

Notes:

24. If Port B size is word or byte, t

25. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the

SKEW1

rising CLKB edge and rising CLKA edge is less than t

is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.

SKEW1

ENS

ENH

ENStENH

To FIFO

, then IR may transition HIGH one CLKA cycle later than shown.

SKEW1

Page 16

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

(continued)

FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode)

CLK

CLKH

CLKL

CLKB

CSB

W/RB

MBB

LOW

HIGH

LOW

ENStENH

ENB

/OR

0–35

HIGH

Previous Word in FIFO Output Register

SKEW1

Next Word From FIFO

[26]

CLKH

CLKL

CLKA

WFF

/IR

FIFO Full

CLK

WFF

[24]

CSA

W/RA

LOW

HIGH

MBA

ENA

0−35

Notes:

26. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the

SKEW1

rising CLKB edge and rising CLKA edge is less than t

ENH

ENS

ENH

tDHt

, then the transition of FF HIGH may occur one CLKA cycle later than shown.

SKEW1

Page 17

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

(continued)

Timing for AF when FIFO is Almost Full (CY Standard and FWFT Modes)

[30]

SKEW2

CLKA

ENS

ENH

ENA

[D–(Y1+1)] Words in FIFO 1

PAF

(D–Y1)Words in FIFO1

CLKB

ENB

Timing for AE

when FIFO is Almost Empty (CY Standard and FWFT Modes)

ENS

ENH

CLKA

ENS

ENH

ENA

[33]

SKEW2

CLKB

X1 Word in FIFO1

ENB

PAE

[27, 28, 29, 34]

PAF

[31, 32, 34]

(X1+1)Words in FIFO2

ENS

PAE

ENH

Notes:

27. FIFO Write (CSA read from the FIFO.

28. D = Maximum FIFO Depth 1K for the CY7C43643, 4K for the 43663, and 16K for the CY7C43683.

29. If Port B size is word or byte, t

30. t

31. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been

32. If Port B size is word or byte, AE is set LOW by the last word or byte read from FIFO, respectively.

33. t

34. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 3 clock cycles for flag assertion and deassertion. Refer to

is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the

SKEW2

rising CLKA edge and rising CLKB edge is less than t read from the FIFO.

is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the

SKEW2

rising CLKA edge and rising CLKB edge is less than t “Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.

= LOW, W/RA = HIGH, MBA = LOW), FIFO Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been

is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

SKEW2

, then AF may transition HIGH one CLKB cycle later than shown.

SKEW2

, then AE may transition HIGH one CLKB cycle later than shown.

SKEW2

Page 18

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

(continued)

Timing for Mail1 Register and M BF1

CLKA

CSA

W/RA

MBA

ENA

0–35

CLKB

MBF1

CSB

ENS

Flag (CY Standard and FWFT Modes)

ENH

ENS

ENH

PMF

ENS

[35]

PMF

W/RB

MBB

ENB

0−35

Note:

35. If Port B is configured for word size, data can be written to the Mail1 register using A valid data (B inputs). In this second case, B

will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A

18–35

0–8

FIFO Output Register

will have valid data (B

MDV

will be indeterminate).

9–35

PMR

ENS

W1 (Remains valid in Mail1 Register after read)

0–17

are “don’t care” inputs). In this first case B

18–35

ENH

0–8

9–35

DIS

will have

0–17

are “don’t care”

Page 19

CY7C43643 CY7C43663

CY7C43683

Switching Waveforms

(continued)

Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)

CLKB

ENH

ENS

CSB

ENH

ENS

W/RB

ENH

ENS

MBB

ENH

ENS

ENB

0–35

CLKA

PMF

MBF2

CSA

[36]

PMF

W/RA

MBA

ENS

ENH

ENA

MDV

PMR

W1 (Remains valid in Mail2 Register after read)

0−35

FIFO Retransmit Timing

FIFO2 Output Register

[37, 38, 39]

PRT

RTR

ENB

EF/FF

Notes:

36. If Port B is configured for word size, data can be written to the Mail2 register using B valid data (A inputs). In this second case, A

37. Clocks are free-running in this case. CY standard mode only.

38. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t

39. For the AF & AE flags, two clock cycles are necessary after t

will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B

18–35

will have valid data (A

0–8

will be indeterminate).

9–35

to update the se flags .

RTR

0–17

are “don’t care” inputs). In this first case, A

18–35

0–8

RTR

DIS

9–35

will have

0–17

are “don’t care”

Page 20

CY7C43643 CY7C43663

CY7C43683

Signal Description

Master Reset (MRS1

The FIFO memory of the CY7C436x3 undergoes a complete reset by taking its associated Master Reset (MRS1 input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset input can s witch asynchr onously to t he clocks . A Master Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FF flag (EF Almost Full flag (AF Mailbox flag (MBF1 HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. A Master Reset must be performed on the FIFO after power up, before data is written to its memory.

A LOW-to-HIGH transition on a FIFO Master Reset (MRS1 MRS2 determining the order by which bytes are transferred through Port B.

A LOW-to-HIGH transition on a FIFO reset (MRS1 input latches the values of the Flag select (FS0, FS1) and Serial Programming Mode (SPM Full and Almost Empty offset programming method (see Almost Empty and Almost Full flag offset progra mmi ng below).

Partial Reset (PRS

Each of the two FI FO memories of the CY7C436x3 under goes a limited reset by taking its associated Partial Reset (PRS input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset inputs can s witch asy nchr onous ly to the clocks. A Partial Rest initializes the internal read and write pointers and forces the Full/Input Ready flag (FF flag (EF Almost Full flag (AF Mailbox flag (MBF1 HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two clock cycles to begin normal oper ation.

Whatev er flag offset s, progr amming method (paral lel or serial), and timing mode (FWFT or IDT Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will remain unch anged upon c ompletion of the reset operation. A Par tial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be inconvenient.

Big Endian/First-Word Fall-Through (BE/FWFT

This is a dual-purpose pin. At the time of Master Reset , the BE select function is active, permitting a choice of Big or Little Endian byte arrangement for data written to or read from Port B. This selection determines the order by which bytes (or words) of data are tr ansferred th rough t his port. F or the following illustrations, assume that a byte (or word) bus size has been selected for Port B. (Note that when Port B is config ured for a long-wor d siz e, the Big En dian func tion has no appli cation and the BE input is a “Don’t Care .”

A HIGH on the BE/FWFT MRS2 arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the long-word written to Port A will be transferred to Port B first; the least

/OR) LOW, the Almost Empty flag (AE) LOW, and the

) input latches t he value of the Big Endian (BE) input or

/OR) LOW, the Almost Empty flag (AE) LOW, and the

) inputs go from LOW to HIGH will select a Big Endian

MRS2

)

, MRS2)

/IR) LOW, the Empty/Output Ready

) HIGH. A Master Reset also forces the

, MBF2) of the parallel mailbox register

, MRS2)

) inputs f or choosing the Al mo st

)

/IR) LOW, the Empty/Output Ready

) HIGH. A Partial Reset also forces the

, MBF2) of the parallel mailbox register

)

input when the Master Reset (MRS1,

significant b yte (word) of the lon g-word written to P ort A will be transferred to P ort B last.

A LOW on the BE/FWFT MRS2

) inputs go from LOW to HIGH will selec t a Little Endi an arrangement. When data is moving in the direction from Port A to Por t B, the least significant byte (word) of the long-word written to Port A will be transferred to Port B first; the most significant b yte (word) of the lon g-word written to P ort A will be transf erred to P ort B last. After Master Reset, t he FWFT select function is active, permitting a choice between two possible timing modes: CY Standard Mode or First-Word Fall-Through (FWFT) Mode. Once the Master Reset (MRS1 is HIGH, a HIGH on the BE/FWFT to-HIGH transition of CLKA will select CY Standard Mode. Thi s mode uses the Empty Flag function (EF or not there a re any wor ds present in the FIFO memory. It uses the Full Flag function (F F memory has any free space for writing. In CY Stan dar d Mode,

every word read from the FIFO, including the first, must be requested using a formal read operation.

Once the Master Reset (MRS1 on the BE/FWFT of CLKA will select FWFT Mode. This mode uses the Output Ready function (OR) to indicate whether or not there is valid data at the data outputs (B function (IR) to indicate wh ether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIF O goes direct ly to data o utputs, no read request necessary. Subsequent words must be accessed by performing a f ormal r ead operation.

)

Following Master Reset, the level applied to the BE/FWFT put to choose the desired timing mode must remain static throughout the FIFO ope ration.

Programming the Almost Empty and Almos t Full Flags

Two registers in the CY7C436x3 are used to hold the offset values for the Alm ost Empty and Almost Full flags. The Port B Almost Empty flag (AE Almost Full flag (AF each register name corre spond s with pr eset v a lues duri ng the reset of a FIFO , programmed in par allel using the FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1).

To load a FIFO’s Almost Empty fla g and Almost Ful l flag of fset registers with one of the three preset values listed in Table 1, the Serial Program Mode (SPM select inp uts must be HIG H during t he LO W -to-HIGH transiti on of its Master Reset i nput (MRS1 the preset value of 64 into X and Y, SPM be HIGH when the FIFO reset (MRS1 When using one of the preset values for the flag offsets, the FIFO can be reset simultaneously or at different times.

To prog ram the X and Y registers from Port A, perform a Master Reset on both FIFOs simultaneously with SPM FS0 and FS1 LOW during the LOW-to-HIGH transition of MRS1

/MRS2. A fte r this re se t is com ple te, the firs t two write s to the FIFO do not store data in RAM but loa d the offse t registers in the order Y and X. The Port A data inputs used by the offset registers are (A CY7C436x3, respect ivel y . The highest numbered i nput is u sed as the most significant bit of the binary number in each case. Valid programming values for the registers range from 0 to

input during the ne xt LOW -to-HI GH transi tion

input whe n the Mast er Res et (MRS1,

, MRS2) input

input at the second LOW-

) to indicate whether

) to indicate whether or not the FIFO

, MRS2) input is HIGH, a LO W

). It also uses the Input Ready

0–35

) offset regi ster i s label ed X. The Port A

) offset register is labeled Y. The index of

) and at least one of the flag, MRS2). For example , t o load

, FS0 and FS1 must

, MRS2) return s HIGH .

0–9

), (A

0–11

), or (A

0–13

in-

HIGH and

),for the

Page 21

CY7C43643 CY7C43663

CY7C43683

1023 for the CY7C43643; 0to 4095 for the CY7C43663; 0 to 16383 fo r the CY7C436 83. Bef ore p rogramm ing the o ffset register, FF

/IR is set HIGH. FIFOs begin normal operation after

programming is done. To program the X and Y registers serially, initiate a Master

Reset with SPM ing the LOW-to-HIGH transition of MRS1

LOW , FS0/SD LOW , and FS1/SEN HIGH dur-

/MRS2. After this re set is compl ete, the X and Y register v alu es are lo aded bit-wis e through the FS0/SD input on each LOW-to- H IGH tr ansition of CLKA that the FS1/SEN

input is LOW. Twenty, twenty four, or twenty eight bit writes are needed to complete the programming for the CY7C436x3, respectively. The two registers are written in the order Y then finally X. The first-bit write stores the most significant bit of the Y register and the last-bit write stores the least significant bit of the X register. Each register value can be pr og ramm ed from 0 to 1 023 f or the CY7C43 643; 0to 4095 for the CY7C43663; 0 to 16383 (Cy7c43683).

When the opt ion t o prog r am the off set r egist ers se riall y is chosen, the Port A Full/Input Ready (FF until all reg ister bits are wri tten. FF

/IR) flag remains LOW

/IR is set HIGH by the LOWto-HIGH transit ion of CLKA after the last bit is loaded to all ow normal FIFO operation.

SPM

, FS0/SD, and FS1/SEN function the same way in both

CY Standard and FWFT modes.

FIFO Write/Read Operation

The state of the Port A data (A A Chip Select (CSA The A CSA

lines are in the high-impedance state when either

0–35

or W/RA is HIGH. The A

) and Port A Write/Read Select (W/RA).

ister outputs when both CSA Data is loaded int o the FIFO from the A

to-HIGH transi tion of CLKA when CSA ENA is HIGH, MBA is LOW, and FF

) lines is controlled by Port

0–35

lines are active mail 2 reg-

0–35

and W/RA are LOW.

inputs on a LOW-

0–35

is LOW, W/RA is HIGH,

/IR is HIGH (see Table 2). FIFO writes on Port A are indepe ndent of any concurrent P ort B operation.

The Port B control signals are identical to those of Port A with the exception that the Port B Write/Read Select (W inverse of the Port A Write/Read Select (W/RA the Port B data (B Select (CSB

) and Port B Write/Read Select (W/RB). The B

) lines is controlled by the Port B Chip

0–35

lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B when CSB

is LOW and W/RB is HIGH.

Data is read from the FIFO to the B HIGH transition of CLKB when CSB ENB is HIGH, MBB is LO W, and EF

lines are active outputs

0–35

outputs by a LOW-to-

0–35

is LOW, W/RB is HIGH,

/OR is HIGH (see Table 3).

/RB) is the

). The state of

0–35

FIFO reads and writes on Port B are independent of any concurrent Port A operation.

The set-up and hold time constraint s to the port clocks for the port Chip Selects and Write/Rea d Selects are only for enab ling write and read operations and are not related to highimpedance co ntrol of th e data out puts . If a po rt enable is LO W during a clock cycle, the port’s Chip Select and Write/Read Select may ch ange states duri ng the set-up an d hold time window of the cycle .

When operating the FIFO in FWFT Mode with the Output Ready flag LO W, the ne x t word written i s autom atica lly sent t o the FIFO’s output register by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH, data residing in the FIFO’s mem ory arra y i s cloc ked to the ou tput r eg-

ister only when a read is sel ected usi ng the p ort’s C hip Select , Write/Read Select, Enab le, and Mailbox Select.

When operating the FIFO in CY Standar d Mode , r egardle ss o f whether the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is clocked to the output register only when a read is selected using the port’s Chip Sele ct, Writ e/ Read Select, Enable, and Mailbox Select.

Synchronized FIFO Fl ags

Each FIFO is synchronized to its port clock through at least two flip-fl op st ages . Thi s is d one t o impr ov e f lag-s ignal re liabil ity by reducing the probability of the metastable events when CLKA and CLKB operate asynchronously to one another. EF OR and AE

are synchroniz ed to CLKA. FF/IR and AF are synchronized t o CLKB . Table 4 shows the relations hip of ea ch port flag to the FIFO.

Empty/Output Ready Fla gs (EF

/OR)

These are dual-purpose flags. In the FWFT Mode, the Output Ready (OR) function is sel ected. When the Out put Ready fl ag is HIGH, new dat a is prese nt in the FIFO out put regi ster . When the Output Ready flag is LOW, the previous data word is present in the FIFO output register and attempted F IFO reads are ignored.(See footnote #18)

In the CY Standard Mode, the Empty Flag (EF

) function is selected. When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory for reading to the output register. When the Empty Flag is LOW, the previous data word is present in the FIFO output register and attempted F IFO reads are ignored.

The Empty/Output Ready f lag of a FIFO is synchr onized to the port clock that reads data from its array. For both the FWFT and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2.

In FWFT Mode, from t he time a wor d is written t o a FIFO , it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three cycles hav e not elapsed s ince the ti me the word w as written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously for cing t he Outp ut Ready flag HI GH and shi fting the word to the FIFO output register.

In the CY Standard Mode , f rom the time a word is written to a FIFO, the Empty Flag will indicate the presence of data available for reading in a m inimum of two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is th e next data to be sent to the FIFO output register and two cycles have not elapsed since the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occur s , forcing the Em pty Fl ag HIGH; onl y the n ca n data be read.

A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t

SKEW1

or grea ter after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle.

Page 22

CY7C43643 CY7C43663

CY7C43683

Full/Input Ready Flags (FF

/IR)

This is a dual-purpose flag. In FWFT Mode, the Input Ready (IR) function is selected. In CY Standard Mode, the Full Flag (FF

) function is selected. For both timing modes, when the Full/Input Read y flag i s HIGH, a mem ory locatio n is fr ee in th e SRAM to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored.

The Full/Input Read y flag of a FIFO is synchr onized to the port clock that writes data to its arra y. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its write pointer is inc rement ed. The st ate machi ne that cont rols a Full/ Input Ready flag monitors a write pointer and read pointer comparator t hat indicates when the FIFO SRAM status is f ull , full–1, or full–2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/ Input Ready flag HIGH.

A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t read. Otherwise, the subsequent clock cycle can be the first

or greater after the

SKEW1

synchronization cycle.

Almost Empty Flags (AE

)

The Almost Empty flag of the FIFO is synchronized to port B clock. The state machine that controls an Almost Empty flag monitors a write p ointer and read poi nter comparat or that indi cates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The Almost Empty state is defined by th e contents of register X for AE

. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Empty flag is LOW when i ts FIFO conta ins X or less wor ds and is HIGH when its FIFO contains (X+1) or more words. (See footnote #34)

Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost Empty flag to reflec t the new le v e l of fill. Ther ef or e, the Almost empty flag of a FIFO containing (X+1) or more words remains LOW if tw o cycles of its synchronizing clock ha ve not elapsed since the write that filled the memory to the (X+1) level. An Almost Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the ( X+1) le vel. A LOW -to- HIGH transi tion of an Almost Empty flag synchronizing clock begins the first synchro nizat ion cycl e if it oc curs at time t the write that fills t he FIFO to (X+1) wor ds. Other wise, the sub-

or gr eat er af ter

SKEW2

sequent synchronizing clock cycle may be the first synchronization cycle.

Almost Full Flags (AFA

, AFB)

The Almost Full flag of the FIFO is synchronized to port A clock. The st ate machine that control s an Almost Full flag monitors a write pointer and re ad pointer compar ator that ind icates when the FIFO SRAM status is almost full, almost full–1, or

almost full–2. The Almost Full state is defined by the contents of register Y for AF. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almos t Empty flag and Almost Full fl ag offset programming above). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024–Y), (409 6–Y), or (16384 –Y) for the CY7C436x3 respec tively. An Almost Full flag is HIGH when the number of words in its FIFO is less t han or equal to [1024 –(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for the CY7C436x3 respectively.(See footnote #34)

Two LOW-to-HIGH transitions of the Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing [1024/4096/16384–(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in mem ory to [102 4/40 96/16384–(Y+1)]. An A lm ost F ull flag is set HIGH by the second LOW-to-HIGH transition of its synchronizin g cloc k after the FI FO read t hat reduces the n umber of words in memory to [1024/4096/16384–(Y+1)]. A LOWto-HIGH transition of an Almost Full flag synchronizing clock begins the fi rst synchroni zation cy cle if i t occurs at time t or greater after the read that reduces the number of words in

SKEW2

memory to [1024/4096/16384–(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle.

Mailbox Registers

Each FIFO has a 36-bit bypass regist er to pass command and control information between P ort A and P ort B without put ti ng it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usable wi dth of both the Mail1 and Mail2 registers matches the sel ected bus size for Port B.

A LOW-to-HIGH transition on CLKA writes A

data to the

0−35

Mail1 Register when a Port A write is selected b y CSA, W/RA and ENA with MBA HIGH. If the selected Por t A bus size is also 36 bits, then the usable width of the Mail1 Register employs d ata li nes A then the usabl e widt h of the Mai l1 Regi ster empl o ys dat a li nes A

. (In this case, A

0−17

. If the select ed P ort A bus size is 18 bi ts,

0–35

are “don’t care” inputs.) If the se-

18–35

lected Port A bus size is 9 bits, then the usable width of the Mail1 Register emplo ys data lines A “don’t care” inputs.)

A LOW-to-HIGH transition on CLKB writes B Mail2 register when a P ort B write is selected b y CSB

. (In this case, A

0–8

0−35

are

9–35

data to the

, W/RB, and ENB with MBB HIGH. If the selected Por t B bus size is also 36 bits, then the usable width of the Mail2 Register employs d ata li nes B

. If the select ed P ort B bus size is 18 bi ts,

0–35

then the usable width of the Mail2 register employs data lines B

. (In this ca se, B

0–17

lected Port B bus size is 9 bits, then the usable width of the Mail2 Register emplo ys data lines B “don’t care” inputs.)

are “don’t care” inputs.) If the se-

18–35

. (In this case, B

0−8

9−35

are

Writing data to a mail register sets its corresponding flag (MBF1

or MBF2) LOW. Attempted writes to a mail register are

ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus

comes from the FIFO output register when the port Mailbox Select input is LOW and from the mail register when the port Mailbox Select input is HIGH.

Page 23

CY7C43643 CY7C43663

CY7C43683

The Mail1 Register flag (MBF1

) is set HIGH by a LOW-toHIGH transition on CLKB when a Port B read is selected by CSB

, W/RB, and ENB with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B size, 18 bit s of m ailb ox d ata are pl aced on B B

are indeterminate.) For a 9-bit bus size, 9 bits of mail-

18–35

box data are placed on B

. (In this cas e, B

0–8

. For an 18-bi t bus

0–35

. (In thi s case ,

0–17

are indeter-

9–35

minate.) The Mail2 Register flag (MBF2

) is set HIGH by a LOW-toHIGH transition on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA HIGH.

For a 36-bit bus size, 36 bits of mailbox data are placed on A

. For an 18-bit bu s size, 18 bit s of mailbox data are pl aced

0–35

on A bus size, 9 bits of mailbox data are placed on A case, A

. (In this c ase, A

0–17

are indeterminate.)

9–35

are indeterminate.) For a 9-bit

18–35

. (In this

0–8

The data in a mail register remains intact after it is read and changes only when new data is written to the register. The Endian Select feature has no effect on the mailbox data.

Bus Sizing

The Port B bus can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data read from FIFO. The levels applied to the Port B Bus Size Select (SIZE) and the Bus Match Select ( BM) determine the P ort B bu s size. The se le vels should be static throughout FIFO operation. Both bus siz e selections are implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH.

Two different methods for sequencing data transfer are available for Port B when the bus size selection is either byte-or word-siz e . The y are ref er red t o as Big End ian ( most si gn ificant byte first) and Little Endian (least significant byte first). The level applied to the Big Endian Select (BE) input during the LOW-to-HIGH transition of MRS1

/MRS2 selects the endian method that will be acti v e during F IFO oper ation. BE is a don’t care input when the bus size selected for Port B is long-word. The endian method is implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH.

Only 36-bit long-word data is written to or read from the two FIFO memories on th e CY7C436 x3. Bus- matc hing ope rati ons are done aft er data i s read f rom the FI FO. These b us-match ing operation s are not av ailab le when t ransf erring d ata via mai lbox

registers. Furthermore, both the word- and byte-size bus selections limit the width of the dat a bus that can be used fo r mail register opera ti ons. In thi s case , only t hose b yte lan es belong ing to the selected word- or byte-size bus can carry mailbox data. The remaining data outputs will be indeterminate. The remaining data inputs will be don’t care inputs. For example, when a word-size bus is selected, then mailbox data can be transmitted only between A bus is select ed, then mai lbo x da ta can be tr ans mitted only between A

0–8

and B

0–8

0–17

and B

. When a byte-size

0–17

Bus-Matching FIFO Reads

Data is read from the FIFO RAM in 36-bit long-word increments. If a long-w ord bus s ize is implement ed, t he ent ire long word imm ed ia tel y sh if ts t o th e FIF O ou t put re gi ste r. If byte or word size is implemented on Port B, only the first one or two bytes appear on the se lected portion of the FIFO out put reg ister, with the rest of the long-word stored in auxiliary registers. In this case, subsequent FIFO reads output the rest of the long-word to the FIFO output register.

When reading data from the FIFO in the byte or word format, the unused B

Retransmit (RT

outputs are indeterminate.

0–35

)

The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. Retransmit function applies to CY standar d mo de only.

The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least o ne wor d has be en read si nce the l ast rese t cycle. A LOW pulse on RT

resets the internal read pointer to the first phy sical locat ion of the FIFO . CLKA and CLKB ma y be free-running but ENB must be disabled during and t

RTR

after the retrans mit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented unt il it is equ al to the write po inter. Flags ar e g overned by the relative locations of the read and write pointers and are updated duri ng a retransmit cycle. Data written to the FIFO after activation of RT

are transmit ted als o . The full depth

of the FIFO can be repeatedly tr ansmitted.

Page 24

CY7C43643 CY7C43663

CY7C43683

BYTE ORDER ON PORT A:

BE BM SIZE

XLX

BE BM SIZE

HHL

BE BM SIZE

LHL

BE BM SIZE

HHH

27–35

18–26

9–17

(a) LONG WORD SIZE

27–35

18–26

9–17

A B

27–35

18–26

9–17

C D

(b) WORD SIZE – BIG ENDIAN

27–35

18–26

9–17

27–35

18–26

9–17

27–35

18–26

(d) BYTE SIZE – BIG ENDIAN

9–17

0–8

Write to FIFO

Read from FIFO

1st: Read from FIFO

0–8

2nd: Read from FIFO

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

0–8

3rd: Read from

FIFO

0–8

4th: Read from

FIFO

BE BM SIZE

LHH

27–35

18–26

9–17

(e) BYTE SIZE – LITTLE ENDIAN

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

0–8

3rd: Read from

FIFO

0–8

4th: Read from

FIFO

Page 25

CY7C43643 CY7C43663

CY7C43683

Table 1. Flag Programming

SPM FS1/SEN FS0/SD MRS1

H H H H H L H L H H L L

L H L

L H H L L H L L L

[34]

MRS2

↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑

X and Y Registers

64 16

Parallel programming via Port A

Serial programm ing via SD

Reserved Reserved Reserved

Table 2. Port A Enable Function

CSA W/RA ENA MBA CLKA A

Outputs Port Function

0–35

H X X X X In high-impedance state None

L H L X X In high-impedance state None LHHL LHHH

↑ ↑

In high-impedance state FIFO write

In high-impedan ce state Mail1 write L L L L X Active, Mail2 register None LLHL

↑

Active, Mail2 register None L L L H X Active, Mail2 register None LLHH

↑

Active, Mail2 register Mail2 read (set MBF2

[



]

HIGH)

Table 3. Port B Enable Function

CSB W/RB ENB MBB CLKB B

Outputs Port Function

0–35

H X X X X In high-impe dance state None

L L L X X In high-impe dance state None LLHL LLHH

↑ ↑

In high-impedance state None

In high-impedance state Mail2 write L H L L X Active, FIFO output regi ster None LHHL

↑

Active, FIFO output register FIFO read L H L H X Active, Mail1 reg ister None LHHH

Note:

40. X register holds the offset for AE

; Y register holds the offset for AF.

↑

Active, Ma il 1 register Mail1 read (set MBF1

HIGH)

Page 26

CY7C43643 CY7C43663

CY7C43683

Table 4. FIFO Flag Operation (CY Standard and FWFT Modes)

Number of Wo rds in FIFO Memory

[41, 42, 43 , 44]

[34]

Synchronized to CLKB Synchronized to CLKA

CY7C43643 CY7C43663 CY7C43683 EF/OR AE AF FF/IR

0 0 0 L L H H

1 TO X1 1 TO X1 1 TO X1 H L H H

(X1+1) to

[1024–(Y1+1)]

(X1+1) to

[4096–(Y1+1)]

(X1+1) to

[16384–(Y1+1)]

H H H H

(1024–Y1) to 1023 (4096–Y1) to 4095 (16384–Y1) to 16383 H H L H

1024 4096 16384 H H L L

Table 5. Data Size for FIFO Long-Word Reads

Size Mode

[45]

BM SIZE BE A

27–35

Data Written to FIFO Data Read From FIFO

18–26

9–17

0–8

27–35

18–26

9–17

LXXABCDABCD

Table 6. Data Size for Word Reads

Size Mode

BM SIZE BE A

[45]

27–35

Data Written to FIFO Read No. Data Read From FIFO

18–26

9–17

0–8

9–17

HLHABCD1AB

2CD

HLLABCD1CD

2AB

0–8

Table 7. Data Size for Byte Reads from FIFO

Size Mode

[45]

BM SIZE BE A

27–35

Data Written to FIFO Read No.

18–26

9–17

0–8

Data Read From

FIFO

0–8

HHHABCD1 A

2B 3C 4D

HHLABCD1 D

2C 3B 4A

Notes:

41. X is the Almost Empty offset for FIFO used by AE programming.

42. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

43. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT Mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.

44. The OR and IR functions are active during FWFT mode; the EF

45. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

. Y is the Almost Full offset for FIFO used by AF. Both X and Y are selected during a FIFO reset or port A

and FF functions are active in CY Standard Mode.

Page 27

CY7C43643 CY7C43663

CY7C43683

Ordering Information

1K x36 Unidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns) Ordering Code

7 CY7C43643–7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43643–10AC A128 128-Lead Thin Quad Flat Package Commercial 15 CY7C43643–15AC A128 128-Lead Thin Quad Flat Package Commercial

4K x36 Unidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns) Ordering Code

7 CY7C43663–7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43663–10AC A128 128-Lead Thin Quad Flat Package Commercial 15 CY7C43663–15AC A128 128-Lead Thin Quad Flat Package Commercial

Package

Name

Package

Name

Package

Type

Package

Type

Operating

Range

Operating

Range

16K x36 Unidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns) Ordering Code

7 CY7C43683–7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43683–10AC A128 128-Lead Thin Quad Flat Package Commercial 15 CY7C43683–15AC A128 128-Lead Thin Quad Flat Package Commercial 15 CY7C43683–15AI A128 128-Lead Thin Quad Flat Package Industrial

Document #: 38-00699-D

Package

Name

Package

Type

Operating

Range

Page 28

Package Diagram

CY7C43643 CY7C43663

CY7C43683

128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128

51-85101-A

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Datasheet CY7C43683-7AC, CY7C43663-7AC, CY7C43663-15AC, CY7C43663-10AC, CY7C43683-15AC Datasheet (Cypress Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual