Datasheet CY7C43662AV-7AC, CY7C43662AV-15AC, CY7C43662AV-10AC, CY7C43682AV-7AC, CY7C43682AV-15AC Datasheet (Cypress Semiconductor)
...Page 1
V
CY7C43642AV
PRELIMINARY
CY7C43662AV/CY7C43682A V
3.3V 1K/4K/16K x36 x2 Bidirectional
Synchronous FIFO
Features
• 3.3V high-speed, l ow-power, bidirectional, First-I n FirstOut (FIFO ) me mories
• 1K x36 x2 (CY7C43642AV)
• 4K x36 x2 (CY7C43662AV)
• 16K x36 x2 (CY7C43682AV)
• 0.25-micr on CMOS for optimum speed/power
• High-speed 133- MHz operat ion (7.5- ns read /write c ycle
times)
• Low power
= 60 mA
—I
CC
= 10 mA
—I
SB
Logic Block Diagram
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Par all el Programmable Al mo st Full and Almost Empty
flags
• Ret ra n smit function
• Standard or FW FT user selectable mode
• 120-pin TQFP packaging
• Easily expandable in width and depth
CLKA
CSA
W/RA
ENA
MBA
RT2
MRST1
FFA/IRA
AFA
FS0
FS1
A
0–35
EFA/ORA
AEA
Por t A
Control
Logic
FIFO1,
Mail1
Reset
Logic
Input
Register
Programmable
Flag Offset
Registers
Output
Register
Write
Pointer
Write
Pointer
Mail1
Register
1K/4K/16K
x36
Dual Ported
Memory
(FIFO1)
Status
Flag Logic
Status
Flag Logic
1K/4K/16K
x36
Dual Ported
Memory
(FIFo2)
Read
Pointer
Timing
Mode
Read
Pointer
Input
Output
Register
MBF1
CLKB
Port B
Control
Register
Logic
FIFO2,
Mail2
Reset
Logic
CSB
W/RB
ENB
MBB
RT1
EFB/ORB
AEB
B
0–35
FWFT/STAN
FFB/IRB
AFB
MRST2
MBF2
Cypress Semiconductor Corporation
Mail2
Register
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 14, 2000
Page 2
CY7C43642AV
Pin Configuration
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT/STAN
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
RT2
A
12
PRELIMINARY
CY7C43662AV/CY7C43682A V
TQFP
Top View
EFB/ORB
VCCEFA/ORA
FFA/IRA
CSA
W/RA
ENA
CLKA
GND
120
119
118
117
116
115
1
114
113
AFA
112
AEA
111
MBF2
110
MBA
109
MRST1
108
FS0
107
106
GND
MBB
MRST2
FS1
105
104
103
2
3
4
5
6
7
8
9
10
11
12
CY7C43642AV
13
14
15
16
17
CY7C43662AV
CY7C43682AV
18
19
20
21
22
23
24
25
26
27
28
29
30
3132333435363738394041424344454647484950515253545556575859
AFB
AEB
VCCMBF1
999897969594939291
102
101
100
FFB/IRB
W/RB
VCCCLKB
ENB
CSB
GND
90
B
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
RT1
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
60
3
9
11
A10A
GND
5
A6A7A8A
GND
2
A
A4A
CC
V
0
A0A1A
GND
B5B4B3B2B1B
GND
8
6
B
9B7
10
B
B
CC
V
B11B
2
Page 3
CY7C43642AV
PRELIMINARY
Functional Description
The CY7C436X2AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous FIFO memory which supports clock frequencies up to 133 MHz and has read access
times as fast as 6 ns. Two independent 1K/4K/16K x 36 dualport SRAM FIFOs on board each chip buffer data in opposite
directions.
The CY7C436X2AV is a synchronous (clocked) FIFO, meaning each port emplo ys a sync hron ous int erf ace . All data t ransfers th rough a port are gate d to the LO W - to-HI GH trans iti on of
a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a
simple bidi rectional i nterfac e between microproces sors and/or
buses with synchronous control.
Communication b etw een each port ma y b ypas s the FIF Os via
two mailbox registers. The mailbox registers’ width matches
the selected P ort B bus width. Each mailbo x register has a f lag
(MBF1
and MBF2) to signal when new mail has been stored.
Master Reset initializes the read and write pointers to the first
location of the memory array, and selects parallel flag programming, or one of the three possible default flag offset settings, 8 , 16, o r 64. Eac h FIFO has it s ow n indep endent M aster
Reset pin, MRST1
The CY7C436X2AV have two modes of operation: In the CY
Standard Mode, the first word written to an em pty FIFO is deposited into the memory array. A read operation is required to
access that word (along with all other words residing in memory). In the First-Word Fall-Through Mode (FWFT ), the firs t
word (36-bi t wide) writ ten to an empty FIFO appe ars automatically on the output s, no read operati on required (nev ertheless,
accessing subsequent words does necessitate a formal read
request). The state of the FWFT
ation determines the mode in use.
and MRST2.
/STAN pin during FIFO oper-
CY7C43662AV/CY7C43682A V
Each FIFO has a combined Empty/Output Ready flag (EFA
ORA and EFB
(FFA
/IRA and F FB/IRB). The EF a nd FF func tions ar e select ed
in the CY Standard Mode. EF
is full or not. The IR and OR functions are sele cted in the First Word F all- Through Mode. IR indi cates whet her or not the FIFO
has ava il able memory locations. OR shows whether the FIFO
has data available for reading or not. It marks the pres ence of
valid data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA
AEB
) and a programmable Almost Full flag (AFA and AFB).
AEA
and AEB indicate when a selected number of words written to FIFO memory achieve a predetermined “almost empty
state.” AFA
words written t o the m emory achi ev e a predet ermined “almost
full sta te” (see Note 34).
IRA, IRB, AFA
writes data into its array. ORA, ORB, AEA
chronized to th e port clock that reads data from its array. Programmable offset for AEA
parallel usi ng P ort A. Three defa ult offs et settings are also pro vided. The AEA
locations from the empty boundary and AFA
old can be set at 8, 16, or 64 locations from the full boundary.
All these cho ices ar e made using the FS0 and FS1 i npu ts dur ing Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If at any time the FIFO i s not activ ely performing a
function, the chip will automatically power down. During the
Power Down state, supply current consumption (I
minimum. Init iating any oper ati on (b y act iv atin g contr ol inputs )
will immediately take the device out of the Power Down state.
The CY7C436X4AV FIFOs are characterized for operation
from 0°C to 70°C commercial, and f rom –40°C to 85°C industrial. Input ESD prot ection is greater than 2001V, and latch-up
is prevented by the use of guard rings.
/ORB) and a combined Full/Input Ready flag
indicates whether the memory
and
and AFB indicate when a selected number of
, and AFB are synchro nized to the port clock tha t
, and AEB are syn-
, AEB, AFA, and AFB are loaded in
and AEB threshold can be set at 8, 16, or 64
and AFB thresh-
) is at a
CC
/
Selectio n Gu ide
CY7C43642/
62/82AV
7
Maximum Frequency (MHz) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enable Hold (ns) 0 0 0
Maximum Flag Delay (ns) 6 8 10
Active Power Supply
Current (I
Density 1K x 36 x2 4K x 36 x2 16K x 36 x2
Package 120 TQFP 120 TQFP 120 TQFP
CC1
) (mA)
Commercial 60 60 60
Industrial 60
CY7C43642AV CY7C43662AV CY7C43682AV
CY7C43642/
62/82AV
10
-
CY7C43642/
62/82AV
15
-
3
Page 4
CY7C43642AV
PRELIMINARY
CY7C43662AV/CY7C43682A V
Pin Definitions
Signal Name Description I/O Function
A
0–35
AEA
AEB
AFA
AFB
B
0–35
/STAN First-Word Fall-
FWFT
CLKA Port A Clock I CLKA is a continuous clock t hat synchr onizes al l data t ransf ers thro ugh Port A a nd can
CLKB Port B Clock I CLKB is a continuous clock t hat synchr onizes al l data t ransf ers thro ugh Port B a nd can
CSA
CSB
/ORA Port A Empty/
EFA
EFB
/ORB Port B Empty/
ENA Port A Enable I ENA must be HIGH to enable a L O W -to- HIGH tra nsition of CLKA to rea d or write dat a
ENB Port B Enable I ENB must be HIGH to enable a L O W -to- HIGH tra nsition of CLKB to rea d or write dat a
FFA
/IRA Port A Full/Input
/IRB Port B Full/Input
FFB
Port A Data I/O 36-bit bidirectional data port for side A.
Port A Almost
Empty Flag
Port B Almost
Empty Flag
Port A Almost
Full Flag
Port B Almost
Full Flag
Port B Data I/O 36-bit bidirect ional data port for side B.
Through / CY
Standard Select
Port A Chip
Select
Port B Chip
Select
Output Ready
Flag
Output Ready
Flag
Ready Flag
Ready Flag
O Programmab le Almost Empty flag sy nchroni zed to CLKA. It is LO W when the numb er
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2 (see Note 34).
O Programmab le Almost Empty flag sync hroni zed to CLKB . It is LO W when the nu mber
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1 (see Note 34).
O Programmab le Almost Full flag synchronized t o CLKA. It is LO W when the number of
empty locations in FIFO1 is less than or equal to the value in the Almost Full A of fset
register, Y1 (see Note 34).
O Programmab le Almost Full flag synchronized t o CLKB. It is LOW when the number of
empty locations in FIFO2 is less than or equal to the value in the Almost Full B of fset
register, Y2 (see Note 34).
I D urin g M a ster Reset. A H IG H on FWFT
First -Wor d F a ll- Through m ode. Once t he timi ng mo de has be en se lecte d, the l ev el on
FWFT
/STAN must be static throughout device operation.
be asynchronous or coincident to CLKB. FFA
synchronized t o the LOW-to-HIGH transition of CLKA.
be asynchronous or coincident to CLKA. FFB
synchronized t o the LOW-to-HIGH transition of CLKB.
ICSA must be LOW to enable a LO W-to HIGH transition of CLKA to read or write on
Port A. The A
ICSB must be LOW to enable a LO W-to HIGH transition of CLKB to read or write on
Port B. The B
O This is a dual -function pin. In the CY Stand ard Mode , the EF A
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is select ed. ORA indicates the presence of valid data on A
able for reading. EFA
O This is a dual-funct ion pin. In the CY Standard Mode, the EFB functio n is selected. EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is select ed. ORB indicates the presence of valid data on B
able for reading. EFB
on Port A.
on Port B.
O This is a dual-fu nction pi n. In the CY Stand ard Mode, the FFA function is sele cted. FF A
indicates whether or not t he FIFO1 memory is full. In the FWFT mode , the I RA function
is selected. IRA indicat es whether or not there is space av ailable fo r writing to the FIFO1
memor y. F FA
O This is a du al-functio n pin. I n the CY St andard M ode, th e FFB funct ion is selected. FFB
indicates whether or not t he FIFO2 memory is full. In the FWFT mode , the I RB function
is selected. IRB indicat es whether or not there is space av ailable fo r writing to the FIFO2
memor y. F FB
outputs are in the high-impedance state when CSA is HIGH.
0–35
outputs are in the high- impedance state when CSB is HIGH.
0–35
/ORA is synchronized to t he LOW-to-H IGH tr ansition of CLKA.
/ORB is synchronized to t he LOW-to- HIGH tr ansition of CLKB.
/IRA is syn ch r on i ze d to th e LOW-to- HIG H tra n s iti o n o f CLK A .
/IRB is syn ch r on i ze d to th e LOW-to- HIG H tra n s iti o n o f CLK B.
selects CY Standard mode , a LOW selects
/IRA, E FA/ORA, AFA, and AEA are all
/IRB, EFB /ORB, AFB, and AEB are all
function is selected. EF A
outputs avail-
0–35
outputs avail-
0–35
4
Page 5
CY7C43642AV
PRELIMINARY
Pin Definitions
Signal Name Description I/O Function
FS1 Flag Offset
FS0 Flag Offset
MBA Port A Mailbox
MBB Port B Mailbox
MBF1
MBF2
MRST1
MRST2
RT1
RT2
W/RA
RB Port B Write/
W/
(continued)
Select 1
Select 0
Select
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
FIFO2 Master
Reset
Retransmit
FIFO1
Retransmit
FIFO2
Port A Write/
Read Select
Read Select
I The LOW-to- HIGH transition of a FIFO’s reset i nput lat ches the values of F S0 and FS 1.
If either FS0 or FS1 is HIGH when a reset input goes HIGH, one of the three preset
values (8, 16, or 64) is selected as the offset f or the FIFO’s Almost Ful l and Almost
I
Empty flags. If both FIFOs res et simultaneo usly and both FS0 and FS1 are LOW when
MRST1
both FIFOs.
I A HIGH lev el on MBA chooses a mailbox register for a Port A read or write operation.
When the A
register for output and a LOW level selects FIFO2 output register data f or output.
I A HIGH lev el on MBB chooses a mailbox register for a Port B read or write operation.
When the B
register for output and a LOW level selects FIFO1 output register data f or output.
OMBF1 is set LOW by a LOW-to-HIGH trans it ion of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1
HIGH by a LOW- to-HI GH transi tion of CLKB when a P ort B read is selected and MBB
is HIGH. MBF1
OMBF2 is set LOW by a LOW-to-HIGH trans it ion of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2
HIGH by a LOW- to-HI GH transi tion of CLKA when a P ort A read is selected and MBA
is HIGH. MBF2
I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on M
selects the prog ramming method (serial or paral lel) and one of three program m able
flag default of fsets for FIFO1. Four LOW-to-HIGH transition s of CLKA and f our LOWto-HIGH transitions of CLKB must occu r w h ile M
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to al l zeroes. A LOW pulse on MRST2
selects one of th ree programmable f lag default off sets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW -to-HIGH transitions of CLKB must occur while
MRST2
I A LOW strobe on this pin will retransmit the data on FIFO1. This is achie ved by bringi ng
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
I A LOW strobe on this pin will retransmit the data on FIFO2. This is achie ved by bringi ng
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
I A HIGH selects a write operation and a LOW selects a read operat ion on Port A for a
LOW-t o-HIGH transition of CLKA. The A
when W/RA
I A LOW selects a write operation and a HIGH selects a read operation on Port B for a
LOW-to-HIGH transition of C L K B. The B
when W
and MRST2 go HIGH, the first four writes to FIFO1 Almost Empty offsets for
outputs are active, a HIGH lev el on MBA selects data from the Mail2
0–35
outputs are active, a HIGH lev el on MBB selects data from the Mail1
0–35
is set HIGH followi ng either a Master or Partial Reset of FIFO1.
is set HIGH followi ng either a Master or Partial Reset of FIFO2.
is LOW.
is HIGH.
/RB is LOW.
CY7C43662AV/CY7C43682A V
0–35
0–35
is LOW. MBF1 is set
is LOW. MBF2 is set
RST1
RST1 is LOW.
outputs are i n the high-impedance st ate
outputs are in the high-impedance state
5
Page 6
CY7C43642AV
PRELIMINARY
Maximum Ratings
[1]
(Abov e which the useful life m ay be impaired. F or user guidelines, not tested.)
Storage Temperature .................... .............. .–65
°
C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125
°
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
Electrical Characteristics
[2]
......................................–0.5V to VCC+0.5V
[2]
...................................–0.5V to VCC+0.5V
Over the Operating Range
Parameter Description Tes t Condi ti ons
V
V
V
V
I
IX
I
OZL
I
OZH
I
CC1
I
SB
OH
OL
IH
IL
[4]
[5]
Output HIGH Voltage VCC = 3.0V,
I
= –2.0 mA
OH
Output LO W Voltage VCC = 3.0V,
I
= 8.0 mA
OL
Input HIGH Voltage 2.0 V
Input LOW Voltage –0.5 0.8 V
Input Leakage Curr ent V
Output OFF, High Z
= Max. –10 +10 µA
CC
VSS < VO< V
Current
Active Power Supply
Current
Average Standby
Current
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......... ............. .. .. ............. ...>2001V
(per MIL-STD-883, Method 3015)
Latch -U p Cu rre n t.............. .......... ......... .......... .......... . >200mA
Operating Range
C
CY7C43662AV/CY7C43682A V
Range
Temperature V
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
CY7C43642/62/82AV
2.4 V
0.5 V
Ambient
CC
CC
–10 +10
Com’l 60 mA
Ind 60 mA
Com’l 10 mA
Ind 10 mA
CC
[3]
UnitMin. Max.
V
µA
[6]
Capacitance
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Operating V
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
5. All inputs = V
6. Tested initially and after any design or process changes that may affect these parameters
Range for -7 speed is 3.3V ± 5%.
CC
– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
CC
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.3V
Outp u t C a pacit a nce 8 pF
CC
4 pF
6
Page 7
CY7C43642AV
PRELIMINARY
CY7C43662AV/CY7C43682A V
AC Test Loads and Waveforms (-10 & -15)
3.3V
OUTPUT
CL=30 pF
INCLUDING
JIG AND
SCOPE
Ω
[8]
R2=680
Ω
3.0V
GND
≤
3ns
ALL INPUT PULSES
90%
10%
90%
10%
3 ns
≤
R1=330
AC Test Loads and Waveforms (-7)
VCC/2
3.0V
GND
≤
3ns
I/O
Z0=50
Ω
Switching Characteristics
50Ω
Over the Operating Range
Parameter Description
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
RSTS
t
FSS
Clock Fr equency, CLKA or CLKB 133 100 67 MHz
Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
Set-Up Time, A
CLKB↑
before CLK A↑ and B
0–35
0–35
before
Set-Up Ti me , CSA , W/RA, ENA, and MBA before CLKA↑;
CSB
, W/RB, ENB, and MBB before CLKB↑
Set-Up Time, MRST1 or MRST2 LOW bef ore CLKA↑ or
[7]
CLKB↑
Set-Up Time, FS0 and FS1 before MRST1 and MRST2
HIGH
t
FWS
t
DH
t
ENH
t
RSTH
t
FSH
t
SPH
t
SKEW1
Notes:
7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
8. C
L
9. Ske w time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
Set-Up Time, FWFT bef ore CLKA↑ 0 0 0 ns
Hold Time, A
after CLKA↑ and B
0–35
after CLKB↑ 0 0 0 ns
0–35
Hold Time, CSA, W /RA, ENA, and MBA after CLKA↑;
CSB
, W/RB, ENB, and MBB after CLKB↑
Hold Time, MRST1 or MRST2 LOW after CLKA↑ or
[7]
CLKB↑
Hold Time, FS0 and FS1 after MRST1 and MRST2 HIGH 1 1 2 ns
Hold Time, FS1 HIGH after MRST1 and MRST2 HIGH 0 1 2 ns
[9]
Skew Time between CLKA↑ and CLKB↑ for EFA/ORA,
EFB
/ORB, FFA/IRA, and FFB/IRB
= 5 pF for t
DIS
.
ALL INPUT PULSES
-10
90%
10%
≤
CY7C43642/
62/82AV
3
ns
-15
90%
10%
CY7C43642/
62/82AV
-7
CY7C43642/
62/82AV
3 4 5 ns
3 4 5 ns
2.5 4 5 ns
5 7 7.5 ns
0 0 0 ns
1 2 2 ns
5 5 7.5 ns
UnitMin. Max. Min. Max. Min. Max.
7
Page 8
CY7C43642AV
PRELIMINARY
Switching Characteristics
Parameter Description
[9]
t
SKEW2
t
A
t
WFF
t
REF
t
PAE
t
PAF
t
PMF
t
PMR
t
MDV
t
RSF
t
EN
t
DIS
t
PRT
t
RTR
Notes:
10. Writing data to the Mail1 register when the B
11. Writing data to the Mail2 register when the A
Skew Time between CLKA↑ and CLKB↑ for AEA, AEB,
AFA
, AFB
Access Time, CLKA↑ to A
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑
to FFB
/IRB
Propagation Dela y Time, CLKA↑ to EF A/ORA and CLKB↑
to EFB
/ORB
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to
AEB
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to
AFB
Propagation Dela y Time , CLKA↑ to MBF 1 LO W or MBF2
HIGH and CLKB↑ to MBF2
Propagation Delay Time, CL KA↑ to B
to A
0–35
[11]
Propagation Delay Time, MBA to A
B
Valid
0–35
Propagation Delay Time, MRS1 or PRS1 LOW to AEB
LOW, AFA
MBF1
HIGH, FFB
HIGH, FFA/IRA LOW, EFB /ORB LOW and
HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB
/IRB LOW, EFA /ORA LOW and MBF2 HIGH
Enable Time, CSA or W/RA LOW to A
LOW and W
/RB HIGH to B
Disable Time, CSA or W/RA HIGH to A
Impedance and CSB
High-Impedance
Retransmit Pulse Width 60 60 60 ns
Retransmit Recovery Time 90 90 90 ns
Over the Operating Range (continued)
0–35
LOW or MBF1 HIGH
0–35
HIGH or W/RB LOW to B
outputs are active and MBB is HIGH.
0–35
outputs are active and MBA is HIGH.
0–35
and CLKB↑ to B
[10]
and CLKB↑
0–35
Vali d and MBB to
0–35
Active a nd CSB
0–35
Active
at High-
0–35
0–35
0–35
at
CY7C43662AV/CY7C43682A V
CY7C43642/
62/82AV
-7
7 8 12 ns
1 6 1 8 3 10 ns
1 6 1 8 2 10 ns
1 6 1 8 2 10 ns
1 6 1 8 1 10 ns
1 6 1 8 1 10 ns
0 6 0 8 0 12 ns
1 7 2 11 3 12 ns
1 6 2 9 3 11 ns
1 6 1 10 1 15 ns
1 6 2 8 2 10 ns
1 5 1 6 1 8 ns
CY7C43642/
62/82AV
-10
CY7C43642/
62/82AV
-15
UnitMin. Max. Min. Max. Min. Max.
8
Page 9
CY7C43642AV
PRELIMINARY
Switching W aveforms
FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
CLKB
t
M
RST1
FWFT/STAN
FS1, FS0
FFA
/IRA
EFB
/ORB
AEB
AFA
RSTS
t
t
RSF
RSF
t
RSF
t
RSF
t
FSS
[12]
CY7C43662AV/CY7C43682A V
t
RSTH
t
FWS
t
FSH
t
WFF
t
RSF
MBF1
Note:
12. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
9
Page 10
CY7C43642AV
PRELIMINARY
Switching W aveforms
Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
(continued)
[13]
CY7C43662AV/CY7C43682A V
CLKA
RST1, MRST2
M
t
FSS
t
FSH
FS1, FS0
t
WFF
IRA
FFA/
t
ENS
t
ENH
ENA
t
A
t
0−35
AFA Offset (Y1)
DH
DS
AEB Offset (X1)
AFB
Offset (Y2)
CLKB
FFB
/IRB
AEA
t
SKEW1
Offset (X2)
[14]
First Word to FIFO1
t
WFF
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
t
CLK
t
CLKH
t
CLKL
CLKA
FFA
/IRA
HIGH
t
ENS
t
ENH
CSA
t
t
ENH
ENS
W/RA
t
ENStENH
MBA
t
t
ENH
ENS
ENA
t
t
DS
DH
A
0–35
Notes:
13. CSA
14. t
15. Written to FIFO1.
=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
SKEW1
edge of CLKA and rising edge of CLKB is less than t
W1
[15]
, then FFB/IRB may transition HIGH one cycle later than shown.
SKEW1
t
W2
ENS
[15]
t
ENH
t
ENS
t
ENH
10
Page 11
CY7C43642AV
PRELIMINARY
t
CLKH
(continued)
t
CLK
t
CLKL
t
t
ENS
t
ENStENH
t
ENStENH
t
t
ENS
t
DStDH
[16]
W1
ENH
ENH
Switching W aveforms
Port B Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKB
FFB
CSB
W/RB
MBB
ENB
B
0−35
/IRB
HIGH
CY7C43662AV/CY7C43682A V
t
ENS
W2
[16]
t
ENH
t
ENS
t
ENH
Port B Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
t
CLK
t
CLKH
t
CLKL
CLKB
EFB
/ORB
HIGH
CSB
W/RB
MBB
t
t
ENS
ENH
ENB
W1
[17]
t
A
t
A
B
0–35
(Standard Mode)
OR
B
0–35
(FWFT Mode)
Notes:
16. Written to FIFO2.
17. Read from FIFO1.
t
MDV
t
EN
t
MDV
t
EN
Previous Data
W1
W2
[17]
[17]
t
ENS
t
ENH
t
ENS
t
A
t
A
No Operation
W2
W3
[17]
[17]
t
EN
t
DIS
t
DIS
11
Page 12
CY7C43642AV
PRELIMINARY
Switching W aveforms
Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKA
/ORA
EFA
CSA
W/RA
MBA
ENA
A
0–35
(Standard Mode)
OR
A
0−35
(FWFT Mode)
HIGH
(continued)
t
CLK
t
CLKH
t
EN
t
EN
t
t
MDV
MDV
t
CLKL
t
t
ENS
ENH
t
A
Previous Data
t
[18]
W1
A
CY7C43662AV/CY7C43682A V
W1
W2
[18]
[18]
t
ENS
t
ENH
t
A
t
A
t
ENStENH
No Operation
[18]
W2
[18]
W3
t
DIS
t
DIS
Note:
18. Read from FIFO2.
12
Page 13
CY7C43642AV
CY7C43662AV/CY7C43682A V
Switching W aveforms
PRELIMINARY
(continued)
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
t
CLK
t
t
CLKH
CLKL
CLKA
CSA
W/RA
LOW
HIGH
t
ENS
t
ENH
MBA
t
t
ENH
ENS
ENA
FFA
A
0–35
CLKB
/IRA
HIGH
t
t
DS
DH
W1
t
[19]
t
SKEW1
CLKHtCLKL
t
REF
EFB
CSB
W/RB
MBB
/ORB
FIFO1 Empty
LOW
HIGH
LOW
t
CLK
ENB
t
A
B
0–35
Note:
19. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
SKEW1
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
load of the first word to the output register may occur one CLKB cycle later than shown.
Old Data in FIFO1 Output Register
t
ENStENH
t
REF
W1
, then the transition of ORB HIGH and
SKEW1
13
Page 14
CY7C43642AV
CY7C43662AV/CY7C43682A V
Switching W aveforms
PRELIMINARY
(continued)
EFB Flag Timing and First Data Read F all Through when FIFO1 is Empty (CY Standard Mode)
t
CLK
t
t
CLKH
CLKL
CLKA
CSA
W/RA
LOW
HIGH
t
ENS
t
ENH
MBA
t
t
ENS
ENH
ENA
/IRA
FFA
A
0–35
HIGH
t
t
DS
DH
W1
t
SKEW1
[20]
t
CLKH
t
CLKL
CLKB
t
REF
EFB
/ORB
FIFO1 Empty
t
CLK
t
REF
[20]
CSB
W/RB
MBB
LOW
HIGH
LOW
ENB
B
0–35
Note:
20. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between
SKEW1
the rising CLKA edge and rising CLKB edge is less than t
t
t
ENS
ENH
t
A
W1
, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
SKEW1
14
Page 15
CY7C43642AV
CY7C43662AV/CY7C43682A V
Switching W aveforms
PRELIMINARY
(continued)
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
t
CLK
t
CLKHtCLKL
CLKB
CSB
W/RB
LOW
LOW
t
ENS
t
ENH
MBB
t
t
ENH
ENS
ENB
FFB
B
0–35
/IRB
HIGH
t
DS
W1
t
DH
t
SKEW1
[22]
t
CLKHtCLKL
CLKA
t
REF
EFA
/ORA
FIFO2 Empty
t
CLK
t
[21]
REF
CSA
W/RA
MBA
LOW
LOW
LOW
ENA
t
A
A
0–35
Notes:
21. t
22. t
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
SKEW1
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than t
load of the first word to the output register may occur one CLKA cycle later than shown.
Old Data in FIFO2 Output Register
t
ENStENH
W1
, then the transition of ORA HIGH and
SKEW1
15
Page 16
CY7C43642AV
CY7C43662AV/CY7C43682A V
Switching W aveforms
PRELIMINARY
(continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
t
CLK
t
CLKHtCLKL
CLKB
CSB
W/RB
LOW
LOW
t
ENS
t
ENH
MBB
t
t
ENH
ENS
ENB
FFB
B
0–35
/IRB
HIGH
t
t
DH
DS
W1
[23]
t
SKEW1
t
CLKHtCLKL
CLKA
t
REF
EFA
/OFA
FIFO2 Empty
t
CLK
t
REF
CSA
W/RA
MBA
LOW
LOW
LOW
ENA
A
0–35
Note:
23. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the
SKEW1
rising CLKB edge and rising CLKA edge is less than t
t
ENStENH
t
A
W1
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
SKEW1
16
Page 17
CY7C43642AV
PRELIMINARY
t
CLKH
(continued)
CLK
t
CLKL
t
ENStENH
t
A
t
SKEW1
Next Word From FIFO1
[24]
t
CLKHtCLKL
t
CLK
t
WFF
Switching W aveforms
IRA Flag Timing and First Available Writ e when FIFO1 is Full ( FWFT Mode)
t
CLKB
CSB
W/RB
MBB
ENB
EFB
B
0–35
CLKA
FFA
/ORB
/IRA
LOW
HIGH
LOW
HIGH
Previous Word in FIFO1 Output Register
FIFO1 Full
CY7C43662AV/CY7C43682A V
t
WFF
CSA
W/RA
LOW
HIGH
MBA
ENA
A
0–35
Note:
24. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
SKEW1
rising CLKB edge and rising CLKA edge is less than t
t
t
ENH
ENS
t
ENStENH
t
t
DS
DH
To FIFO1
, then IRA may transition HIGH one CLKA cycle later than shown.
SKEW1
17
Page 18
CY7C43642AV
CY7C43662AV/CY7C43682A V
Switching W aveforms
PRELIMINARY
(continued)
FFA Flag Timing and First A vailable Write when FIFO1 is Full (CY Stan dard Mode)
t
CLK
t
t
CLKH
CLKL
CLKB
CSB
W/RB
MBB
LOW
HIGH
LOW
t
ENStENH
ENB
/ORB
EFB
B
0–35
HIGH
t
A
Previ ous Wo r d in FIFO1 Ou t pu t R egister
t
SKEW1
Next Word From FIFO1
[25]
t
CLKH
t
CLKL
CLKA
t
WFF
FFA
/IRA
FIFO1 Full
t
CLK
t
WFF
CSA
W/RA
LOW
HIGH
MBA
ENA
A
0−35
Note:
25. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the
SKEW1
rising CLKB edge and rising CLKA edge is less than t
t
t
ENH
ENS
t
t
ENS
ENH
tDHt
DS
, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
SKEW1
18
Page 19
CY7C43642AV
PRELIMINARY
t
CLK
t
ENS
(continued)
t
CLKL
t
t
SKEW1
t
ENH
A
[26]
Next Word From FIFO2
t
t
CLKH
CLKL
t
CLK
t
WFF
Switching W aveforms
IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
t
CLKH
CLKA
CSA
W/RA
MBA
ENA
EFA
A
0–35
CLKB
FFB
/ORA
/IRB
LOW
LOW
LOW
HIGH
Previous Word in FIFO2 Output Register
FIFO2 Full
CY7C43662AV/CY7C43682A V
t
WFF
CSB
W/RB
LOW
LOW
MBB
ENB
B
0–35
Note:
26. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the
SKEW1
rising CLKA edge and rising CLKB edge is less than t
To FIFO2
t
t
ENH
ENH
t
DH
t
ENS
t
ENS
t
DS
, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
SKEW1
19
Page 20
CY7C43642AV
CY7C43662AV/CY7C43682A V
Switching W aveforms
PRELIMINARY
(continued)
FFB Flag Timing and First A vailable Write when FIFO2 is Full (CY Standard Mode)
t
CLK
t
t
CLKH
CLKL
CLKA
CSA
W/RA
MBA
LOW
LOW
LOW
t
ENS
t
ENH
ENA
EFA
A
0–35
/ORA
HIGH
t
A
Previous Word in FIFO12 Output Register
t
SKEW1
Next Word From FIFO2
[27]
t
CLKH
t
CLKL
CLKB
t
WFF
FFB
/IRB
FIFO2 Full
t
CLK
t
WFF
CSB
W/RB
LOW
LOW
MBB
ENB
B
0–35
Note:
27. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the
SKEW1
rising CLKA edge and rising CLKB edge is less than t
t
ENS
t
ENS
t
DS
, then the transition of FFB HIGH may occur one CLKB cycle later than shown.
SKEW1
To FIFO2
t
t
ENH
t
ENH
DH
20
Page 21
CY7C43642AV
Switching W aveforms
Timi ng for A E B
CLKA
ENA
CLKB
AEB
ENB
Timi ng for A E A
when FIFO1 is Almost Empty (CY Standard and FWFT Modes)
X1 Word in FIFO1
when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
(continued)
t
ENS
PRELIMINARY
t
ENH
[30]
t
SKEW2
t
PAE
CY7C43662AV/CY7C43682A V
(X1+1)Words in FIFO1
t
ENS
[28, 29, 30, 34]
t
PAE
t
ENH
[31, 32, 33, 34]
CLKB
t
ENS
t
ENH
ENB
[33]
t
SKEW2
CLKA
t
AEA
X2 Word in FIFO2
t
PAE
(X2+2)Words in FIFO2
t
ENS
t
ENH
PAE
ENA
Notes:
28. FIFO1 Port A Write (CSA
register has been read from the FIFO.
29. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
30. t
31. FIFO2 Port B Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Port A read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output
32. If Port B size is word or byte, t
33. t
34. Program able flag deasserts one clock cycle less than IDT’s equivalent (72V36x2). When FIFO is operated at the almost empty/full boundary, there may be
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
SKEW2
the rising CLKA edge and rising CLKB edge is less than t
register has been read from the FIFO.
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
SKEW2
the rising CLKB edge and rising CLKA edge is less than t
an uncertainty of up to 2 clock cycles for flag deassertion, but the flag will always be asserted exactly when the FIFO content reaches the programmed value.
Refer to “Designing with CY7C436xx Synchronous FIFOs” application note for more details on flag uncertainties.
= LOW, W/RA = HIGH, MBA = LOW), FIFO1Port B read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output
, then AEB may transition HIGH one CLKB cycle later than shown.
SKEW2
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
SKEW2
, then AEA may transition HIGH one CLKA cycle later than shown.
SKEW2
21
Page 22
CY7C43642AV
PRELIMINARY
Switching W aveforms
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
CLKA
ENA
AFA
CLKB
ENB
Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)
CLKB
ENB
AFB
[D–(Y1+1)] Words in FIFO1
[D–(Y2+2)] Words in FIFO2
(continued)
t
ENS
t
ENS
t
t
PAF
PAF
t
t
ENH
ENH
t
SKEW2
(D–Y1)Words in FIFO1
t
ENS
ENH
t
SKEW2
t
(D–Y2)Words in FIFO2
[38]
[40]
CY7C43662AV/CY7C43682A V
[35, 36, 37, 38]
t
PAF
[36, 39,40 ]
t
PAF
CLKA
t
ENS
t
ENH
ENA
Notes:
35. FIFO1 Port A Write (CSA
register has been read from the FIFO.
36. D = Maximum FIFO Depth = 1K for the CY7C43642AV, 4K for the CY7C43662AV, and 16K for the CY7C43682AV.
37. If Port B size is word or byte, t
38. t
39. FIFO2Port A Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Port A Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output
40. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
SKEW2
rising CLKA edge and rising CLKB edge is less than t
register has been read from the FIFO.
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between
SKEW2
the rising CLKB edge and rising CLKA edge is less than t
= LOW, W/RA = HIGH, MBA = LOW), FIFO1 Port B read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
SKEW2
, then AFA may transition HIGH one CLKB cycle later than shown.
SKEW2
, then AFB may transition HIGH one CLKA cycle later than shown.
SKEW2
22
Page 23
CY7C43642AV
Switching W aveforms
(continued)
Timing for Mail1 Register and MBF1
CLKA
CSA
t
W/RA
MBA
ENA
A
0–35
CLKB
MBF1
PRELIMINARY
Flag (CY Standard and FWFT Modes)
t
ENH
t
ENS
t
ENS
t
t
t
ENS
ENS
DS
W1
ENH
t
ENH
t
t
DH
ENH
t
PMF
CY7C43662AV/CY7C43682A V
t
PMF
CSB
W/RB
MBB
ENB
B
0−35
t
EN
FIFO1 Output Register
t
MDV
t
PMR
t
ENS
W1 (Remains valid in Mail1 Register after read)
t
ENH
t
DIS
23
Page 24
CY7C43642AV
PRELIMINARY
Switching W aveforms
Timing for Mail2 Register and M BF2 Flag (CY Standard and FWFT Modes)
CLKB
CSB
W/RB
MBB
ENB
B
0–35
CLKA
MBF2
(continued)
t
ENS
t
ENS
t
ENS
t
ENS
t
DS
W1
t
t
t
t
ENH
t
ENH
ENH
ENH
DH
t
PMF
CY7C43662AV/CY7C43682A V
t
PMF
CSA
W/RA
MBA
ENA
A
0−35
FIFO1 Retransmit Timing
RT1
ENB
EFB/FFA
t
EN
FIFO2 Output Register
[41, 42, 43, 44 ]
t
MDV
t
PMR
t
t
ENS
W1 (Remains valid in Mail2 Register after read)
PRT
t
ENH
t
RTR
t
DIS
Notes:
41. Retransmit is performed in the same manner for FIFO2.
42. Clocks are free-running in this case. CY standard mode only.
43. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
44. For the AEA, AEB, AFA, and AFB flags, two clock cycle are necessary after t
to update th ese flags .
RTR
24
RTR
.
Page 25
CY7C43642AV
PRELIMINARY
Signal Description
Reset (MR ST1, MRST2)
Each of the t wo FIFO memories of the CY7C436X2AV undergoes a complete reset by taking its associated Master Reset
RST1, MRST2) input LOW for at least four Port A clock
(M
(CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset inputs can switch asynchronously to
the clocks. A Master Reset initializes the internal read and
write pointers and forces the Full/Input Ready flag (FFA
FFB
/IRB) LOW, the Empty/Output Ready flag (EFA/ORA,
EFB
/ORB) LOW , the Almost Empt y flag (AEA, AEB) LO W , and
the Almost Full flag (AFA
forces the Mailbox flag (MBF1
, AFB) HIGH. A Master Reset also
, MBF2) of the parallel mailbox
register HIGH. After a Master Reset, the FIFO’s Full/Input
Ready flag is set HIGH aft er two clock cycle s to begin normal
operation. A Master Reset must be perfo rmed on the FIFO
after power up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO reset (M
RST1, MRST2)
input latches the values of the Flag select (FS0, FS1) for
choosing the Almost Full and Almost Empty offset programming method (see Almost Empty and Almost Full flag offset
programming below).
First-Word Fall-Through (FWFT
/STAN)
After M aster R eset, the FWFT sele ct fu nctio n is ac tiv e, perm itting a choice between two possible timing modes: CY Standard Mode or First-Word Fall-Through (FWFT) Mode. Once
the Master Reset (M
the FWFT
/STAN input at the second LOW-to-HIGH transition
RST1, MRST2) input is HIGH, a HIGH o n
of CLKA (f or FIFO1) and CLKB (f or FIFO2) will sel ect CY Standard Mode. This mode uses the Empty Flag function (EFA
EFB
) to indica te whether or not t here ar e an y wor ds p resent in
the FIFO memory. It uses the Full Flag function (FFA
indicate whether or not the FIFO memory has any free space
for writing. In CY Standard mode, every word read from the
FIFO, including the first, must be requested using a formal
read operati on.
Once t he Ma ster Res et (M
LOW on the FWFT
/STAN input during the next LOW-to-HIGH
RST1, MRST2 ) input is HIGH, a
transitio n of CLKA (for FIFO1) and CLKB (f or FIFO2) will select
FWFT Mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at
the data output s (A
0–35
or B
). It also uses the Input Ready
0–35
function (IRA, IRB) to indicate whether or not the FIFO memory has any free spac e fo r writing. In the FWFT m ode, t he fir st
word written to an empty FIFO goes directly to data outputs,
no read request necessary. Subsequent words must be accessed by performing a formal read operation.
Following Master Reset, the level applied to the FWFT
input to choose the desired timing mode must remain static
throughout th e FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four re gisters in the CY7 C436X2A V a re used t o hold th e offset
values for the Almost Empty and Al m ost Full flags. The Port B
Almost Empty flag (AEB
Port A Almost Empty flag (AEA
The Port A Almost Full flag (AFA
and the Port B Almost Full f lag (AFB
) offset register is labeled X1 and the
) offset register is labeled X2.
) offset register is labeled Y1
) offset register is labele d
Y2. The index of each register name corresponds with preset
/IRA,
, FFB) to
/STAN
CY7C43662AV/CY7C43682A V
values during the reset of a FIFO, programmed in parallel using the FIFO’s P ort A data inputs .
To program the X1, X2, Y1, and Y2 registers in parallel from
Port A, perf orm a Master Reset on b oth F IFOs sim ultane ously
with SPM
HIGH transition of M
plete, the first four writes to FIFO1 do not store data in RAM
but load the offset registers in the order Y1, X1, Y2, X2. The
Port A data inputs used by the offset registers are (A
(A
highest numbered input is used as the most significant bit of
the binary number i n each case . V al id pr ogr amming v al ues f o r
the regist ers range from 0 to 1023 for the CY7C43642AV; 0 to
4095 for the CY7C43662 AV ; 0 to 16383 for the CY7C43682A V .
(see footnote #34) After all the offset registers are programmed from Port A, the Port B Full/Input Ready (FFB
is set HIGH and both FIFOs begin normal operation.
FS0 and FS1 function the same wa y in both CY Standard and
FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A
A Chip Select (CSA
The A
CSA
when both CSA
Data is loaded into FIFO1 from the A
HIGH transition of CLKA when CSA
ENA is HIGH, MBA is LOW, and FF A
from FIFO2 to the A
of CLKA when CSA
,
is LOW, and EF A
writes on Port A are independent of any concurrent Port B
operation.
The Port B contr ol signals are identical to those of Port A with
the exception that the Port B Write/Read select (W
inverse of the Port A Write/Read select (W/RA
the Port B data (B
Select (CSB
lines are in the high-impedance state when either CSB is
HIGH or W
when CSB
Data is loaded into FIFO2 from the B
HIGH transition of CLKB when CSB
ENB is HIGH, MBB is LOW , and FFB
from FIFO1 to the B
of CLKB when CSB
MBB is LOW , and EFB
and writes on Port B are independent of any concurrent Port
A operation.
The set-up and hold t ime constraints to the port clocks for the
port Chip Selects and Write/Read sel ects are onl y for ena bling
write and read operations and are not related to high-impedance control of the data o utputs. If a port enabl e is LOW during
a clock cycle, the p ort’s Chip Select and Write/Read select
may change states during the set -up and hold time window of
the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag i s LOW, the next word written is automatically sent
to the FIFO’s output reg ister by t he LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data re-
HIGH and FS0 and FS1 LOW during the LOW-to-
RST1 and MRST2. After this reset is com-
), or (A
0–11
lines are in the high-impedance state when either
0–35
or W/RA is HIGH. The A
), for the CY7C436X2AV, respectively. The
0–13
) lines is controlled by Port
) and Port A Write/Read Select (W/RA).
and W/RA are LOW.
0–35
lines are active outputs
0–35
inputs on a LOW-to -
0–35
is LOW, W/RA is HIGH,
/IRA is HIGH. Data is read
outputs by a LOW-to-HIGH transition
0–35
is LOW, W/RA is LOW, ENA is HIGH, MBA
/ORA is HIGH (see Table 2). FIFO reads and
) lines is controlled by the Port B Chip
0–35
) and Port B Write/Read select (W/RB) . The B
/RB is LOW. The B
is LOW and W/RB is HIGH.
lines are active outputs
0–35
inputs on a LOW-to -
0–35
is LOW, W/RB is LOW,
/IRB is HIGH. Data is read
outputs by a LOW-to-HIGH transition
0–35
is LOW, W/RB is HIGH, ENB is HIGH,
/ORB is HIGH (see Table 3). FIFO reads
). The state of
0–9
/IRB)
/RB) is the
0–35
),
25
Page 26
CY7C43642AV
PRELIMINARY
siding in the FI FO’s memory array is cl ock e d t o the ou tput r eg-
ister only when a r ead is sel ected us ing t he port’s Chip Select,
Write/Read select, Enable, and Mailbox select.
When operat ing t he FIFO i n CY Standard Mode , rega rdless of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select, Write/
Read select, Enable, and Mailbox select.
Synchronized Flags
Each FIFO is synchronized to its port clock through at least
two fli p-flop st age s. Th is is don e to i mpro v e fl ag-si gnal r elia bility by reducing the probability of the metastable events when
CLKA and CL KB operat e asynchro nously t o one another . EFA
ORA, AEA
EFB
CLKB. Table 4 and Table 5 show the relationship of each port
flag to FIFO1 and FIFO2.
Empty/Output Ready Flags (EFA
These are dual-purpose flags. In the FW FT M ode, the Output
Ready (ORA, ORB) function is selected. When the Output
Ready flag is HIGH, new data is present in the FIFO output
register. When the Output Ready flag is LOW, the previous
data word remains in the FIFO output register and any FIFO
reads are ignored.
In the CY Standard Mod e, the Empty Flag ( EF A
is selected . When the Empty Fl ag is HI GH, data is av ailab le i n
the FIFO’s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word remains in
the FIFO output register and any FIFO reads are ignored.
The Empty/Output Rea dy flag of a FIFO is sync hronized to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer comparator th at indicates when
the FIFO SRAM status is empty, empty+1, or empty+2.
In FWFT Mode, from the time a w ord is writte n to a FIFO , it ca n
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three cycles hav e not elapse d since the t ime the w ord was written . The
Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH trans it ion of the synchronizing clock occurs , simultaneousl y f orc ing the Out put Ready f lag HIGH and s hift ing
the word to the FIFO output register.
In the CY Standard Mode , from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty flag
synchronizi ng cloc k. Theref ore, an Empty flag is LOW if a w ord
in memory is the next data to be sent to the FIFO output register and tw o cycles have not elapsed since the ti m e the word
was written. The Empty flag of the FIFO remai ns LO W until th e
second LOW -t o-HIGH transit ion of the synchr onizing cloc k occurs, f orc ing th e Empt y fla g HIGH; on ly then ca n data b e r ead.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizi ng clock begins the first synchronization cycle of a
write if the clock transition occurs at time t
after the write. Otherwise, the subsequent clock cycle will be
the first synchronization cycle.
, FFA/IRA, and AFA are synchronized to CLKA.
/ORB, AEB, FFB/IRB, and AFB are synchronized to
/ORA, EFB/ORB)
, EFB) function
or greater
SKEW1
CY7C43662AV/CY7C43682A V
Full/Input Ready Flags (FFA
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IRA and IRB) functio n is selected. In CY Standard M ode, the
Full Flag (FFA
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
any writes to the FIFO are igno red.
The Full/Input Ready f lag of a FIFO is synchron ized to the port
clock that write s data to its arr ay. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its write
pointer is incr ement ed. The st ate machin e that co ntrol s a Full /
Input Ready flag monitors a write pointer and read pointer
/
comparator that indicates when the FIFO SRAM status is full,
full–1, or full–2. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next memory write location has been
read. The second LOW-to-HIGH transition on the Full/Input
Ready flag synchronizing clock after the read sets the Full/
Input Ready flag HIGH.
A LOW-t o-HIGH tr ansit ion on a Full/ Input Read y flag sync hronizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time t
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AEA
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The Almost Empty state is defined by the contents of register
X1 for AEB
ed with preset values during a FIFO reset, programmed from
Port A, or programmed serially (see Almost Empty flag and
Almost Full flag offset progr ammi ng abo ve) . An Almost Empty
flag is LOW when its FIFO contains X or less words and is
HIGH when its FIFO cont ains (X+1) or more wo rds. (see footnote #34)
Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost
Empty flag to reflect the ne w le v el of fil l. Theref o re, t he Almost
Empty flag of a FIFO containing (X+1 ) or more words remains
LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to the (X+1) lev el. A LO W -to-HIGH tr ansition of an
Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t
the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle will be the first synchronization cycle.
Almost Full Flags (AFA
The Almost Full flag of a FIF O is sync hronized to the port cloc k
that writes data t o it s arr a y. The state machine t hat contr ols an
Almost Full f lag mon itor s a write po inter a nd read po inter c om-
and FFB) function is selected. For both timing
and regist er X2 for AEA. These registers are load-
/IRA, FFB/IRB)
, AEB)
, AFB)
or greater after the
SKEW1
or greater after
SKEW2
26
Page 27
CY7C43642AV
PRELIMINARY
parator that indicates when the FIFO SRAM status is almost
full, alm ost full–1, or almost full–2. The Almost Full state is
defined by the contents of register Y1 for AFA
for AFB
. These regis ters are loaded with preset values d uring
a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024–Y),
(4096–Y), or (1 6384–Y) for the CY7C436X2AV respectively.
An Almost Full flag is HIGH when the number of words in its
FIFO is less than or equal to [1024–(Y+1) ], [4096 –(Y+1 )], or
[16384–(Y+1)], for the CY7C436X2AV respectively. (see footnote #34)
Two LOW-to-HI G H tr ansitions of the Almost F ull flag synchronizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] o r less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [1024/4096 /16384–(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizi ng clo c k aft er the FIFO r ead th at redu ces t he num ber of words in mem ory t o [1024/4096/16384–(Y+1)]. A LOWto-HIGH transition of an Almost Full flag synchronizing clock
begins the f irst sync hroniza tion cycle i f it occ urs at time t
or greater after the read that reduces the number of words in
memory to [1024/4096/16384–(Y+1)]. Otherwise, the subsequent synchronizing clock cycle will be the first synchronization cycle.
Mailbox Registers
Each FIFO ha s a 36-b it b yp ass register t o pass c omma nd and
control infor mation between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usabl e width of both the Mail1 and Mail 2 registers matc h es th e se le ct e d bus s ize for Port B.
A LOW-to-HIGH transition on CLKA writes A
Mail1 Register whe n a Port A write is selected b y CSA
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register employs dat a lines A
. If the selecte d Po rt A bus size is 18 bi ts,
0−35
then the usab le widt h of t he Mail1 Re gister emplo ys data lines
A
. (In th is cas e , A
0−17
ed Port A bus size is 9 bits, then the usable width of the Mail1
Register emplo ys data l ines B
care inputs .)
are don’t care i nputs .) If the sel ec t-
18−35
. (In this case, A
0−8
A LOW-to-HIGH transition on CLKB writes B
Mail2 Register when a Port B write is selected b y CSB
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register employs dat a lines B
. If the selecte d Po rt B bus size is 18 bi ts,
0–35
and register Y2
SKEW2
data to the
0−35
0−35
, W/RA,
are don’t
9−35
data to the
, W/RB,
CY7C43662AV/CY7C43682A V
then the usabl e widt h of the Mai l2 Regi ster e mplo ys dat a li nes
B
. (In this case, B
0–17
ed Port B bus size is 9 bits, then the usable width of the Mail2
Register emplo ys data lines B
care inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1
or MBF2) LOW. Attempte d writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register Flag (MBF1
HIGH transition on CLKB when a Port B read is selected by
CSB
, W/RB, and ENB with MBB HIGH. For a 36-bit bus size,
36 bits of mailbox data are placed on B
size, 18 bits o f mai lbo x data ar e place d on B
B
are indeterminate.) For a 9-bit bus size, 9 bits of mail-
18–35
box data are placed on B
minate.)
The Mail2 register Fl ag (MBF2
transition o n CLKA when a Port A read is select ed by CSA
RA
, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A
. For an 18-bi t bus size, 18 bi ts of mailbox data are placed
0–35
on A
. (In this case, A
0–17
bus size, 9 bits of mailbox data are placed on A
case, A
are indeterminate.)
9–35
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Retransmit (RT1
, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit function applies to CY standar d mo de only.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have occurred and at least one wor d has been r ead si nce the l ast rese t
cycle. A LOW pu lse o n RT1
er to the first physical location of the FIFO. CLKA and CLKB
may be free running but ENB must be deasserted during and
t
after the retr ansmit pulse . With ev ery valid re ad cycle after
RTR
retransmit, previously accessed data is read and the read
pointer is increment ed until it is equal to the write point er. Flags
are governed by the relative locations of the read and write
pointers and ar e updated during a retransmit cycle. Data written to the FIFO after activation of RT1
also.
are don’t care i nputs .) I f the s el ect-
18–35
. (In this case, B
0−8
9−35
) is set HIGH by a LOW-to-
. For an 18-bit bus
. (In this case, B
0–8
0–35
. (In this case,
0–17
are indeter-
9–35
) is set HIGH by a LO W-to-HIGH
are indeterminate.) For a 9-bit
18–35
, RT2 r esets the internal read point -
, RT2 are transmitted
are don’t
. (In th is
0–8
, W/
27
Page 28
CY7C43642AV
PRELIMINARY
CY7C43662AV/CY7C43682A V
Table 1. Flag Programming
FS1 FS0 MRST1 MRST2 X1 and Y1 Registers
H H
H H X
H L
H L X
L H
L H X
L L
↑
↑
↑
↑ ↑
X 64 X
↑
X 16 X
↑
X 8 X
↑
Programming via Port A Program ming via Port A
X 64
X 16
X 8
[45]
X2 and Y2 Registers
T able 2. Port A Enable Function
CSA
W/RA ENA MBA CLKA A
Outputs Port Function
0–35
H X X X X In high-impedance state None
L H L X X In high-impedance state None
LHHL↑ In high-impedance state FIFO1 write
LHHH↑ In high-impedance state Mail1 write
L L L L X Active, FIFO2 output register None
LLHL↑ Active, FIFO2 outp ut register FIFO2 read
L L L H X Active, Mail2 register None
LLHH↑ Active, Mail2 register Mail2 read (set M B F2
[46]
HIGH)
Table 3. Port B Enable Function
CSB
W/RB ENB MBB CLKB B
Outputs Port Function
0–35
H X X X X In high-impedance state None
L L L X X In high-impedance state None
LLHL↑ In high-impedance state FIFO2 write
LLHH↑ In high-impedance state Mail2 write
L H L L X Activ e, FIFO1 output register None
LHHL↑ Active, FIFO1 output register FIFO1 read
L H L H X Active, Mail1 register None
LHHH↑ Active, Mail1 register Mail1 read (set MBF1
Notes:
45. X1 register holds the offset for AEB
46. X2 register holds the offset for AEA
; Y1 register holds the offset for AFA.
; Y2 register holds the offset for AFB.
HIGH)
28
Page 29
CY7C43642AV
PRELIMINARY
t.
CY7C43662AV/CY7C43682A V
T able 4. FIFO1 Flag Operation (CY Standard and FWFT Modes)
Number of Words in FIFO Memory
[34, 47, 48, 49, 50]
CY7C43642AV CY7C43662AV CY7C43682AV EFB
Synchronized to CLKB Synchronized to CLKA
/ORB AEB AFA FFA/IRA
0 0 0 L L H H
1 to X1 1 to X 1 1 to X1 H L H H
(X1+1) to
[1024–(Y1+1)]
(1024–Y1) to
1023
(X1+1) to
[4096–(Y1+1)]
(4096–Y1) to
4095
(X1+1) to
[16384–(Y1+1)]
(16384–Y1) to
16383
HH HH
HH L H
1024 4096 16384 H H L L
T able 5. FIFO2 Flag Operation (CY Standard and FWFT modes)
Number of Words in FIFO Memory
CY7C43642AV CY7C43662AV CY7C43682AV EFA
[34, 48, 49, 51, 52]
Synchronized to CLKA Synchronized to CLKB
/ORA AEA AFB FFB/IRB
0 0 0 L L H H
1 to X2 1 to X2 1 to X2 H L H H
(X2+1) to
[1024–(Y2+1)]
(1024–Y2) to 1023 (4096–Y2) to 4095 (16384–Y2) to
(X2+1) to
[4096–(Y2+1)]
(X2+1) to
[16384–(Y2+1)]
HHHH
HHL H
16383
1024 4096 16384 H H L L
Notes:
47. X1 is the almost-empty offset for FIFO1 used by AEB
or port A programming.
48. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
49. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to
the output register (no read operation necessary), it is not included in the FIFO memory count.
50. The ORB and IRA functions are active during FWFT mode; the EFB
51. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset
or port A programming.
52. The ORA and IRB functions are active during FWFT mode; the EF A
. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset
and FFA functions are active in CY Standard mode.
and FFB functions are active in CY Standard mode.
29
Page 30
CY7C43642AV
PRELIMINARY
CY7C43662AV/CY7C43682A V
3.3V 1K x36 x2 Bidirectional Synchronous FIFO
Speed
(ns) Ordering Code
7 CY7C43642AV-7AC A120 120-Lead Thin Quad Flat Package Commercial
10 CY7C43642AV-10AC A120 120-Lead Thin Quad Flat Package Commercial
15 CY7C43642AV-15AC A120 120-Lead Thin Quad Flat Package Commercial
Package
Name
Package
Type
3.3V 4K x36 x2 Bidirectional Synchronous FIFO
Speed
(ns) O rderi ng C ode
7 CY7C43662AV-7AC A120 120-Lead Thin Quad Flat Package Commercial
10 CY7C43662A V-10AC A120 120-Lead Thin Quad Flat Package Commercial
15 CY7C43662A V-15AC A120 120-Lead Thin Quad Flat Package Commercial
Package
Name
Package
Type
3.3V 16K x36 x2 Bidirectional Synchronous FIFO
Speed
(ns) O rderi ng C ode
7 CY7C43682AV-7AC A120 120-Lead Thin Quad Flat Package Commercial
10 CY7C43682A V-10AC A120 120-Lead Thin Quad Flat Package Commercial
15 CY7C43682A V-15AC A120 120-Lead Thin Quad Flat Package Commercial
15 CY7C43682AV-15AI A120 120-Lead Thin Quad Flat Package Industrial
Shaded area contains advance information.
Package
Name
Package
Type
Operating
Range
Operating
Range
Operating
Range
Document #: 38-00775-A
Package Diagram
120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) A120
51-85100
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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