Datasheet CY7C43683AV-7AC, CY7C43683AV-15AC, CY7C43683AV-10AC, CY7C43663AV-7AC, CY7C43663AV-15AC Datasheet (Cypress Semiconductor)

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Page 1

CY7C43643AV

PRELIMINARY

CY7C43663AV/CY7C43683AV

3.3V 1K/4K/16K x36 Unidirectio nal

Synchronous FIFO w/ Bus Matching

Features

• High-speed, lo w-power, unidirectional, First- In Fi rstOut (FIFO) memori es w/ bus matching capabilities

• 1Kx36 (CY7C43643AV)

• 4Kx36 (CY7C43663AV)

• 16Kx36 (CY7C43683AV)

• 0.25-micr on CMOS for optimum speed/power

• High-speed 133- MHz operat ion (7.5- ns read /write c ycle times)

• Low power

—I

= 60 mA

= 10 mA

—I

Logic Block Diagram

• Fully asynchronous and simultaneous read and write operation permitted

• Mailbox bypass register for each FIFO

• Parallel and Serial Programmable Almost Full and Almost Empty flags

• Ret ra n smit function

• Standard or FW FT user selectable mode

• Partial Reset

• Big or Little Endian format for word or byte bus sizes

• 128-Pin TQFP packaging

• Easily expandable in width and depth

CLKA

CSA

W/RA

ENA MBA

MRS1

MRS2

PRS

FF/IR

SPM

FS0/SD

FS1/SEN

0–35

MBF2

Por t A Control Logic

FIFO, Mail1 Mail2 Reset Logic

Input

Write Pointer

Programmable Flag Offset

Registers

Mail1 Register

1K/4K/16K

x36 Dual Ported Memory

Status Flag Logic

Timing Mode

Mail2 Register

Read Pointer

Bus Matching

Output

MBF1

CLKB

Port B Control

Logic

CSB W/RB ENB MBB BE

BM SIZE

EF/OR AE

0–35

BE/FWFT

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600 August 11, 2000

Page 2

CY7C43643AV

Pin Configuration

[1]

W/RA

ENA

CLKA

GND

FWFT/STAN

GND

Note:

1. Pin-compatible to IDT723623/33/43 family.

PRELIMINARY

CY7C43663AV/CY7C43683AV

TQFP

Top View

MBF2NCAF

FS0/SD

FS1/SEN

GND

MRS1

VCCPRS

FF/IR

CSA

128

127

126

125

1 2 3

124

MBA

123

122

121

120

119

118

117

116

115

VCCMBF1

MRS2

MBB

114

113

112

111

4 5 6 7 8 9 10 11 12 13 14 15 16

CY7C43643AV

17 18 19 20 21

CY7C43663AV CY7C43683AV

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

39404142434445464748495051525354555657585960616263

6A7A8A9

GND

A3A4A

SPM

0A1

GND

EF/OR

110

109

108

107

5B4B3B2B1

GND

CSB

GND

ENB

W/RB

106

105

104

103

102

CLKB

101

NC V

100

GND

94 93

87 86

84 83

GND

GND B

SIZE

GND

B9B8B

Page 3

CY7C43643AV

PRELIMINARY

Functional Description

The CY7C436X3AV is a monolithic, high-speed, low-power, CMOS Unidirectional Synchronous FIFO memory which supports clock frequencies up to 133 MHz and has read access times as fast as 6 ns.

The CY7C436X3AV is a synchronous (clocked) FIFO, meaning each port emplo ys a sync hron ous int erf ace . All data t ransfers th rough a port are gate d to the LO W - to-HI GH trans iti on of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple unidirectional interf ace between microprocessors and/ or buses with synchronous control.

Communication b etw een each port ma y b ypas s the FIF Os via two mailbox registers. The mailbox registers’ width matches the selected P ort B bus width. Each mailbo x register has a f lag (MBF1

and MBF2) to signal when new mail has been stored.

T w o kinds of reset are a vailab le on th e CY7C436X3A V : Master Reset and Partial Reset . Master Rese t init ializ es t he read and write pointers to the fi rst location of the memory array, confi gures the FIFO for Big or Little Endian byte arrangement, and selects serial flag programming, parallel flag programming, or one of the three possible default flag offset settings, 8, 16, or

64. The FIFO also has two Master Reset pins, MRS1 MRS2

Partial Reset also sets the read and write pointers to the first location of the memory . Unlike Master Reset, any settings existing prior to P artial Reset ( i.e., progr amming meth od and partial flag default offsets) are retained. Partial Reset is useful since it permits fl ushing of the FI FO memory witho ut chang in g any configuration settings. The FIFO has its own i ndependent Partial Re s e t pin, PRS

The CY7C436X3AV have two modes of operation: In the CY Standard Mode, the first word written to an em pty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First-Word Fall-Through Mode (FWFT ), the fi rst

and

CY7C43663AV/CY7C43683AV

long-word (36-bit wide) written to an empty FIFO appe ars automatically on the out puts, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the FWFT FIFO operation determines the mode in use.

The FIFO has a combined Empty/Output Ready flag (EF and a combi ned Full/Input Ready flag (FF functions are select ed in the CY Standard Mode. EF indicat es whether the memory is ful l or not. The IR and OR funct ions are selected in the First-Word Fall-Through Mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has dat a av ai labl e fo r readin g or not. It marks the presence of valid data on the outputs.

The FIFO has a programm able Almost Empty flag (AE programmable Almost Full flag (AF lected number of words written to FIFO memory achieve a predetermined “almost em pty state.” AF lected number of words written to the memory achieve a predetermined “almost full state.” (See Note #.)

IR and AF into its array. OR and AE that reads data fr om its ar ra y. Progr ammab l e offse t f or AE AF input. Three default offset settings are also provided. The AE threshold can be set at 8, 16, or 64 locations from the empty boundary and AF from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider data paths. If at any time the FIFO i s not activ ely performing a function, the chip will automatically power down. During the Power Down state, supply current consumption (I minimum. Init iating any oper ati on (b y act iv atin g contr ol inputs ) will immediately take the device out of the Power Down state.

The CY7C436X3AV are characterized for operation from 0 to 70 ESD protection is g reater than 200 1V, and latch-up is p revented by the use of guard rings.

are synchronized to the port clock that writes data

are loaded in parallel using Port A or in serial via the SD

threshold ca n be se t at 8, 1 6, or 64 locat ions

C commercial and from –40°C to 85°C industrial. Input

are synchronized to the port clock

). AE indicates when a se-

/STAN pin during

/OR)

/IR). The EF and FF

) and a

indicates when a se-

and

) is at a

Selection Guide

CY7C43643/63/83AV -7CY7C43643/63/83AV

Maximum Frequency (MHz) 133 100 66.7 Maximum Access Time (ns) 6 8 10 Minimum Cycle Time (ns) 7.5 10 15 Minimum Data or Enable Set-Up (ns) 3 4 5 Minimum Data or Enable Hold (ns) 0 0 0 Maximum Flag Delay (ns) 6 8 10 Active Power Supply

Current (I

Density 1K x 36 4K x 36 16K x 36 Package 128 TQFP 128 TQFP 128 TQFP

CC1

) (mA)

Commercial 60 60 60 Industrial 60

CY7C43643AV CY7C43663AV CY7C43683AV

-10

CY7C43643/63/83AV

-15

Page 4

CY7C43643AV

PRELIMINARY

CY7C43663AV/CY7C43683AV

Pin Definitions

Signal Name Description I/O Function

0–35

BE/FWFT

BM Bus Match

CLKA Port A Clock I CLKA is a c ontinuous clock t hat synchr onizes all data tr ansfer s through P ort A and can

CLKB Port B Clock I CLKB is a c ontinuous clock t hat synchr onizes all data tr ansfer s through P ort B and can

CSA

CSB

/OR Empty/Output

ENA Port A Enable I ENA must be HIGH to enable a L O W -to- HIGH tra nsition of CLKA to rea d or write dat a

ENB Port B Enable I ENB must be HIGH to enable a L O W -to- HIGH tra nsition of CLKB to rea d or write dat a

/IR Port B Fu ll/Input

FS1/SEN

FS0/SD Flag Offset

MBA Port A Mailbox

Port A Data I 36-bit unidirectional data port for side A. Almost Empty

Flag (Port B)

Almost Full Flag O Progr am mable Almost Full f lag synchronized to CLKA. It is LOW when the n um ber of

Port B Data O 36-bit unidirectional data port for side B. Big Endian/

First-Word FallThrough Select

Select (Port B)

Port A Chip Select

Port B Chip Select

Ready Flag (Port B)

Ready Flag

Flag Offset Select 1/Serial Enable

Select 0/Serial Data

Select

O Programmab le Almost Empty flag sy nchroni zed to CLKA. It is LO W when the numb er

of words in the FIFO2 is less than or equal to the value in the Almost Empty A offset register, X. (See Note #35.)

empty locations in t he FIFO is less tha n or equal to the v alue in t he Almost Full A off set register, Y. (See Note #35.)

I This is a dual-purpose pin. During Maste r Reset, a HIGH on BE will selec t Big Endian

operation. In thi s case, depe nding on the bus size, the most signi ficant byt e or word on Port A is transf erred to P ort B first. A LO W on BE will select Little Endi an operat ion. In this case, the l eas t sign ificant b yte or w ord on Port A is transf err ed to Port B first. After Master Reset, this pin select s the tim ing mode. A HI GH on FWFT Mode, a LO W sel ects Fi rst- Wo rd F a ll- Through M ode. Once t he ti ming m ode has bee n selected, the level on FWFT

I A HIGH on this pin enables either b yte or wor d bus widt h on Po rt B, dependin g on the

state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. Th e level of BM must be static throughout device operation.

be asynchronous or coincident t o CLKB. FF to-HIGH transition of CLKA.

be asynchronous or coincident to CLKA. FB nized to the LOW-to-HIGH transition of CLKB.

ICSA must be LOW to enable a LOW-to HIGH trans it ion of CLKA to read or write on

Port A. The A

ICSB must be LOW to enable a LOW-to HIGH trans it ion of CLKB to read or write on

Port B. The B

O This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF

indicates whether or not the FIFO memory is empty . In the FWFT mode, the OR function is selected. OR indicates the presence of valid data on B reading. FF

on Port A.

on Port B.

O This is a dual-function pin. In the CY Standard Mode, the FF fu nction is s e lected. FF

indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is selecte d. IR indicates whether or not there is space a vailable for writing to the F IFO memory. FF

I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-

ming. During Master Reset , FS1/ SEN offset program ming method. Three offs et register prog ramming methods are a vailab le: automatically load one of three preset v alues (8, 16, or 64), par allel load from Port A,

and serial load. When serial load i s selec ted f or fl ag offs et regi ster p rogr amming, FS1/ SEN

is used as an enab le synchron ous to the LO W -to-HIGH tr ansition of CLKA. When FS1/SEN and Y registers. The number of bi t writes r equir ed to pr ogr am the of fset re gisters i s 2 0 for the CY7C43643, 24 for the CY7C43663, and 28 for t he CY7C43683. The first bit write stores the Y-register MSB and the last bit write sto res the X-register LSB.

I A HIGH lev el on MBA chooses a mailbox register for a Port A read or write oper ation.

is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X

outputs are in the high-impedance state when CSA is HIGH.

0–35

outputs are in the high- impedance state when CSB is HIGH.

0–35

/OR is synchronized to the LOW-to-HIGH transition of CLKB.

/IR is synchronized to the LOW-to-HIGH transition of CLKA.

must be static throughout device oper ation.

/IR and AF are all synchr onized to the LO W-

/IR, EF /OR, AF, and AE are all synchro-

and FS0/SD , toget her with SPM, sel ect the f lag

selects CY Standar d

outputs, available for

0–35

Page 5

CY7C43643AV

PRELIMINARY

Pin Definitions

Signal Name Description I/O Function

MBB Port B Mailbox

MBF1

MBF2

MRS1

MRS2 PRS

SIZE Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9- bit) size on Port B. A LOW

SPM

W/RA

RB Port B Write/

(continued)

Select

Mail1 Register Flag

Mail2 Register Flag

Master Reset I A LOW on this pin initializes the FIFO read and write pointers to the fi rst location of

Master Reset I A LOW on this pin initializes the Mail2 Register. Partial Reset I A LOW on this pin initializes the FIFO read and write pointers to the fi rst location of

Retransmit I A LOW strobe on this pin will retransmit the data in the FIFO. This is achieved by

Serial Programming

Port A Write/ Read Select

Read Select

I A HIGH lev el on MBB chooses a mailbox register for a Port B read or write oper ation.

When a read operatio n is perf ormed on Port B, a HIGH lev el on MBB select s data from the Mail1 register for output and a LOW level select s F IFO output register data for output. Data can only be written into Mail 2 register through Port B (MBB HIGH) and not into the FIFO memory.

OMBF1 is set LOW by a LOW-to-HIGH trans it ion of CLKA that writes data to the Mail1

register. Writes to the Mail1 register are inhibited while MBF1 HIGH by a LOW- to-HI GH transiti on of CLKB when a Po rt B read is selected and MBB is HIGH. MBF1

OMBF2 is set LOW by a LOW-to-HIGH trans it ion of CLKB that writes data to the Mail2

register. Writes to the Mail2 register are inhibited while MBF2 HIGH by a LOW- to-HI GH transiti on of CLKA when a Po rt A read is selected and MBA is HIGH. MBF2

memory and sets the P ort B output register to a ll zeroes. A LOW puls e on MRS1 the programmi ng method (serial or parallel ) and one of th ree programmab le flag def ault offsets. It also configures Port B for bus size and endian arrangement. Four LOW-toHIGH transitio ns of CLKA an d f our LOW -t o-HIGH tr ansitions o f CLKB mu st occur while MRS1

is LOW.

memory and sets the Port B output register to all zeroes. During Parti al Reset, the currently selected bus size, endian arrangement, pro gramming method (serial or parallel), and progr am m able flag settings are al l retained.

bringing the read pointe r back t o location z er o . The user will sti ll need to preform read operations to retransmit the data. Retransmit function appli es to CY sta ndard mode only.

on this pin when BM is HIGH sele cts word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation.

I A LOW on this pin se lects serial prog ramming o f partial flag offs ets. A HIGH on thi s pin

selects paral lel programming or default offsets (8, 1 6, or 64).

I A HIGH selects a write operation and a LOW selects a read operation on Port A for a

LOW-t o-HIGH transition of CLKA. The A when W/RA

I A LOW selects a write operation and a HIGH selects a read operation on Port B for a

LOW-to-HIG H transition of CL KB. The B when W

is set HIGH following either a Master or P artial Reset.

is HIGH.

/RB is LOW.

CY7C43663AV/CY7C43683AV

is LOW. MBF1 is se t

is LOW. MBF2 is se t

selects

outputs are i n the high-impedance state

0–35

outputs are in the high-impedance state

0–35

Page 6

CY7C43643AV

PRELIMINARY

Maximum Ratings

[2]

(Abov e which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .......... .............. ...........–65

C to +150°C

Ambient Temperature with

Power Applied...............................................–55

C to +125°C

Supply Voltage to Ground Potential............... –0.5V to +7.0V

DC Voltage Applied to Outputs in High Z State

DC Input Voltage

Electrical Characteristics

[3]

......................................–0.5V to VCC+0.5V

[3]

...................................–0.5V to VCC+0.5V

Over the Operating Range

Parameter Description Tes t Condi ti ons

V V I

OZL

OZH

CC1

IH IL

[5]

[6]

Output HIGH Voltage VCC = 3.0V,

= –2.0 mA

Output LO W Voltage VCC = 3.0V,

= 8.0 mA

Input HIGH Voltage 2.0 V Input LOW Voltage –0.5 0.8 V Input Leakage Curr ent V Output OFF, High Z

= Max. –10 +10 µA

VSS < VO< V

Current Active Power Supply

Current Average Standby

Current

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage ........... .. ........................... ...>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

CY7C43663AV/CY7C43683AV

Range

Temperature V

Commercial 0°C to +70°C 3.3V ± 10% Industrial –40°C to +85°C 3.3V ± 10%

CY7C43643/63/83AV

2.4 V

0.5 V

Ambient

–10 +10

Com’l 60 mA Ind 60 mA Com’l 10 mA Ind 10 mA

[4]

UnitMin. Max.

µA

Capacitance

[7]

Parameter Description Test Conditions Max. Unit

OUT

Notes:

2. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.

3. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

4. Operating V

5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded.

6. All inputs = V

7. Tested initially and after any design or process changes that may affect these parameters.

Range for -7 speed is 3.3V ± 5%.

– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.

Input Capacitance TA = 25°C, f = 1 MHz,

= 3.3V

Output Capacitance 8 pF

4 pF

Page 7

CY7C43643AV

PRELIMINARY

AC Test Loads and Waveforms (-10, -15)

R1=330

3.3V

OUTPUT

CL =30 pF

INCLUDING

[8]

JIG AND

SCOPE

AC Test Loads and Waveforms (-7)

I/O

Z0=50

Ω

R2=680

Ω

VCC/2

50Ω

Ω

3.0V

GND

3.0V

GND

CY7C43663AV/CY7C43683AV

ALL INPUT PULSES

90%

10%

≤

90%

10%

3ns

ALL INPUT PULSES

90%

10%

3ns

Switching Characteristics

Over the Operating Range

Parameter Description

CLK

CLKH

CLKL

ENS

RSTS

FSS

Clock Frequency, CLKA or CLKB 133 100 67 MHz Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns Set-Up Time, A

CLKB↑

before CLKA↑ and B

0–35

before

Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB

Set-Up Time, MRS1/MRS2 or PRS LOW before CLKA↑ or CLKB↑

, W/RB, ENB, and MBB before CLKB↑

[9]

Set-Up Time, FS0 and FS1 before MRS1/MRS2 HIGH

BES

SPMS

SDS

SENS

FWS

ENH

Note:

8. C

= 5 pF for t

9. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

Set-Up Time, BE/FWFT before MRS1/MRS2 HIGH 5 7 7.5 ns Set-Up Time, SPM before MRS1/MRS2 HIGH 5 7 7.5 ns Set-Up Time, FS0/SD before CLKA↑ 3 4 5 ns Set-Up Time, FS1/SEN befor e CL KA↑ 3 4 5 ns Set-Up Time, FW F T b e fore CLKA↑ 0 0 0 ns Hold Time, A

CLKB↑

after CLKA↑ and B

0–35

after

Hold Time, CSA, W/RA , ENA, and MBA after CLKA↑; CSB

, W/RB, ENB, and MBB after CLKB↑

DIS

CY7C43643/63/

83AV

-7

CY7C43643/

63/83AV

-10

CY7C43643/

63/83AV

-15

3 4 5 ns

2.5 4 5 ns

5 7 7.5 ns

0 0 0 ns

UnitMin. Max. Min. Max. Min. Max.

Page 8

CY7C43643AV

PRELIMINARY

Switching Characteristics

Parameter Description

RSTH

FSH

BEH

SPMH

SDH

SENH

SPH

SKEW1

SKEW2

WFF

REF

PAE

PAF

PMF

[10]

Hold Time, MRS1/MRS2 or PRS LOW af te r C LKA↑ or CLKB↑

[9]

Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH 1 1 2 ns Hold Time, BE/FWFT after MRS1/MRS2 HIGH 1 1 2 ns Hold Time, SPM after MRS1/MRS2 HIGH 1 1 2 ns Hold Time, FS0/SD after CLKA↑ 0 0 0 ns Hold Time, FS1/SEN after CLKA↑ 0 0 0 ns Hold Time, FS1/SEN HIGH after MRS1/MRS2 HIGH 0 1 2 ns Skew Time between CLKA↑ and CLKB↑ fo r E F/OR

and FF

/IR

Skew Time between CLKA↑ and CLKB↑ for AE and AF7 8 12 ns

Access Time, CLKA↑ to A Propagation Delay Time, CLKA↑ to FF/IR 1 6 1 8 2 10 ns Propagation Delay Time, CLKB↑ to EF/OR 1 6 1 8 2 10 ns Propagation Delay Time, CLKB↑ to AE 1 6 1 8 1 10 ns Propagation Delay Time, CLKA↑ to AF 1 6 1 8 1 10 ns Propagation Delay Time, CLKA↑ to MBF1 LOW or

MBF2

HIGH and CLKB↑ to MBF2 LOW or MBF 1

Over the Operating Range (continued)

and CLKB↑ to B

0–35

CY7C43663AV/CY7C43683AV

CY7C43643/63/

83AV

-7

1 2 2 ns

5 5 7.5 ns

1 6 1 8 3 10 ns

0 6 0 8 0 12 ns

CY7C43643/

63/83AV

-10

CY7C43643/

63/83AV

-15 UnitMin. Max. Min. Max. Min. Max.

HIGH

PMR

MDV

RSF

DIS

Propagation Delay Time, CLKA↑ to B CLKB↑ to A

0–35

[12]

Propagation Delay Time, MBA to A MBB to B

0–35

Va lid

Propagation Dela y Time , MRS1/MRS2 or PRS LOW to AE

LOW , AF HIGH,FF/ IR LO W , E F/ OR LO W and

MBF1

/MBF2 HIGH

Enable Ti me, CSA or W/RA LOW to A CSB

LOW and W/RB HIGH to B

0–35

Disable Time , CSA or W/RA HIGH to A Impedance and CSB

HIGH or W/RB LOW to B

0–35

Valid and

0–35

Active

0–35

[11]

and

Active and

at High

0–35

1 7 2 11 3 12 ns

1 6 2 9 3 11 ns

1 6 1 10 1 15 ns

1 6 2 8 2 10 ns

1 5 1 6 1 8 ns

at High Impedance

PRT

RTR

Notes:

10. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB cycle.

11. Writing data to the Mail1 register when the B

12. Writing data to the Mail2 register when the A

Retransmit Pulse Width 60 60 60 ns Retransmit Recovery Time 90 90 90 ns

outputs are active and MBB is HIGH.

0–35

outputs are active and MBA is HIGH.

0–35

Page 9

CY7C43643AV

PRELIMINARY

Switching W aveforms

Master Reset Loading X and Y with a Preset Value of Eight

CLKA

CLKB

MRS1 MRS2

BE/FWFT

SPM

FS1/SEN, FS0/SD

/IR

/OR

RSTS

RSF

[13]

CY7C43663AV/CY7C43683AV

RSTH

SPMS

BES

FSS

BEH

SPMH

FSH

FWS

WFF

MBF1

Note:

13. PRS1

RSF

must be HIGH during Master Reset.

Page 10

CY7C43643AV

PRELIMINARY

Switching W aveforms

Partial Reset (CY Standard and FWFT Modes)

CLKA

CLKB

PRS

FF/IR

/OR

MBF1

(continued)

RSTS

RSF

[14]

CY7C43663AV/CY7C43683AV

RSTH

WFF

Parallel Program ming of the Almost-Full Flag and Almost-Empty Flag Off set Values after Reset

(CY Standard and FWFT Modes)

[15]

CLKA MRS1

MRS2

FSS

FSH

SPM

FSS

FSH

FS1/SEN, FS0/SD

FF/

WFF

ENS

ENH

ENA

0−35

Notes:

14. MRS1

15. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.

16. t

/MRS2 must be HIGH during Partial Reset.

is the minimum time between the rising CLKA edge and a rising CLKB for FF/IR to transition HIGH in the next cycle. If the time between the rising

SKEW1

edge of CLKA and rising edge of CLKB is less than t

AF Offset (Y)

, then FF/IR may transition HIGH one cycle later than shown.

SKEW1

AE Offset (X)

First Word to FIFO

SKEW1

[16]

Page 11

CY7C43643AV

PRELIMINARY

Switching W aveforms

Serial Programming of the Almost -Full Flag and Almost-Empty Flag Offset Values (CY Standard and FWFT Modes)

CLKA

MRS1

MRS2

SPM

FF/IR

FS1/SEN

FS0/SD

[18]

FSS

(continued)

FSH

SPH

[17]

SENS

SENH

SDS

AF Offset (Y) MSB

SDH

CY7C43663AV/CY7C43683AV

WFF

SENH

SENS

SDS

AE Offset (X) LSB

SDH

Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)

CLK

CLKH

CLKL

CLKB

/OR

HIGH

CSB

W/RB

MBB

ENS

ENH

ENS

ENH

ENStEN

ENB

[19]

offset (Y) then AE offset (X).

[19]

0–35

(Standard Mode)

0–35

MDV

Previous Data

(FWFT Mode)

Notes:

17. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.

18. Programmable offsets are written serially to the SD input in the order AF

19. Read From FIFO.

No Operation

[19]

DIS

Page 12

CY7C43643AV

PRELIMINARY

Switching W aveforms

Port B W ord Read Cycle Timing for FIFO (CY Standard and FWFT Modes)

CLKB

/OR

CSB

W/RB

MBB

ENB

0–17

(Standard Mode)

0–17

(FWFT Mode)

HIGH

(continued)

MDV

ENS

ENH

Previous Data

CY7C43663AV/CY7C43683AV

[20]

No Operation

DIS

Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes)

CLKB

/OR

HIGH

CSB

W/RB

MBB

ENStENH

ENB

0–8

(Standard Mode)

0–8

(FWFT Mode)

Notes:

20. Unused bytes B

21. Unused bytes B

MDV

Previous Data

MDV

contains all zeroes for word-size reads.

18–35

, B

9–17

18–26

, and B

contain all zeroes for byte-size reads.

27–35

[21]

DIS

No Operation

Page 13

CY7C43643AV

CY7C43663AV/CY7C43683AV

Switching W aveforms

PRELIMINARY

(continued)

OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)

CLK

CLKH

CLKL

CLKA

CSA W/RA

LOW

HIGH

ENS

MBA

ENS

ENA

/IR

0–35

CLKB

HIGH

[23]

SKEW1

CLKH

CLKL

[22]

REF

/OR

CSB

W/RB

MBB

FIFO Empty

LOW

HIGH

LOW

CLK

ENB

0–35

Notes:

22. If Port B size is word or byte, EF

23. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output

SKEW1

register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t of the first word to the output register may occur one CLKB cycle later than shown.

Old Data in FIFO Output Register

is set LOW by the last word or byte read from the FIFO, respectively.

ENStENH

REF

, then the transition of OR HIGH and load

SKEW1

Page 14

CY7C43643AV

CY7C43663AV/CY7C43683AV

Switching W aveforms

PRELIMINARY

(continued)

EF Flag Timing and First Data Read F all Through when FIFO is Empty (CY Standard Mode)

CLK

CLKH

CLKL

CLKA

CSA

W/RA

LOW

HIGH

ENS

ENH

MBA

ENS

ENH

ENA

/IR

0–35

HIGH

SKEW

[24]

CLKH

CLKL

CLKB

REF

/OR

FIFO Empty

CLK

REF

[22]

CSB

W/RB

MBB

LOW

HIGH

LOW

ENB

0–35

Note:

24. t

is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the

SKEW1

rising CLKA edge and rising CLKB edge is less than t

ENS

ENH

, then the transition of EF HIGH may occur one CLKB cycle later than shown.

SKEW1

Page 15

CY7C43643AV

PRELIMINARY

Switching W aveforms

IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)

CLKB

CSB

W/RB

MBB

ENB

/OR

0–35

CLKA

/IR

LOW

HIGH

LOW

HIGH

Previous Word in FIFO Output Regis ter

FIFO Full

CLKH

CLK

(continued)

CLKL

ENH

ENS

SKEW1

Next Word From FIFO

[26]

CLKHtCLKL

CLK

WFF

CY7C43663AV/CY7C43683AV

[25]

WFF

CSA

W/RA

LOW

HIGH

MBA

ENA

0–35

Notes:

25. If Port B size is word or byte, t

26. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the

SKEW1

rising CLKB edge and rising CLKA edge is less than t

is referenced to the rising CLKB edge that reads the last word or byte write of the long-word, respectively.

SKEW1

ENS

ENH

ENStENH

To FIFO

, then IR may transition HIGH one CLKA cycle later than shown.

SKEW1

Page 16

CY7C43643AV

CY7C43663AV/CY7C43683AV

Switching W aveforms

PRELIMINARY

(continued)

FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode)

CLK

CLKH

CLKL

CLKB

CSB

W/RB

MBB

LOW

HIGH

LOW

ENStENH

ENB

/OR

0–35

HIGH

Previous Word in FIFO Output Register

SKEW1

Next Word From FIFO

[27]

CLKH

CLKL

CLKA

WFF

/IR

FIFO Full

CLK

WFF

[25]

CSA

W/RA

LOW

HIGH

MBA

ENA

0−35

Note:

27. t

is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the

SKEW1

rising CLKB edge and rising CLKA edge is less than t

ENH

ENS

ENH

tDHt

, then the transition of FF HIGH may occur one CLKA cycle later than shown.

SKEW1

Page 17

CY7C43643AV

PRELIMINARY

Switching W aveforms

Timing for AF when FIFO is Almost Full (CY Standard and FWFT Modes)

CLKA

ENA

CLKB

ENB

Timing for AE

CLKA

ENA

[D–(Y1+1)] Words in FIFO

when FIFO is Almost Empty (CY Standard and FWFT Modes)

(continued)

ENS

PAF

ENH

SKEW2

(D–Y)Words in FIFO

ENS

ENH

[31]

CY7C43663AV/CY7C43683AV

[28, 29, 30, 35]

PAF

[32, 33, 35]

[34]

SKEW2

CLKB

X1 Word in FIFO1

PAE

(X+1)Words in FIFO1

ENS

ENH

PAE

ENB

Notes:

28. FIFO Write (CSA read from the FIFO.

29. D = Maximum FIFO Depth = 1K for the CY7C43643, 4K for the 43663, and 16K for the CY7C43683.

30. If Port B size is word or byte, t

31. t

32. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been

33. If Port B size is word or byte, AE

34. t

35. Programmable flag deasserts one clock cycle less than IDT’s equivalent (72V36x3). When FIFO is operated at the almost empty/full boundary, there may

is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the

SKEW2

rising CLKA edge and rising CLKB edge is less than t read from the FIFO.

is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the

SKEW2

rising CLKA edge and rising CLKB edge is less than t be an uncertainty of up to 2 clock cycles for flag deassertion, but the flag will always be asserted exactly when the FIFO content reaches the programmed

value. Refer to “Designing with CY7C436xx Synchronous FIFOs” application note for more details on flag uncertainties.

= LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been

is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

SKEW2

, then AF may transition HIGH one CLKB cycle later than shown.

SKEW2

is set LOW by the last word or byte read from FIFO, respectively.

, then AE may transition HIGH one CLKB cycle later than shown.

SKEW2

Page 18

CY7C43643AV

Switching W aveforms

(continued)

Timing for Mail1 Register and MBF1

CLKA

CSA

W/RA

MBA

ENA

0–35

CLKB

MBF1

PRELIMINARY

Flag (CY Standard and FWFT Modes)

ENH

ENS

ENH

PMF

ENS

CY7C43663AV/CY7C43683AV

[36]

PMF

CSB

W/RB

MBB

ENB

0−35

Note:

36. If Port B is configured for word size, data can be written to the Mail1 register using A valid data (B inputs). In this second case, B

will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A

18–35

0–8

FIFO Output Register

will have valid data (B

MDV

will be indeterminate).

9–35

PMR

ENS

W1 (Remains valid in Mail1 Register after read)

0–17

are “Don’t Care” inputs). In this first case B

18–35

ENH

0–8

DIS

are “Don’t Care”

9–35

0–17

will have

Page 19

CY7C43643AV

PRELIMINARY

Switching W aveforms

Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)

CLKB

CSB

W/RB

MBB

ENB

0–35

CLKA

MBF2

(continued)

ENS

ENH

PMF

CY7C43663AV/CY7C43683AV

[37]

PMF

CSA

W/RA

MBA

ENA

0−35

FIFO Retransmit Timing

RT1

ENB

EFB/FFA

FIFO2 Output Register

[37, 38, 39, 40 ]

MDV

PMR

ENS

W1 (Remains valid in Mail2 Register after read)

PRT

ENH

DIS

RTR

Notes:

37. If Port B is configured for word size, data can be written to the Mail2 register using B data (A In this second case, A

38. Clocks are free-running in this case. CY standard mode only.

39. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t

40. For the AE and AF flags, two clock cycles are necessary after t

will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B

18–35

will have valid data (A

0–8

will be indeterminate).

9–35

RTR

to update these flags.

0–17

are don’t care inputs). In this first case A

18–35

0–8

will have valid

0–17

are “Don’t Care” inputs).

9–35

RTR

Page 20

CY7C43643AV

PRELIMINARY

Signal Description

Master Reset (MRS1

The FIFO memory of the CY7C436X3AV undergoes a complete reset by taking its associated Master Reset (MRS1 MRS2

) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FF Output Ready flag (EF LOW , and the Almost Full flag (AF forces the Mailbox flag (MBF1 register HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag is set HIGH aft er two clock cycle s to begin normal operation. A Master Reset must be performed on the FIFO after power up, before data is written to its memory.

A LOW-to-HIGH transition on a FIFO Master Reset (MRS1 MRS2

) input latches the value of the Big Endian (BE) input, determining the order by which bytes are transferred through Port B.

A LOW-to-HIGH transition on a FIFO reset (MRS1 input latches the values of the Flag Select (FS0, FS1) and Serial Programming Mode (SPM most Full and Almost Empty offset programming method (see Almost Empty and Almost Full flag offs et progr amming belo w).

Partial Reset (PRS

Each of the t wo FIFO memories of the CY7C4 36X3AV undergoes a limited reset by taking its associated Partial Reset (PRS

) input LO W f or at leas t four P ort A clo ck ( CLKA) and four Port B clock (CLKB) LO W-t o-HIGH trans itions. The P artial Reset inputs can switch asynchronously to the clocks. A Partial Reset initial izes the internal read and write poi nters and f orces the Full/Input Ready flag (FF Ready flag (EF and the Almost F ull flag (AF the Mailbo x fl ag (MBF1 HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation.

Whatever flag offsets, programming method (parallel or serial), and timing mode (FWFT or CY Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will remain unchanged upon completion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be inconvenient.

Big Endian/First-Word Fall-Through (BE/FWFT

This is a dual-purpose pi n. At the time of Master Reset , the BE select function is active, permitting a choice of Big or Little Endian byte arrangement for data written to or read from Port B. This selection determines the order by which bytes (or words) of data ar e t ransferred throug h t his port. F or the f ol low ing illustrations, assume that a byte (or word) bus size has been selected for Port B.

A HIGH on the BE/FWFT MRS2

) inputs go from LOW to HIGH will select a Big Endian arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the long-word written to Port A will be transferred to Port B first; the least

/OR) LOW, the Almost Empty flag (AE) LOW,

MRS2

)

/IR) LOW, the Empty/

/OR) LOW, the Almost Empty fl ag (AE)

) HIGH. A Master Reset also

, MBF2) of the parallel mailbox

, MRS2)

) inputs for choosing the Al-

/IR) LOW, the Empty/Output

) HIGH. A Partial Reset also forces

, MBF2) of the par all el mail bo x regi ster

)

input when the Master Reset (MRS1,

CY7C43663AV/CY7C43683AV

significant b yte (word) of the long -word written to P ort A will be transferred to Port B last.

A LOW on the BE/FWFT MRS2

) inputs go from LOW to HIGH will select a Littl e Endian

arrangement. When data is moving in the direction from Port

A to Port B, the least significant byte (word) of the long-word written to Port A will be transferred to Port B first; the most significant b yte (word) of the long -word written to P ort A will be transferred to Port B last.

After Master Reset, t he FWFT select func tion is activ e, permitting a choice between two possible timing modes: CY Standard Mode or First-Word Fall-Through (FWFT) Mode. Once the Master R eset (MRS 1 BE/FWFT CLKA will select CY Standard Mode . This mode uses the Empty Flag function (EF words present i n the FIFO memory. It uses the Full Flag function (FF

free space f or writi ng. In CY Standard Mode, every word read from the FIFO, including the first, must be requested using a formal read operation.

Once the Master Reset (MRS1 on the BE/FWFT of CLKA will select FWFT Mode. This mode uses the Output Ready function (OR) to indicate whether or not there is valid data at the data outputs (B function (IR) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FI FO goes direct ly to data outputs, no r ead request necessary. Subsequent words must be accessed by performing a f ormal r ead operation.

Followi ng Ma ster Reset, the level applied to the BE/FWFT put to choose the desired timing mode must remain static throughout the FIFO ope ration.

Programming the Almost Empty and Almost Full Flags

T w o r egist ers i n t he CY7C436 X3AV are us ed t o hol d the of fset values fo r the Almost Empty and Almost Ful l flags. The P ort B Almost Empty flag (AE Almost Full flag (AF each register name corre spond s with pr eset v a lues during t he reset of a FIFO , programmed in par allel using the FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1).

To load a FIFO’s Almost Empty flag and Almost Ful l fl ag offse t registers with one of the three preset values listed in Ta ble 1 , the Serial Program Mode (SPM select inputs m ust be HIGH during the LO W-to-HIGH tr ansition of its Master Reset i nput (MRS1 the preset value of 64 into X and Y, SPM be HIGH when the FIFO reset (MRS1 When using one of the preset values for the flag offsets, the FIFO can be reset simultaneously or at different times.

To progr am the X and Y registers from Port A, perform a Master Reset on both FIFOs simultaneously with SPM FS0 and FS1 LOW during the LOW-to-HIGH transition of MRS1 to the FIFO do not store data in RAM but loa d the offse t registers in the order Y and X. The Port A data inputs used by the offset registers are (A CY7C436X3AV, respectively. The highest numbered input is used as the most significant bit of the binary number in each

input at the second LOW-to-HIGH transition of

) to indicate whether or not the FIFO memory has any

, MRS2. After this re s e t is co mp le te , th e firs t tw o w r ite s

input whe n the Mast er Res et (MRS1,

, MRS2) input is HIGH, a HIGH on the

) to indicate whether or not there are any

, MRS2) input is HIGH, a LO W

input of the second LOW-to-HIGH transition

). It also uses the Input Ready

0–35

) offset regi ster i s label ed X. The Port A

) offset register is labeled Y. The index of

) and at least one of the flag-

, MRS2). For example, t o load

), (A

0–9

, FS0 and FS1 must

, MRS2) returns HIGH.

), or (A

0–11

0–13

in-

HIGH and

), for the

Page 21

CY7C43643AV

PRELIMINARY

case. Valid programming values for the registers range from 0 to 1023 for the CY7C43643AV; 0 to 4095 for the CY7C43663AV; 0 to 16383 for the CY7C43683AV. (See footnote #35) Be fore progr amming the offset r egister s, FF HIGH. FIFOs begin normal operation after programming is complete.

To program the X and Y registers serially, initiate a Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN ing the LOW-to-HIGH transition of MRS1 reset is complete, the X and Y register values are loaded bitwise through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/SEN four, or tw enty-eight b it write s are ne eded to complet e the pr ogramming for the CY7C436X3AV, respect ively. The two registers are written in the order Y then finally X. The first-bit write stores the most si gnificant bit of the Y regi ster and the last-bit write stores the l east si gnif icant bit of the X r egist er . Each register value can be programmed from 0 to 1023 (CY7C43643AV), 0 to 4095 (CY7C43663AV), or 0 to 16383 (CY7C43683AV).

When the opt ion t o prog r am the o ffset r egist ers serial l y is chosen, the Port A Full/Input Ready (FF until all re gister bits are wri tten. FF to-HIGH transit ion of CLKA after the last bit is loaded to all ow normal FIFO operation.

SPM

, FS0/SD, and FS1/SEN function the same way in both

CY Standard and FWFT modes.

FIFO Write/Read Operation

The state of the Port A data (A A Chip Select (CSA The A CSA ister outputs when both CSA

Data is loaded into the FIFO from the A to-HIGH transi tion of CLKA when CSA ENA is HIGH, MBA is LOW , and FF FIFO writes on Port A are independent of any conc urrent Port B operation.

The Port B control signals are identical to those of Port A with the exception that the Port B Write/Read select (W inverse of the Port A Write/Read select (W/RA the Port B data (B Select (CSB lines are in the high-impedance state when either CSB is HIGH or W when CSB

Data is read from the FIFO to the B HIGH transition of CLKB when CSB ENB is HIGH, MBB i s LO W, and EF FIFO reads and writes on Port B are independent of any concurrent Port A operation.

The set-up and hold time constraint s to the port clocks for the port Chip Selects and Write/Read Select s are only for enabl ing write and read operations and are not related to high-impedance control of the dat a outputs . If a port enabl e is LO W during a clock cycle, the port’s Chip Select and Write/Read Select may change states during the s et- up and hold time windo w of the cycle.

When operating the FIFO in FWFT Mode with the Output Ready flag LOW, the next word written is automatically sent to

lines are in the high-impedance state when either

0–35

or W/RA is HIGH. The A

) and P o rt B Write/Read se lect (W/RB). The B

/RB is LOW. The B

is LOW and W/RB is HIGH.

) and Port A Write/Read Select (W/RA).

) lines is controlled by the Port B Chip

0–35

input is LOW. Twenty, twenty-

/IR is set HIGH by the LOW-

) lines is controlled by Port

0–35

lines are active mail 2 reg-

0–35

and W/RA are LOW.

0–35

, MRS2. After this

/IR) flag remains LOW

inputs on a LOW-

0–35

is LOW, W/RA is HIGH,

/IR is HIGH. (see Table 2).

lines are active outputs

outputs by a LOW-to-

0–35

is LOW, W/RB is HIGH,

/OR is HIGH (see Table 3).

/IR is set

HIGH dur-

/RB) is the

). The state of

0–35

CY7C43663AV/CY7C43683AV

the FIFO’s output register by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH, data residing in the F IFO’s memory array is cloc k ed to t he output reg- ister only when a rea d is sel ec ted usi ng the p ort’s Chip Select, Write/Read Select, Enable, and Mailbox Select.

When operating the FIFO in CY Standar d Mode , r egardle ss o f whether the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is clocked to the output register only when a read is selected using the port’s Chip Select, Write/ Read Select, Enable, and Mailbox Sel ect.

Synchronized FIFO Flags

Each FIFO is synchronized to its port clock through at least two flip-flop stages . This is done to improv e flag-sign al reliability by reducing the probability of the metastable events when CLKA and CLKB operate asynchronously to one another. EF OR and AE chronized t o CLKB. Table 4 shows the relati onship of each port flag to the FIFO.

Empty/Output Ready Fla gs (EF

These are dual-purpose flags. In the FWFT Mode, the Output Ready (OR) function is sel ected. When the Out put Ready fl ag is HIGH, new dat a is prese nt in the FIFO ou tput regi ster . When the Output Ready flag i s LOW, the previous data word r emains in the FIFO output register and any FIFO reads are ignored.

In the CY Standard Mode, the Empty Flag (EF selected. When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory for reading to the output register. When Empty Flag is LOW, the previous data word remains in the FIFO output register and any FIFO reads are ignored.

The Empty/Output Ready f lag of a FIFO is synchr onized to the port clock that reads data from its array. For both the FWFT and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2.

In FWFT Mode, from t he time a wor d is written t o a FIFO , it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three cycles have not elapsed s ince the ti me the word w as written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transiti on of the synchronizing clock occurs, simultaneously f or cing th e Outpu t Ready flag HI GH and shi fti ng the word to the FIFO output register.

In the CY Standard Mode , f rom the time a word is written to a FIFO, the Empty flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty flag synchronizin g clock. Theref ore, a n Empty flag is LO W if a wor d in memory is the next data to be sent to the FIFO output register and two cy cles have not el apsed since the time the word was written. The Empt y flag of the F IFO remai ns LOW unt il the second LOW -to-HIGH tr ansiti on of the synchroniz ing clock occurs, for cing the Empty flag HIGH; only then can data be read.

A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t after the write. Otherwise, the subsequent clock cycle will be the first synchronization cycle.

are synchroniz ed to CLKA. FF/IR and AF are syn-

/OR)

) function is

or grea ter

SKEW1

Page 22

CY7C43643AV

PRELIMINARY

Full/Input Ready Flags (FF/IR)

This is a dual-purpose flag. In FWFT Mode, the Input Ready (IR) function is selected. In CY Standard Mode, the Full Flag (FF

) function is selected. For both timing modes, when the Full/Input Read y flag i s HIGH, a mem ory locatio n is fr ee in th e SRAM to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and any writes to the FIFO are ignored.

The Full/Input Read y flag of a FIFO is synchr onized to t he port clock that writ es data to its arra y. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its write pointer is inc rement ed. The st ate machi ne that cont rols a Full/ Input Ready flag monitors a write pointer and read pointer comparator th at indicates when the FIFO SRAM status is f ull , full–1, or full–2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/ Input Ready flag HIGH.

A LOW- to-HI GH transi tion on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t read. Otherwise, the subsequent clock cycle can be the first synchronization cycle.

Almost Empty Flags (AE

)

The Almost Empty flag of the FIFO is synchronized to port B clock. The state machine that controls an Almost Empty flag monitors a write pointe r an d read poi nter compar ator that indi cates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The Almost Empty state is defined by the contents of register X for AE loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Empty flag is LOW when its F IFO contains X or less wor ds and is HIGH when its FIFO contains (X+1) or more words. (See footnote #35)

Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost Empty flag to reflec t the ne w lev e l of fill. The ref or e, the Almost Empty flag of a FIFO contain ing (X+1) or more words re mains LOW if tw o cycles of its synchronizing clock ha ve not elapsed since the write that filled the memory to the (X+1) level. An Almost Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost Empty flag synchronizing clock begins the first synchro nizat ion cycl e if it oc curs at time t the write that fills t he FIFO to (X+1) wo rds. Otherwis e, the subsequent synchronizing clock cycle will be the first synchronization cycle.

Almost Full Flags (AF

)

The Almost Full flag of the FIFO is synchronized to port A clock. The st ate machine that controls an Almos t Full flag monitors a write pointer and r ead pointer compar ator that ind icates when the FIFO SRAM status is almost full, almost full–1, or

or greater after the

SKEW1

. These registers are

or gr eat er af ter

SKEW2

CY7C43663AV/CY7C43683AV

almost full–2. The Almost Full state i s defined by the contents of register Y for AF values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almos t Full flag offset programming above). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024–Y), (4096–Y), or (16384–Y), f or the CY7C436X3AV respectively. An Almost Full flag is HIGH when the number of words in its FIFO is less than or equal to [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for the CY7C436X3AV respectively.

Two LOW-to-HIGH tra nsitions of the Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing [1024/4096/16384–(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in mem ory to [102 4/4 096/16384 –(Y+1 )] . An A lm ost F ull flag is set HIGH by the second LOW-to-HIGH transition of its synchronizin g cloc k after the FI FO re ad that reduces t he num ber of words in memory to [1024/409 6/16384–(Y+1)]. A LOWto-HIGH transition of an Almost Full flag synchronizing clock begins the fi rst synchroni zation cy cle if i t occurs at time t or greater after the read that reduces the number of words in memory to [1024/4096/16384–(Y+1)]. Otherwise, the subsequent synchronizing clock cycle will be the first synchronization cycle.

Mailbox Regist ers

Each FIFO has a 36-bit bypass registe r to pass command and control information between Port A and Port B without putting it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usable wi dth of both the Mail1 and Mail2 registers matches the sel ected bus size of Port B.

A LOW-to-HIGH transition on CLKA writes A Mail1 Register when a Port A write is selecte d by CSA and ENA with MBA HIGH. If the selected Port A bus size is also 36 bits, then the usable width of the Mail1 Register employs data l ines A then the usabl e widt h of the Mai l1 Regi ster e mplo ys dat a li nes A

. (In this case, A

0−17

ed Port A bus size is 9 bits, then the usable width of the Mail1 Register employs data lines A “Don’t Care” inputs.)

A LOW-to-HIGH transition on CLKB writes B Mail2 Register when a Port B write is selected by CSB and ENB with MBB HIGH. If the selected Port B bus size is also 36 bits, then the usable width of the Mail2 Register employs data l ines B then the usabl e widt h of the Mai l2 Regi ster e mplo ys dat a li nes B

. (In this case, B

0–17

ed Port B bus size is 9 bits, then the usable width of the Mail2 Register employs data lines B “Don’t Care” inputs.)

Writing data to a mail register sets its corresponding flag (MBF1

or MBF2) LOW. Attempted writes to a mail regi ster are

ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus

comes from the FIFO outpu t regis ter i f the port Mailbo x Selec t input is LOW and from the mail register if the port Mailbox Select input is HIGH.

. These registers are loaded with preset

data to the

0−35

, W/RA,

. If the selected P ort A bus si ze is 18 bit s,

0−35

are don’t care inputs.) If the select-

18−35

. (In this case, A

0–8

. If the select ed P ort B bus size is 18 bi ts,

0–35

are don’t care i nputs .) I f the s el ect-

18–35

. (In this case, B

0−8

data to the

0−35

9−35

, W/RB,

9−35

SKEW2

are

Page 23

CY7C43643AV

PRELIMINARY

The Mail1 Register flag (MBF1) is set HIGH by a LOW-toHIGH transition on CLKB when a Port B read is selected by CSB

, W/RB, and ENB with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B size, 18 bit s of m ailbo x da ta are pl aced on B B

are indeterminate.) For a 9-bit bus size, 9 bits of mail-

18–35

box data are placed on B

. (In this cas e, B

0–8

minate.) The Mail2 Register flag (MBF2

) is set HIGH by a LOW-toHIGH transition on CLKA when a Port A read is selected by CSA

, W/RA, and ENA with MBA HIGH.

For a 36-bit bus size, 36 bits of mailbox data are placed on A

. For a n 18-b it bu s size , 18 bi ts of mailbo x dat a are pl aced

0–35

on A

. (In this c ase, A

0–17

are indeterminate.) For a 9-bit

18–35

bus size, 9 bits of mailbox data are placed on A case, A

are indeterminate.)

9–35

The data in a mail register remains intact after it is read and changes only when new data is written to the register. The Endian Select feature has no effect on the mailbox data.

Bus Sizing

The Port B bus can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data read from FIFO. The levels applied to the Por t B Bus Size Select (SIZE) and the Bus Match Select ( BM) determine the P ort B b us size . These le v els should be static through out FIFO operat ion. Bot h bus size selections are implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH.

Two different methods for sequencing data transfer are available for Port B when the bus size selection is either byte-or word-siz e. They ar e refer red to as Big Endian (most significant byte first) and Little Endian (least significant byte first). The level applied to the Big Endian Select (BE) input during the LOW-to-HIGH transition of MRS1

/MRS2 selects the endian method that will be ac tive duri ng F IFO oper ation. BE is a don’t care input when the bus size selected for Port B is long-word. The endian method is implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH.

Only 36- bit long- word dat a is w ritt en to the FIFO mem or y on the CY7C436X3AV. Bus-matching operations are done after data is read from the FIFO. These bus-matching operations are not available when transferring data via mailbox registers.

. For an 18-bi t bus

0–35

. (In thi s case ,

0–17

are indeter-

9–35

0–8

. (In this

CY7C43663AV/CY7C43683AV

Furthermore, both the word - and byte- siz e b us sele ctions limi t the width of the data bus that can be used for mail register operations . In this case, only those byt e lanes belongi ng to the selected word- or byte-size bus can carry mailbox data. The remaining data outputs will be indeterminate. The remaining data inputs will be don’t care inputs. For example, when a word-size bus is selected, then mailbox data can be transmitted only between A selected, then mailbox data can be transmitted only between A

0–8

and B

0–8

Bus-Matching FIFO Reads

Data is read from the FIFO RAM in 36-bit long-word increments. If a long-w ord bus s ize i s im plement ed, th e ent ire long word immediately shifts to the FIFO output register. If byte or word size is implemented on Port B, only the first one or two bytes appear on t he selec ted portion of the FIFO out put reg ister, with the res t of the long-word stored in auxiliary registers. In this case, subsequent FIFO reads output the rest of the long-word to the FIFO output register.

When reading data from the FIFO in the byte or word format, the unused B

Retransmit (RT

0–35

)

The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. Retransmit function applies to CY standar d mo de only.

The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one wor d has been r ead si nce the l ast rese t cycle. A LOW pulse on RT the first phy sical locat ion of the FIFO . CLKA and CLKB ma y be free running but ENB must be disabled during and t the retrans mit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated duri ng a retransmit cycle. Data written to the FIFO after activation of RT of the FIFO can be repeatedly ret ransmitted.

0–17

and B

. When a byte-size bus is

0–17

outputs are indeterminate.

resets the internal read pointer to

are transmitte d also . The full depth

RTR

after

Page 24

CY7C43643AV

BYTE ORDER ON PORT A:

BE BM SIZE

XLX

BE BM SIZE

HHL

BE BM SIZE

LHL

PRELIMINARY

27–35

18–26

(a) LONG WORD SIZE

18–26

(b) WORD SIZE – BIG ENDIAN

18–26

9–17

A B

9–17

C D

9–17

CY7C43663AV/CY7C43683AV

0–8

Write to FIFO

Read from

FIFO

0–8

1st: Read from FIFO

0–8

2nd: Read from FIFO

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

BE BM SIZE

HHH

BE BM SIZE

LHH

27–35

18–26

9–17

(d) BYTE SIZE – BIG ENDIAN

27–35

18–26

9–17

(e) BYTE SIZE – LITTLE ENDIAN

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

0–8

3rd: Read from

FIFO

0–8

4th: Read from

FIFO

0–8

1st: Read from

FIFO

0–8

2nd: Read from

FIFO

0–8

3rd: Read from

FIFO

0–8

4th: Read from

FIFO

Page 25

CY7C43643AV

PRELIMINARY

..able

Table 1. Flag Programming

SPM FS1/SEN FS0/SD MRS1

H H H H H L H L H H L L L H L L H H L L H L L L

Table 2. Port A Enable Function

CSA

H X X X X In high-impedance state None

L H L X X In high-impedance state None LHHL↑ In high-impedance state FIFO write LHHH↑ In high-impedance state Mail1 write L L L L X Active, Mail2 register None LLHL↑ Active, Mail2 register None L L L H X Active, Mail2 register None LLHH↑ Active, Mail2 register Mail2 read (set MBF2

W/RA ENA MBA CLKA A

MRS2

↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑

0–35

CY7C43663AV/CY7C43683AV

X and Y Registers

64 16

Parallel programming via Port A

Serial programm ing via SD

Reserved Reserved Reserved

Outputs Port Function

[41]

HIGH)

Table 3. Port B Enable Function

CSB

H X X X X In high-impedance state None

L L L X X In high-impedan ce state None LLHL↑ In high-impedance state None LLHH↑ In high-impedance state Mail2 write L H L L X Active, FIFO outp ut r egister None LHHL↑ Active, FIFO output register FIFO read L H L H X Ac ti ve, Mail1 register None LHHH↑ Active , Mail1 register Mail1 read (set MBF1

Note:

41. X register holds the offset for AE

W/RB ENB MBB CLKB B

; Y register holds the offset for AF.

Outputs Port Function

0–35

HIGH)

Page 26

CY7C43643AV

PRELIMINARY

CY7C43663AV/CY7C43683AV

Table 4. FIFO Flag Operation (CY Standard and FWFT Modes)

Number of Wor ds in FIFO Memory

[35, 42, 43, 44, 45]

Synchronized to CLKB Synchronized to CLKA

CY7C43643AV CY7C43663AV CY7C43683AV EF/OR AE AF FF/IR

0 0 0 L L H H

1 TO X 1 TO X 1 TO X H L H H

(X+1) to

[1024–(Y+1)]

(1024–Y) to 1023 (4096–Y) to 4095 (16384–Y) to

(X+1) to

[4096–(Y+1)]

(X+1) to

[16384–(Y+1)]

H H H H

H H L H

16383

1024 4096 16384 H H L L

T able 5. Data Size for FIFO Long-Word Reads

Size Mode

BM SIZE BE A

[46]

27–35

Data Written to FIFO Data Read From FIFO

18–26

9–17

0–8

27–35

18–26

9–17

LXXABCDABCD

Table 6. Data Size for Word Reads

Size Mode

BM SIZE BE A

[46]

27–35

Data Written to FIFO Read No. Data Read From FIFO

18–26

9–17

0–8

9–17

0–8

HLHABCD1AB

2CD

HLLABCD1CD

2AB

0–8

Table 7. Data Size for Byte Reads from FIFO

Size Mode

[46]

BM SIZE BE A

27–35

Data Written to FIFO Read No.

18–26

9–17

0–8

Data Read From

FIFO

0–8

HHHABCD1 A

2B 3C 4D

HHLABCD1 D

2C 3B 4A

Notes:

42. X is the Almost Empty offset for FIFO used by AE programming.

43. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

44. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT Mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.

45. The OR and IR functions are active during FWFT mode; the EF

46. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

. Y is the Almost Full offset for FIFO used by AF. Both X and Y are selected during a FIFO reset or Port A

and FF functions are active in CY Standard Mode.

Page 27

CY7C43643AV

PRELIMINARY

CY7C43663AV/CY7C43683AV

3.3V 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns)

7 CY7C43643AV–7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43643AV–10AC A128 128-Lead Thin Quad Fl at Package Commercial 15 CY7C43643AV–15AC A128 128-Lead Thin Quad Fl at Package Commercial

Orde ring Code

Package

Name

Package

Type

3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns) Ordering Code

7 CY7C43663AV–7AC A128 128-Lead Thin Quad Flat Package Commercial 10 CY7C43663AV–10AC A128 128-Lead Thin Quad Flat P ackage Commercial 15 CY7C43663AV–15AC A128 128-Lead Thin Quad Flat P ackage Commercial

Package

Name

Package

Type

3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns) Ordering Code

7 CY7C43683AV–7AC A128 128-Lead Thin Quad Fla t Package Commercial 10 CY7C43683AV–10AC A128 128-Lead Thin Quad Fla t Package Commercial 15 CY7C43683AV–15AC A128 128-Lead Thin Quad Fla t Package Commercial 15 CY7C43683AV–15AI A128 128-Lead Thin Quad Flat Package Industrial

Shaded areas contain advance information.

Package

Name

Package

Type

Operating

Range

Operating

Range

Operating

Range

Document #: 38-00776-A

Page 28

CY7C43643AV

Package Diagram

PRELIMINARY

128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128

CY7C43663AV/CY7C43683AV

51-85101-A

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Datasheet CY7C43683AV-7AC, CY7C43683AV-15AC, CY7C43683AV-10AC, CY7C43663AV-7AC, CY7C43663AV-15AC Datasheet (Cypress Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual