Datasheet CY7C185A-45DMB, CY7C185A-35DMB, CY7C185A-25DMB, CY7C185A-20DMB Datasheet (Cypress Semiconductor)
Page 1
8K x 8 Static RAM
CY7C185A
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 4, 1999
Features
• High speed
—20 ns
• CMOS for optimum speed/power
• Low active power
—743 mW
• Low standb y Pow e r
—220 mW
• TTL-compatibl e inputs and outputs
• Easy memory expansion wi th CE
1
, CE2 and OE feature s
• Automat ic power-down when deselected
Functional Description
The CY7C185A is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is
provided b y an acti ve LO W Chip Enab le (CE
1
), an activ e HIGH
Chip En able (CE
2
), an active LOW Output Enable (OE), and
three-state driv ers. The dev ice has an automatic power-down
feature (CE
1
), reducing the power consumption by over 70%
when deselected. The CY7C185A is in the standard
300-mil-wide DIP package and leadless chip carrier.
Writing to the device is accomplished when the Chip Enable
one (CE
1
) and Write Enable (WE) inputs are both LOW, and
the Chip Enable two (CE
2
) input is HIGH.
Data on the ei ght I/ O pins (I/ O
0
through I/ O7) is written into the
memory location specified on the address pins (A
0
through
A
12
).
Reading the device is accomplished by taking Chip Enable
one (CE
1
) and Output Enable (OE) LOW, while taking Write
Enable (WE
) and Chip Enable two (CE2) HIGH. Under these
conditions, the contents of the memory location specified on
the address pins will appear on the I/O pins.
The I/O pins remain in a hig h-impeda nce stat e when Chip Enable one (CE
1
) or Output Enable (OE) is HI GH, or W r ite En-
able (WE
) or Chip Enable two (CE2) is LOW.
A die coat is used to ensure alpha immunity.
28
Logic Block Diagram
Pin Configurations
C185A–1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
0
A
10
A
9
A11A
12
I/O
0
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
11
12
19
18
A
6
V
CC
NC
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
GND
Top View
LCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
WE
I/O3I/O
4
I/O
2
I/O
5
A5A
4
8K x 8
ARRAY
INPUT BUFFER
COLUMN DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
CE
2
WE
OE
Top View
DIP
C185A–2
C185A–3
I/O
1
Selection Guid e
[1]
7C185A–20 7C185A–25 7C185A–35 7C185A–45
Maximum Access Time (ns) 20 25 35 45
Maximum Opera ting Current (mA) Military 135 125 125 125
Maximum Standby Current (mA) Military 40/20 40/20 30/20 30/20
Note:
1. For commercial specifications, see the CY7C185 data sheet.
Page 2
CY7C185A
2
Maximum Ratings
(Above which the useful life may be impaired. For use r gui delines, not tested.)
Storage Temperature ......................... .. .......–65°C to +150°C
Ambient Temperature with
Power Applied.............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pi n 14 ) ........ ... .. .............................. –0.5V to +7.0V
DC V oltage Applied to Outputs
in High Z State
[2]
.....................................................–0.5V to + 7. 0 V
DC Input Voltage
[2]
................................................. –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......... ............ ............ ........ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current............. .. .......... .. .......... .......... .. ... >200 mA
Operating Range
Range
Ambient
Temperature
[3]
V
CC
Military
[4]
–55°C to +125°C 5V ± 10%
Electrical Characteristics
Ove r th e Op er ati ng Rang e
[4]
7C185A–20
Parameter Description Te st Condi tions Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
V
V
IL
Input LOW Voltage
[2]
–0.5 0.8 V
I
IX
Input Load Current GND ≤ VI ≤ V
CC
–10 +10
µA
I
OZ
Output Leakage Current GND ≤ V
I
≤ V
CC
, Output Disabled –10 +10
µA
I
OS
Output Short Circuit Current
[5]
VCC = Max., V
OUT
= GND –300 mA
I
CC
V
CC
Operating Supply Current VCC = Max. I
OUT
= 0 mA Military 135 mA
I
SB1
Automati c CE1 Power-Down
Current
Max. VCC, CE1 ≥ V
IH,
Min. Duty Cycle = 100%
Military 40 mA
I
SB2
Automati c CE1 Power-Down
Current
Max. VCC, CE1 ≥ V
CC
–0.3V
V
IN
≥ V
CC
–0.3Vor V
IN
≥ 0.3V
Military 20 mA
Electrical Characteristics
Ove r th e Op er ati ng Rang e
[4]
(continued)
7C185A–25 7C185A–35, 45
Parameter Description T est Condi tions Min. Max. Min. Max. Unit
V
OH
Outp ut HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
2.2 V
CC
V
V
IL
Input LOW Voltage
[2]
–0.5 0. 8 –0.5 0.8 V
I
IX
Input Load Current GND ≤ VI ≤ V
CC
–10 +10 –10 +10
µA
I
OZ
Output Leakage Current GND ≤ V
I
≤ V
CC
, Output Disabled –10 +10 –10 +10
µA
I
OS
Output Short
Circuit Current
[5]
VCC = Max., V
OUT
= GND –300 –300 mA
I
CC
V
CC
Oper ati ng Su pp ly
Current
VCC = Max., I
OUT
= 0 mA Military 125 125 mA
I
SB1
Auto mati c C E
1
Power-Down Current
Max. VCC, CE1 ≥ V
IH,
Min. Dut y Cyc le=100%
Military 40 30 mA
I
SB2
Auto mati c C E
1
Power-Down Current
Max. VCC, CE1 ≥ V
CC
–0.3V
V
IN
≥ V
CC
–0.3V or V
IN
≥ 0.3V
Military 20 20 mA
Notes:
2. V
IL
(min.) = – 3.0V for pulse durations less than 30 ns.
3. TA is the case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Page 3
CY7C185A
3
Capacitance
[6]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 MHz,
V
CC
= 5.0V
10 pF
C
OUT
Output Capacitance 10 pF
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
Ω
R2
255
Ω
30pF
GND
90%
90%
10%
≤
5ns
≤
5
ns
5V
OUTPUT
R2
255
Ω
5
pF
(a) (b)
OUTPUT 1.73V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
R1 481
Ω
10%
Equivalentto: THÉVENIN EQUIVALENT
C185A–4 C185A–5
ALL INPUT PULSES
167
Ω
Page 4
CY7C185A
4
Switching Characteristics
Over t h e Op era t ing Ran ge
[7]
7C185A–20 7C185A–25 7C185A–35 7C185A–45
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 20 25 35 45 ns
t
AA
Address to Data Valid 20 25 35 45 ns
t
OHA
Data Hold from Address Change 3 3 3 3 ns
t
ACE1
CE1 LOW to Data Valid 20 25 35 45 ns
t
ACE2
CE2 HIGH to Data Valid 20 25 35 30 ns
t
DOE
OE LOW to Data Valid 10 12 15 20 ns
t
LZOE
OE LOW to Low Z 3 3 3 3 ns
t
HZOE
OE HIGH to High Z
[8]
8 10 12 15 ns
t
LZCE1
CE1 LOW to Low Z
[9]
5 5 5 5 ns
t
LZCE2
CE2 HIGH to Low Z 3 3 3 3 ns
t
HZCE
CE1 HIGH to High Z
[8, 9]
CE2 LOW to High Z
8 10 15 15 ns
t
PU
CE1 LOW to Power-Up 0 0 0 0 ns
t
PD
CE1 HIGH to Power-Do wn 20 20 20 25 ns
WRITE CYCLE
[10]
t
WC
Write Cycle Time 20 20 25 40 ns
t
SCE1
CE1 LOW to Write End 15 20 25 30 ns
t
SCE2
CE2 HIGH to Write End 15 20 25 30 ns
t
AW
Address Set-Up to Write End 15 20 25 30 ns
t
HA
Address Hold from Write End 0 0 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 0 0 ns
t
PWE
WE Pulse Width 15 15 20 20 ns
t
SD
Data Set-Up to Write End 10 10 15 15 ns
t
HD
Data Hold from Write End 0 0 0 0 ns
t
LZWE
WE HIGH to Low Z 3 5 5 5 ns
t
HZWE
WE LOW to High Z
[8]
7 7 10 15 ns
Notes:
7. Tes t conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V , and output loading of the specified
I
OL/IOH
and 30-pF load capacitance.
8. t
HZOE, tHZCE
, and t
HZWE
are specified with CL = 5 pF as in part (b) of AC T est Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
10. Device is continuously selected. OE, CE = VIL. CE2 = VIH.
Page 5
CY7C185A
5
Switching Waveforms
Notes:
11. Address valid prior to or coincident with CE
transition LOW.
12. WE
is HIGH for read cycle.
13. The internal write time of the memory is defined by the overlap of CE1 LOW , C E2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
14. Data I/O is high impedance if OE = VIH.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
C185A–6
Read Cycle No. 1
[10, 11]
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
HIGH
DATA OUT
V
CC
SUPPLY
CURRENT
CE
2
CE
1
OE
C185A–7
Read Cycle No. 2
[11, 12]
DATA UNDEFINED
HIGH IMPEDANCE
t
HD
t
HZOE
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE2
t
SCE1
t
C185A–8
OE
DATA IN
DATA I/O
ADDRESS
CE
2
CE
1
WE
DATAINVALID
Write Cycle No. 1 (WE Co ntrolled)
[13, 14]
WC
Page 6
CY7C185A
6
Note:
15. If CE
goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued )
t
WC
HIGH IMPEDANCE
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
CE
2
WE
DATA IN
DATA I/O
ADDRESS
t
SCE2
t
SCE1
CE
1
C185A–9
DATAINVALID
Write Cycle No. 2 (CE Controlled)
[13, 14, 15 ]
Page 7
CY7C185A
7
T ypical DC and AC Characteris ti cs
–55 25 125
1.2
1.0
0.8
OUTPUT SOURCE CURRENT (mA)
AMBIENT TEMPERATURE (°C)
0.6
0.4
0.2
0.0
NORMA LIZED I , I
CC
VCC=5.0V
V
IN
=5.0V
I
CC
SB
1.2
1.4
1.0
0.6
0.4
0.2
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
–55 25 125
NORMALIZED t
AA
120
100
80
60
40
20
0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT
VOLTAGE
0.0
0.8
1.4
1.3
1.2
1.1
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED t
AA
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY
VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINKCURRENT
vs. OUTPUT VOLTAGE
NORMA LIZED I , I
CC SB
I
CC
VCC=5.0V
V
CC
=5.0V
T
A
=25°C
V
CC
=5.0V
T
A
=25°C
I
SB
TA=25°C
0.6
0.8
0
I
SB
C185A–10
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
NORMALIZED I
PO
SUPPLY VOLTAGE (V)
TYPICALPOWER-ON CURRENT
vs. SUPPLY
VOLTAGE
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT
LOADING
1.25
1.00
0.75
10 20 30 40
NORMALIZED I
CC
CYCLE FREQUENCY (MHz)
NORMALIZED I
CC
vs. CYCLE TIME
0.0
5.0
0.0
1000
0.50
V
CC
=4.5V
T
A
=25°C
V
CC
=5.0V
T
A
=25°C
V
CC
=0.5V
C185A–11
Page 8
CY7C185A
8
Truth Table
CE1CE2WE OE Input/Output Mode
H X X X High Z Deselect/
Power-Down
X L X X High Z Deselect
L H H L Data Out Read
L H L X Data In Write
L H H H Hi gh Z Deselect
Address Designators
Address
Name
Address
Function
Pin
Number
A4 X3 2
A5 X4 3
A6 X5 4
A7 X6 5
A8 X7 6
A9 Y1 7
A10 Y4 8
A11 Y3 9
A12 Y0 10
A0 Y2 21
A1 X0 23
A2 X1 24
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
20 CY7C185A–20DMB D22 28-Lead (300-Mil) CerDIP Military
25 CY7C185A–25DMB D22 28-Lead (300-Mil) CerDIP Military
35 CY7C185A–35DMB D22 28-Lead (300-Mil) CerDIP Military
45 CY7C185A–45DMB D22 28-Lead (300-Mil) CerDIP Military
Page 9
CY7C185A
9
MILI TAR Y SPECIFICATIONS
Group A Subgroup Testing
Document #: 38–00114–C
DC Characteristics
Parameter Subgroups
V
OH
1, 2, 3
V
OL
1, 2, 3
V
IH
1, 2, 3
VIL Max. 1, 2, 3
I
IX
1, 2, 3
I
OZ
1, 2, 3
I
OS
1, 2, 3
I
CC
1, 2, 3
I
SB1
1, 2, 3
I
SB2
1, 2, 3
Switching Characteristics
Parameter Subgroups
READ CYCLE
t
RC
7, 8, 9, 10, 11
t
AA
7, 8, 9, 10, 11
t
OHA
7, 8, 9, 10, 11
t
ACE1
7, 8, 9, 10, 11
t
ACE2
7, 8, 9, 10, 11
t
DOE
7, 8, 9, 10, 11
WRITE CYCLE
t
WC
7, 8, 9, 10, 11
t
SCE1
7, 8, 9, 10, 11
t
SCE2
7, 8, 9, 10, 11
t
AW
7, 8, 9, 10, 11
t
HA
7, 8, 9, 10, 11
t
SA
7, 8, 9, 10, 11
t
PWE
7, 8, 9, 10, 11
t
SD
7, 8, 9, 10, 11
t
HD
7, 8, 9, 10, 11
Page 10
CY7C185A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032
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