Datasheet CY7C1381C, CY7C1383C Datasheet (CYPRESS)

查询CY7C1381C-100AC供应商

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

CY7C1381C

CY7C1383C

Features

• Supports 133-MHz bus operations

• 512K X 36/1M X 18 common I/O

• 3.3V –5% and +10% core power supply (V

• 2.5V or 3.3V I/O supply (V

DDQ

)

• Fast clock-to-output times
— 6.5 ns (133-MHz version)

— 7.5 ns (117-MHz version)

— 8.5 ns (100-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP ,119-ball BGA

and 165-ball fBGA packages

• JTAG boundary scan for BGA and fBGA packages

• “ZZ” Sleep Mode option

DD

)



Functional Description

[1]

The CY7C1381C/CY7C1383C is a 3.3V, 512K x 36 and 1M x
18 Synchronous Flowthrough SRAMs, respectively designed
to interface with high-speed microprocessors with minimum
glue logic. Maximum access delay from clock rise is 6.5 ns
(133-MHz version). A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(

), depth-expansion Chip Enables (CE2 and

CE

1

Control inputs (

), and Global Write (GW). Asynchronous

and

BWE

include the Output Enable

ADSC

,

ADSP

,

and

ADV

(

)

and the ZZ pin

OE

), Write Enables

[2]

), Burst

CE

3

(

BW

inputs

.

The CY7C1381C/CY7C1383C allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP
cache Controller Address Strobe (ADSC

) inputs. Address

) or the

advancement is controlled by the Address Advancement
(ADV) input.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
Address Strobe Controller (

) are active. Subsequent

ADSC

ADSP

) or

burst addresses can be internally generated as controlled by
the Advance pin (

ADV

).

The CY7C1381C/CY7C1383C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

,

x

Selection Guide

133 MHz 117 MHz 100 MHz Unit

Maximum Access Time 6.5 7.5 8.5 ns

Maximum Operating Current 210 190 175 mA

Maximum CMOS Standby Current 70 70 70 mA

1

2

3

4

5

6

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05238 Rev. *B Revised February 26, 2004

are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

3, CE2

C

C

A
B

C

C

7

s

A
B
C
D

A

A

A
B

Logic Block Diagram – CY7C1381C (512K x 36)

CY7C1381

CY7C1383

D

,

DQP

DQ

BYTE

BYTE

C

,

DQP

DQ

BYTE

ADDRESS
REGISTER

DQ

B

,

DQP

BYTE

DQ

A

,

DQP

BYTE

ENABLE

REGISTER

B

A

,DQP

A

ADDRESS
REGISTER

COUNTER

AND LOGIC

CLR

D

C

B

A

BURST

A

[1:0]

Q1

Q0

ADV/LD

C

A1
A0

WRITE ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

A[1:0]

Q1

BURST

COUNTER AND

LOGIC

READ LOGIC

CLR

CONTROL

Q0

SLEEP

D1
D0

BURST
LOGIC

DQ

D

,

BYTE

WRITE REGISTER

C

DQ

BYTE

WRITE REGISTER

DQ

B

,

A1'

Q1

BYTE

A0'

WRITE REGISTER

Q0

DQ

A

,

BYTE

WRITE REGISTER

WRITE

DRIVERS

DQB,DQP

WRITE DRIVER

DQ

A

,DQP

WRITE DRIVER

DQP

,

DQP

DQP

DQP

D

C

MEMORY

B

A

ARRAY

SENSE
AMPS

OUTPUT
BUFFERS

O
U

INPUT

REGISTERS

DQ
DQP
DQP
DQP
DQP

T
P

D

MEMORY

ARRAY

S

E
N
S
E

A

M

P
S

U

A

T

T
A

B
U

S

F

T

F

E

E

E

R

R

S

I

N

E

DQs
DQP
DQP

G

INPUT

REGISTER

B

MEMORY

ARRAY

A

E

SENSE
AMPS

OUTPUT
BUFFERS

DQs
DQP
DQP

INPUT

REGISTERS

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

D

WRITE REGISTER

WRITE REGISTER

BW

C

A0, A1, A

BW

B

MODE

A

B

CE

SLEEP

CONTROL

LK

BW

A

EN

BWE

GW
CE1

CE2
CE3

OE

ZZ

8

Logic Block Diagram – CY7C1383C (1M x 18)

0,A1,A

C

ADV/LD

BW
BW

WE

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

ADDRESS
REGISTER

MODE

ADV

CLK

OE

ADSC

ADSP

BW

BW

B

A

BWE

GW

CE

1

CE

2

CE

3

OE

CE1
CE2
CE3

ZZ

DQB,DQP

WRITE REGISTER

DQ

WRITE REGISTER

ENABLE

REGISTER

ZZ

Document #: 38-05238 Rev. *B Page 2 of 36

SLEEP

CONTROL

C

C

Pin Configurations

1CE2

A

A

BWDBWCBWBBW

CE

A

CE3VDDV

SS

CLKGWBWEOEADSC

100-pin TQFP Pinout

A

A

ADSP

ADV

CY7C1381

CY7C1383

1CE2

A

A

CE

A

NCNCBWBBW

CE3VDDV

SS

CLKGWBWEOEADSC

A

A

ADSP

ADV

DQP
DQ
DQ

V

DDQ

V

SSQ

DQ
DQ
DQ
DQ

V

SSQ

V

DDQ

DQ
DQ

VSS/DNU

V

DD

NC

V

SS

DQ
DQ

V

DDQ

V

SSQ

DQ
DQ
DQ
DQ

V

SSQ

V

DDQ

DQ
DQ

DQP

100999897969594939291908988878685848382

C

1

C

2

C

3
4
5

C

6

C

7

C

8

C

9
10
11

C

12

C

13
14
15
16
17

D

18

D

19
20
21

D

22

D

23

D

24

D

25
26
27

D

28

D

29

D

30

CY7C1381C

(512K x 36)

31323334353637383940414243444546474849

MODE

AAA

1A0

A

A

NC

NC

SS

DD

V

V

A

A

AAAAA

81

DQP

80

DQ

79

DQ

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
DQP

B

B

B

B

B

B

B

B

A

A

A

A

A

A

A

A

B

A

NC
NC
NC

V

DDQ

V

SSQ

NC

NC
DQ
DQ

V

SSQ

V

DDQ

DQ
DQ

VSS/DNU

V

DD

NC

V

SS

DQ
DQ

V

DDQ

V

SSQ

DQ
DQ

DQP

NC

V

SSQ

V

DDQ

NC

NC

NC

B

B

B

B

B

B

B

B

B

50

A

A

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1383C

(1M x 18)

31323334353637383940414243444546474849

AAA

MODE

1A0

A

A

NC

NC

A

AAAAA

A

SS

DD

V

V

81

A

80

NC

79

NC

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

NC
DQP
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

A

A

A

A

A

A

A

A

A

50

A

A

Document #: 38-05238 Rev. *B Page 3 of 36

C

C

Pin Configurations (continued)

V

A

B

C

D

E

F

G
H

K

L

M

N

P

R

T
U

DQ

DQ

V

DQ
DQ

V

J

DQ

DQ

V

DQ

DQ

V

119-ball BGA (1 Chip Enable with JTAG)

CY7C1381C (512K x 36)

2345671

DDQ

NC

NC

DDQ

DDQ

DDQ

NC

NC

DDQ

AA AA

AA

AA

DQP

C

DQ

C

DQ

DQ

C

DQ

C

V

DD

DQ

D

DQ

D

DQ

DQ

D

DQP

D

A

V

C

C

C

C

C

V

V

BW

V

SS

SS

SS

SS

NC V

V

BW

V

V

V

SS

SS

SS

SS

D

D

D

D

D

MODE

AAA

ADSP

ADSC

V

DD

NC

CE

1

OE

ADV

C

GW

DD

CLK

D

NC

BWE

A1

A0

V

DD

V

V

V

BW

V

NC

V

BW

V

V

V

NC

TDOTCKTDITMS

CY7C1381

CY7C1383

V

DDQ

A

A

AA

SS

SS

SS

SS

SS

SS

SS

SS

DQP

DQ

B

DQ

B

DQ
DQ
V

DQ

DQ

DQ

DQ

B

B

DD

A

A

A

A

B

A

DQP

A

NCNC
NC

NC

NC

DQ

DQ

V

DQ
DQ

V

DQ

DQ

V

DQ

DQ

B

B

DDQ

B

B

DDQ

A

A

DDQ

A

A

B

A

NC

ZZ

V

DDQ

CY7C1383C (1M x 18)

2

V

A

B

C

D

E

F

G

H
J

K

L

M

N

P

R

T

U

V

DQ

V

DQ

V

DQ

V

DDQ

NC

NC

B

NC

DDQ

NC

B

DDQ

NC

B

DDQ

B

NC

NC

NC

DDQ

AA AA

AA

NCDQ

DQ

B

NC

DQ

B

NC

V

DD

DQ

B

NC

DQ

B

NC

DQP

B

A

345671

ADSP

V

V

V

V

V

NC

V

BW

V

V

V

NC

A

SS

SS

SS

SS

SS

SS

A

SS

SS

SS

AA

V

SS

V

SS

V

SS

BW

B

V

SS

NC V

V

SS

V

SS

V

SS

V

SS

V

SS

MODE

ADSC

V

DD

NC

CE

1

OE

ADV

GW

DD

CLK

NC

BWE

A1

A0

V

DD

ANCA

TDOTCKTDITMS

A
AA

DQP

NC

DQ

NC

DQ

V

DD

NC

DQ

NC

DQ

NC

A

AA

NC

V

DDQ

NC

NC

NC

A

DQ

A

V

DQ

V

DQ

V

DQ

DDQ

A

NC

DDQ

A

NC

DDQ

NC

A

A

A

A

A

NC

ZZ

V

DDQ

Document #: 38-05238 Rev. *B Page 4 of 36

C

C

Pin Configurations (continued)

234 5671

NC / 288M

A

B
C
D

G
H

K

M
N

R

NC

DQP

C

DQ

C

E
F

DQ

DQ

DQ

C

C

C

NC

J

L

P

DQ

DQ

DQ

DQ

DQP

NC

D

D

D

D

D

MODE

A

A

NC

DQ

C

DQ

C

DQ

C

DQ

C

V

SS

DQ

D

DQ

D

DQ

D

DQ

D

NC

NC / 72M

NC / 36M

V

V

V

V

V

V

V

V

V

V

CE

CE

DDQ

DDQ

DDQ

DDQ

DDQ

NC

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

CY7C1381

CY7C1383

165-ball fBGA (3 Chip Enable)

CY7C1381C (512K x 36)

891011

BW

1

BW

2

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

BW

C

D

BW

V

V

V

V

V
V
V

V

V

V

SS

SS

SS

SS

SS

SS

SS

SS

SS

SS

NC

TDI

TMS

CE

B

CLK

A

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

A0

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCK

ADSC

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

ADSP

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A

NC / 144M

A

NC DQP

DQ

DQ

DQ

DQ

DQ

B

DQ

B

DQ

B

DQ

B

NC

DQ

DQ

DQ

DQ

NC

DQ

A

DQ

A

DQ

A

DQ

A

DQP

A

NC

B

B

B

B

B

ZZ

A

A

A

A

A

A

AA

A

B
C
D

E
F

G

H

J
K
L

M

N
P

R

CY7C1383C (1M x 18)

234 5671

NC / 288M

NC

NC

NC

NC V

NC

NC

V

SS

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC

MODE

ACE

A

NC

DQ

B

DQ

B

DQ

B

DQ

B

V

SS

NC

NC

NC

NC

NC

NC / 72M

NC / 36M

CE

V

V

V

V

V

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

BW

1

2

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

A

CE

CLK

V

SS

V

SS

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

891011

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

ADSC

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

ADSP

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A

NC / 144M

A

NC DQP

NC

NC

NC

NC
NC

DQ

DQ

DQ

DQ

NC

DQ

DQ

DQ

DQ

ZZ

A

A

A

A

NCV

NC

NC

NC

NC

A

A

A

A

A

A

A

A

AA

Document #: 38-05238 Rev. *B Page 5 of 36

C

C

CY7C1381C–Pin Definitions

CY7C1381

CY7C1383

TQFP

(3-Chip

Name

, A1 , A 37,36,32,33,34,

A

0

Enable)

35,42,43,44,45,
46,47,48,49,50,

81,82,99,100

BGA

(1-Chip

Enable)

P4,N4,A2,B2,C2

,R2,A3,B3,C3,T

3,T4,A5,B5,C5,

T5,A6,B6,C6,R6

fBGA

(3-Chip

Enable) I/O Description

R6,P6,A2,A10,
B2,B10,N6,P3,

Input-

Synchronous
P4,P8,P9,P10,
P11,R3,R4,R8,

R9,R10,R11

BWA,BW

BWC,BW

GW

93,94,95,96 L5,G5,G3,L3 B5,A5,A4,B4 Input-

B

D

88

H4 B7 Input-

Synchronous

Synchronous

CLK 89 K4 B6 Input-

Clock

CE

CE

CE

OE

1

2

[2]

3

98 E4 A3 Input-

Synchronous

97 - B3 Input-

Synchronous

92 - A6 Input-

Synchronous

86 F4 B8 Input-

Asynchronous

Address Inputs used to select one of the
512K address locations. Sampled at the

rising edge of the CLK if ADSP
active LOW, and CE
sampled active. A

1, CE2

feed the 2-bit counter.

[1:0]

or ADSC is

, and CE

[2]

are

3

Byte Write Select Inputs, active LOW.
Qualified with BWE

to conduct byte writes to
the SRAM. Sampled on the rising edge of
CLK.

Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW

and BWE).

[A:D]

Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV

is

asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled
on the rising edge of CLK. Used in
conjunction with CE2 and CE
select/deselect the device. ADSP

is HIGH.

if CE

1

[2]

to

3

is ignored

Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE
select/deselect the device.

[2]

to

3

Chip Enable 3 Input, active LOW. Sampled
on the rising edge of CLK. Used

in
conjunction with CE1 and CE2 to
select/deselect the device.

Output Enable, asynchronous input,
active LOW. Controls the direction of the I/O

pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE
is masked during the first clock of a read
cycle when emerging from a deselected
state.

ADV

83 G4 A9 Input-

Synchronous

Advance Input signal, sampled on the
rising edge of CLK. When asserted, it

automatically increments the address in a
burst cycle.

ADSP

84 A4 B9 Input-

Synchronous

Address Strobe from Processor, sampled
on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented
to the device are captured in the address
registers. A
counter. When ADSP
asserted, only ADSP
ignored when

Document #: 38-05238 Rev. *B Page 6 of 36

are also loaded into the burst

[1:0]

and ADSC are both

is recognized. ASDP is

CE

is deasserted HIGH

1

C

C

CY7C1381C–Pin Definitions (continued)

CY7C1381

CY7C1383

TQFP

Name

ADSC

BWE

ZZ 64 T7 H11 Input-

DQ

s

(3-Chip

Enable)

85 B4 A8 Input-

87 M4 A7 Input-

52,53,56,57,58,
59,62,63,68,69,
72,73,74,75,78,

79,2,3,6,7,8,9,

12,13,18,19,22,

23,24,25,28,29

BGA

(1-Chip

Enable)

K6,L6,M6,N6,K7

,L7,N7,P7,E6,F
6,G6,H6,D7,E7,
G7,H7,D1,E1,G
1,H1,E2,F2,G2,

H2,K1,L1,N1,P1

,K2,L2,M2,N2

fBGA

(3-Chip

Enable) I/O Description

Synchronous

Synchronous

Asynchronous

M11,L11,K11,

J11,J10,K10,
L10,M10,D10,
E10,F10,G10,

D11,E11,F11,

G11,D1,E1,

F1,G1,D2,E2,

F2,G2,J1,K1,

L1,M1,J2,

K2,L2,M2,

I/O-

Synchronous

Address Strobe from Controller, sampled
on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented
to the device are captured in the address
registers. A
counter. When ADSP
asserted, only ADSP

Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.

ZZ “sleep” Input, active HIGH. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.

Bidirectional Data I/O lines. As inputs, they
feed into an on-chip data register that is
triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE
asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
in a tri-state condition.

automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE

are also loaded into the burst

[1:0]

and ADSC are both

is recognized

. When OE is

are placed

[A:D]

The outputs are

.

.

DQP

[A:D]

MODE 31 R3 R1 Input-Static Selects Burst Order. When tied to GND

V

DD

Document #: 38-05238 Rev. *B Page 7 of 36

51,80,1,30 P6,D6,D2,P2 N11,C11,C1,N1 I/O-

15,41,65,91 J2,C4,J4,R4,J6 D4,D8,E4,

E8,F4,F8,

G4,G8,H4,

H8,J4,J8,
K4,K8,L4,

L8,M4,M8

Synchronous

Power Supply Power supply inputs to the core of the

Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQs. During write sequences, DQP
controlled by BW

selects linear burst sequence. When tied to

or left floating selects interleaved burst

V

DD

sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.

device.

correspondingly.

[A:D]

[A:D]

is

C

C

CY7C1381C–Pin Definitions (continued)

CY7C1381

CY7C1383

TQFP

Name

V

DDQ

V

SS

V

SSQ

TDO - U5 P7 JTAG serial

(3-Chip

Enable)

4,11,20,27,

54,61,70,77

17,40,67,90 H2,D3,E3,F3,H3

5,10,21,26,
55,60,71,76

BGA

(1-Chip

Enable)

A1,F1,J1,M1,U1

,

A7,F7,J7,M7,U7

,K3,

M3,N3,

P3,D5,E5,F5,H5

,K5,

M5,N5,P5

- - I/O Ground Ground for the I/O circuitry.

fBGA

(3-Chip

Enable) I/O Description

C3,C9,D3,
D9,E3,E9,
F3,F9,G3,

G9,J3,J9,

K3,K9,L3,

L9,M3,M9,

N3,N9

C4,C5,C6,
C7,C8,D5,
D6,D7,E5,

E6,E7,F5,

F6,F7,G5,

G6,G7,H5,

H6,H7,J5,
J6,J7,K5,K6,K7,
L5,L6,L7,M5,M6

,M7,N4,N8

I/O Power

Supply

Ground Ground for the core of the device.

output

Synchronous

Power supply for the I/O circuitry.

Serial data-out to the JTAG circuit.

Delivers data on the negative edge of TCK.
If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.

TDI - U3 P5 JTAG serial

TMS - U2 R5 JTAG serial

TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the

NC 16,38,39,66 B1,C1,R1,T1,T2

V

/DNU 14 - - Ground/DNU This pin can be connected to Ground or

SS

,J3,D4,L4,J5,R5

,T6,U6,B7,C7,R

7

A1,A11,B1,

B11,C2,C10,H1,

H3,H9,

H10,N2,N5,N7,

N10,P1,P2,R2

input

Synchronous

input

Synchronous

- No Connects. Not internally connected to

Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be left
floating or connected to V
up resistor. This pin is not available on TQFP
packages.

Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be discon­nected or connected to V
available on TQFP packages.

JTAG feature is not being utilized, this pin
must be connected to V
available on TQFP packages.

the die. 18M, 36M, 72M, 144M and 288M are
address expansion pins are not internally
connected to the die.

should be left floating.

through a pull

DD

. This pin is not

DD

. This pin is not

SS

Document #: 38-05238 Rev. *B Page 8 of 36

C

C

CY7C1383C:Pin Definitions

CY7C1381

CY7C1383

TQFP

(3-Chip

Name

, A1 , A 37,36,32,33,34,

A

0

Enable)

35,42,43,44,45,
46,47,48,49,50,

80,81,82,99,100

BGA

(1-Chip

Enable)

P4,N4,A2,B2,
C2,R2,T2,A3,
B3,C3,T3,A5,
B5,C5,T5,A6,

B6,C6,R6,T6

fBGA

(3-Chip

Enable) I/O Description

R6,P6,A2,

A10,A11,B2,

Input-

Synchronous

B10,N6,P3,P4,

P8,P9,P10,
P11,R3,R4,

R8,R9,R10,R11

BW

GW

BWE

A,BWB

93,94 L5,G3 B5,A4 Input-

Synchronous

88 H4 B7 Input-

Synchronous

87 M4 A7 Input-

Synchronous

CLK 89 K4 B6 Input-

Clock

CE

CE

CE

OE

ADV

1

2

[2]

3

98 E4 A3 Input-

Synchronous

97 - B3 Input-

Synchronous

92 - A6 Input-

Synchronous

86 F4 B8 Input-

Asynchronous

83 G4 A9 Input-

Synchronous

Address Inputs used to select one of the
1M address locations. Sampled at the ris-

ing edge of the CLK if ADSP
active LOW, and CE
sampled active. A

1, CE2

feed the 2-bit counter.

[1:0]

or ADSC is

, and CE

[2]

are

3

Byte Write Select Inputs, active LOW.
Qualified with BWE

to conduct byte writes
to the SRAM. Sampled on the rising edge of
CLK.

Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW

and BWE).

[A:B]

Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.

Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV

is

asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE
select/deselect the device. ADSP

if CE

is HIGH.

1

[2]

to

3

is ignored

Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device.

and CE

1

[2]

to

3

Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK.

Used in
conjunction with CE1 and CE2 to
select/deselect the device.

Output Enable, asynchronous input,
active LOW. Controls the direction of the

I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE
is masked during the first clock of a read
cycle when emerging from a deselected
state.

Advance Input signal, sampled on the
rising edge of CLK. When asserted, it

automatically increments the address in a
burst cycle.

Document #: 38-05238 Rev. *B Page 9 of 36

C

C

CY7C1383C:Pin Definitions (continued)

CY7C1381

CY7C1383

TQFP

Name

ADSP

ADSC

ZZ 64 T7 H11 Input-

DQ

s

(3-Chip

Enable)

84 A4 B9 Input-

85 B4 A8 Input-

58,59,62,63,68,

69,72,73,8,9,12,

13,

18,19,22,23

BGA

(1-Chip

Enable)

P7,K7,G7,E7,F6

,H6,L6,N6,D1,H

1,L1,N1,E2,G2,

K2,M2

fBGA

(3-Chip

Enable) I/O Description

Synchronous

Synchronous

Asynchronous

J10,K10,

L10,M10,

D11,E11,

F11,G11,J1,K1,

L1,M1,

D2,E2,F2,

G2

I/O-

Synchronous

Address Strobe from Processor,
sampled on the rising edge of CLK,
active LOW. When asserted LOW,

addresses presented to the device are
captured in the address registers. A
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP

is recognized. ASDP is ignored when

is deasserted HIGH

CE

1

Address Strobe from Controller,
sampled on the rising edge of CLK,
active LOW. When asserted LOW,

addresses presented to the device are
captured in the address registers. A
also loaded into the burst counter. When

and ADSC

ADSP

is recognized

ADSP

ZZ “sleep” Input, active HIGH. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.

Bidirectional Data I/O lines. As inputs,
they feed into an on-chip data register that
is triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE
asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
in a tri-state condition.

automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE

are both asserted, only

.

. When OE is

[A:B]

The outputs are

.

are

[1:0]

are

[1:0]

are placed

DQP

[A:B]

MODE 31 R3 R1 Input-Static Selects Burst Order. When tied to GND

Document #: 38-05238 Rev. *B Page 10 of 36

74,24 D6,P2 C11,N1 I/O-

Synchronous

Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to

During write sequences, DQP

DQ

s.

controlled by BW

selects linear burst sequence. When tied to

or left floating selects interleaved burst

V

DD

sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.

correspondingly.

[A:B]

[A:B]

is

C

C

CY7C1383C:Pin Definitions (continued)

CY7C1381

CY7C1383

TQFP

Name

V

DD

V

DDQ

V

SS

V

SSQ

TDO - U5 P7 JTAG serial

TDI - U3 P5 JTAG serial

TMS - U2 R5 JTAG serial

TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the

(3-Chip

Enable)

15,41,65,91 C4,J2,J4,J6,R4 D4,D8,E4,

4,11,20,27,

54,61,70,77

17,40,67,90 D3,D5,E3,E5,F3

5,10,21,26,

55,60,71,76,

BGA

(1-Chip

Enable)

A1,A7,F1,F7,J1,

J7,M1,M7,U1,U

7

,F5,G5,H3,

H5,K3,K5,L3,M3

,

M5,N3,

N5,P3,P5

- - I/O Ground Ground for the I/O circuitry.

fBGA

(3-Chip

Enable) I/O Description

Power Supply Power supply inputs to the core of the

E8,F4,F8,

G4,G8,

H4,H8,J4,

J8,K4,K8,

L4,L8,M4,

M8

C3,C9,D3,
D9,E3,E9,
F3,F9,G3,

G9,J3,J9,
K3,K9,L3,

L9,M3,M9,

N3,N9

C4,C5,C6,
C7,C8,D5,
D6,D7,E5,

E6,E7,F5,
F6,F7,G5,

G6,G7,H1,

H2,H5,H6,

H7,J5,J6,J7,K5,

K6,K7,L5,L6,L7,

M5,

M6,M7,N4,

N8

I/O Power

Supply

Ground Ground for the core of the device.

output

Synchronous

input

Synchronous

input

Synchronous

device.

Power supply for the I/O circuitry.

Serial data-out to the JTAG circuit.

Delivers data on the negative edge of TCK.
If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.

Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be left floating or connected to V
through a pull up resistor. This pin is not
available on TQFP packages.

Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be disconnected or connected to V
This pin is not available on TQFP packages.

JTAG feature is not being utilized, this pin
must be connected to V
available on TQFP packages.

. This pin is not

SS

DD

DD

.

Document #: 38-05238 Rev. *B Page 11 of 36

C

C

CY7C1383C:Pin Definitions (continued)

CY7C1381

CY7C1383

TQFP

Name

NC 1,2,3,6,7,16,25,

V

/DNU 14 - - Ground/DNU This pin can be connected to Ground or

SS

(3-Chip

Enable)

28,29,30,38,39,
51,52,53,56,57,
66,75,78,79,95,

96

BGA

(1-Chip

Enable)

B1,B7,C1,C7,D
2,D4,D7,E1,E6,
H2,F2,G1,G6,H
7,J3,J5,K1,K6,L

4,L2,L7,M6,N2,

N7,L7,P1,P6,R1

,R5,R7,T1,T4,U

6

fBGA

(3-Chip

Enable) I/O Description

A1,A5,B1,

B4,B11,C1,C2,C

10,D1,D10,E1,E
10,F1,F10,G1,G
10,H3,H9,H10,J

2,J11,K2,K11,

L2,L11,M2,M11,

N2,N5,N7,N10,

N11,P1,P2,R2

- No Connects. Not internally connected to
the die. 36M, 72M, 144M and 288M are
address expansion pins are not internally
connected to the die.

should be left floating.

Document #: 38-05238 Rev. *B Page 12 of 36

CY7C1381

C

C

CY7C1383

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tC0) is 6.5 ns (133-MHz device).

The CY7C1381C/CY7C1383C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP

). Address advancement through the burst sequence is

(ADSC
controlled by the ADV

burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BWX) inputs. A Global Write

Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE

selection and output tri-state control. ADSP is ignored if
is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP

the access is initiated by ADSC
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.

If the OE
available at the data outputs a maximum to t

rise. ADSP

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are
satisfied at clock rise: (1)

active, and (2)
presented are loaded into the address register and the burst

inputs (
cycle. If the write inputs are asserted active ( see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise,the appropriate data will be latched and

written into the device.Byte writes are allowed.
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous

and the I/Os must be tri-stated prior to the presentation of data

) overrides all byte write inputs and writes data to

input is asserted LOW, the requested data will be

is ignored if CE1 is HIGH.

GW

, BWE, and BWX)are ignored during this first clock

) or the Controller Address Strobe

input. A two-bit on-chip wraparound

, CE2, CE

1

) provide for easy bank

, CE2, and CE

1

or ADSC is asserted LOW (if

, the write inputs must be

, CE2, CE

CE

ADSP is asserted LOW. The addresses

1

input signal must be deasserted

OE

[2]

3

[2]

) and an

3

CE

[2]

are all

3

after clock

CDV

are all asserted

All I/Os are

to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC

The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
written into the specified address location. Byte writes are
allowed. All I/Os are tri-stated when a write is detected, even
a byte write. Since this is a common I/O device, the
asynchronous OE
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless

input signal must be deasserted and the

, CE2, and CE

1

is ignored if ADSP is active LOW.

of the state of OE

[2]

are all asserted

3

.

Burst Sequences

The CY7C1381C/CY7C1383C provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter
is fed by A

1

burst order. The burst order is determined by the state of the
MODE input. A LOW on MODE will select a linear burst
sequence. A HIGH on MODE will select an interleaved burst
order. Leaving MODE unconnected will cause the device to
default to a interleaved burst sequence.

, and can follow either a linear or interleaved

[1:0]

Interleaved Burst Address Table
(MODE = Floating or VDD)

First

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Second

Address

A1: A0

Third

Address

A1: A0

Linear Burst Address Table
(MODE = GND)

First

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Second

Address

A1: A0

Third

Address

A1: A0

will be

[A:D]

Fourth

Address

A1: A0

Fourth

Address

A1: A0

Document #: 38-05238 Rev. *B Page 13 of 36

CY7C1381

C

C

CY7C1383

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering

“sleep” mode. CE

the
remain inactive for the duration of t

, CE2, CE

1

returns LOW.

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Snooze mode standby current ZZ > VDD – 0.2V 60 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
ZZ active to snooze current This parameter is sampled 2t
ZZ Inactive to exit snooze current This parameter is sampled 0 ns

[ 3, 4, 5, 6, 7]

[2]

, ADSP, and ADSC must

3

after the ZZ input

ZZREC

.

CYC

CYC

CYC

ns
ns
ns

Cycle Description

Deselected Cycle,

Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

None H X X L X L X X X L-H Tri-State

Power-down

ADDRESS

Deselected Cycle,

None L L X L L X X X X L-H Tri-State

Power-down

Deselected Cycle,

None L X H L L X X X X L-H Tri-State

Power-down

Deselected Cycle,

None L L X L H L X X X L-H Tri-State

Power-down

Deselected Cycle,

None X X X L H L X X X L-H Tri-State

Power-down

Snooze Mode, Pow-

None X X X H X X X X X X Tri-State

er-down

Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

Notes:

3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.

4. WRITE

5. The DQ pins are controlled by the current cycle and the

6. The SRAM always initiates a read cycle when ADSP

7.

9

= L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..

after the
don't care for the remainder of the write cycle.

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE

OE
is

inactive or when the device is deselected, and all data bits behave as output when

or with the assertion of

ADSP

. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a

ADSC

signal. OE is asynchronous and is not sampled with the clock.

OE

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks

is active (LOW).

OE

Document #: 38-05238 Rev. *B Page 14 of 36

CY7C1381

C

C

CY7C1383

Truth Table

[ 3, 4, 5, 6, 7]

ADDRESS

Cycle Description

Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

Write Cycle, Continue Burst Next X X X L H H L L X L-H D

Write Cycle, Continue Burst Next H X X L X H L L X L-H D

Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State

Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q

Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State

Write Cycle, Suspend Burst Current X X X L H H H L X L-H D

Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

Partial Truth Table for Read/Write

Function (CY7C1381C)

[3, 8]

GW

BWE

BW

D

BW

C

BW

B

BW

A

Read H H X X X X

Read HLHHHH

Write Byte A (DQ

, DQPA)HLHHHL

A

Write Byte B(DQB, DQPB)HLHHLH

Write Bytes A, B (DQ

Write Byte C (DQ

Write Bytes C, A (DQC, DQ

Write Bytes C, B (DQ

Write Bytes C, B, A (DQ
DQP

, DQPA)

B

Write Byte D (DQ

Write Bytes D, A (DQD, DQ

Write Bytes D, B (DQ

Write Bytes D, B, A (DQ
DQP

, DQPA)

B

Write Bytes D, B (DQ

Write Bytes D, B, A (DQ

, DQPA)

DQP

C

Write Bytes D, C, A ( DQ

, DQPA)

DQP

B

, DQB, DQPA, DQPB)H L H H L L

A

, DQPC) HLHLHH

C

DQPC, DQPA)HLHLHL

A,

, DQ

C

, DQPD)HLLHHH

D

D

D

DQPC, DQPB)H L H L L H

B,

, DQB, DQ

C

DQPD, DQPA)H L L H H L

A,

, DQ

DQPD, DQPA)H L L H L H

A,

, DQB, DQ

D

, DQ

DQPD, DQPB)H L L L H H

B,

, DQC, DQ

D

, DQB, DQA, DQPD,

D

DQPC,

A,

DQPD,

A,

DQPD,

A,

HLHLLL

HLLHLL

HLLLHL

HLLLLH

Write All Bytes HLLLLL

Write All Bytes L X X X X X

Note:

8. Table only lists a partial listing of the byte write combinations. Any Combination of BW

Truth Table for Read/Write

Function (CY7C1383C)

[3]

GW

is valid Appropriate write will be done based on which byte write is active.

X

BWE

BW

B

BW

A

Read H H X X

Read H L H H

Write Byte A - ( DQ

Write Byte B - ( DQ

and DQPA)HLHL

A

and DQPB)HLLH

B

Write All Bytes H L L L

Document #: 38-05238 Rev. *B Page 15 of 36

CY7C1381

C

C

CY7C1383

Truth Table for Read/Write

Function (CY7C1383C)

Write All Bytes L X X X

[3]

GW

BWE

BW

B

BW

A

Document #: 38-05238 Rev. *B Page 16 of 36

CY7C1381

C

C

T

O

CY7C1383

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1381C/CY7C1383C incorporates a serial boundary
scan test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of
the SRAM. Note that the TAP controller functions in a manner
that does not conflict with the operation of other devices using

1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1381C/CY7C1383C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V

SS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may alter­nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

0

RUN-TEST/

IDLE

1

SELECT

DR-SCAN

1 1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

1

0

0

0 0

1

1 1

0 0

0

1

1

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

1

SELECT

The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

1

0

0

1

0

1

1

0

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif­icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

0

Bypass Register

012

TDI TD

TCK

MS TAP CONTROLLER

Selection

Circuitry

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.

At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.

Instruction Register

012293031 ...

Identification Register

012..x ...

Boundary Scan Register

S

election

Circuitr

y

Document #: 38-05238 Rev. *B Page 17 of 36

CY7C1381

C

C

CY7C1383

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

SS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
70-bit-long register and the x18 configuration has a 51-bit long
register.

The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.

The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.

When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (t

The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still

plus tCH).

CS

Document #: 38-05238 Rev. *B Page 18 of 36

CY7C1381

C

C

123456

T

CY7C1383

possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.

Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.

TAP Timing

Test Clock

(TCK)

t

est Mode Select

(TMS)

t

Test Data-In

(TDI)

Test Data-Out

(TDO)

TMSS

TDIS

t

t

TMSH

t

TDIH

TH

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

t

TL

t

CYC

t

TDOX

t

TDOV

DON’T CARE UNDEFINED

TAP AC Switching Characteristics Over the operating Range

[9, 10]

Parameter Symbol Min Max Units

Clock

TCK Clock Cycle Time t
TCK Clock Frequency t
TCK Clock HIGH time t
TCK Clock LOW time t

TCYC

TF

TH

TL

100 ns

10 MHz
40 ns
40 ns

Output Times

TCK Clock LOW to TDO Valid t
TCK Clock LOW to TDO Invalid t

TDOV

TDOX

0ns

20 ns

Setup Times

TMS Set-Up to TCK Clock Rise t
TDI Set-Up to TCK Clock Rise t
Capture Set-Up to TCK Rise t

TMSS

TDIS

CS

10 ns
10 ns
10

Hold Times

TMS hold after TCK Clock Rise t

TMSH

TDI Hold after Clock Rise t
Capture Hold after Clock Rise t

Notes:

t

CS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

9.

10. Test conditions are specified using the load in TAP AC test Conditions. t

R/tF

= 1ns

TDIH

CH

10 ns
10 ns
10 ns

Document #: 38-05238 Rev. *B Page 19 of 36

CY7C1381

C

C

T

F

T

F

CY7C1383

3.3V TAP AC Test Conditions

Input pulse levels ........ ........................................VSS to 3.3V

Input rise and fall times...................... ..............................1ns

Input timing reference levels ...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage ...............................1.5V

3.3V TAP AC Output Load Equivalent

1.5V

50Ω

DO

Z = 50Ω

O

20p

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)

2.5V TAP AC Test Conditions

Input pulse levels....... ........................................VSS to 2.5V

Input rise and fall time ......................................................1ns

Input timing reference levels................... ......................1.25V

Output reference levels .................. ..............................1.25V

Test load termination supply voltage .................... ........1.25V

2.5V TAP AC Output Load Equivalent

1.25V

50Ω

DO

[11]

Z = 50Ω

O

20p

PARAMETER DESCRIPTION DESCRIPTION CONDITIONS MIN MAX UNITS

V

V

V

V

V

V

V

I

OH1

OH2

OL1

OL2

IH

IL

X

Output HIGH Voltage IOH = -4.0 mA

= -1.0 mA

I

OH

Output HIGH Voltage IOH = -100 µA

Output LOW Voltage IOL = 8.0 mA

= 8.0 mA

I

OL

Output LOW Voltage IOL = 100 µA

Input HIGH Voltage

Input LOW Voltage

Input Load Current GND < VIN < V

DDQ

= 3.3V 2.4 V

DDQ

V

= 2.5V 2.0 V

DDQ

V

= 3.3V 2.9 V

DDQ

V

= 2.5V 2.1 V

DDQ

V

= 3.3V 0.4 V

DDQ

V

= 2.5V 0.4 V

DDQ

V

= 3.3V 0.2 V

DDQ

V

= 2.5V 0.2 V

DDQ

V

= 3.3V 2.0 VDD + 0.3 V

DDQ

V

= 2.5V 1.7 VDD + 0.3 V

DDQ

V

= 3.3V -0.3 0.8 V

DDQ

V

= 2.5V -0.3 0.7 V

DDQ

-5 5 µA

Note:

11.All voltages referenced to V

Document #: 38-05238 Rev. *B Page 20 of 36

SS (GND).

C

C

Identification Register Definitions

CY7C1381

CY7C1383

INSTRUCTION FIELD

Revision Number (31:29)

Device Depth (28:24)

Device Width (23:18)

Cypress Device ID (17:12)

Cypress JEDEC ID Code (11:1)

ID Register Presence Indicator (0)

CY7C1381C

(512KX36)

010 010

01010 01010

000001 000001

100101 010101

00000110100 00000110100

11

CY7C1383C

(1MX18)

DESCRIPTION

Describes the version number.

Reserved for Internal Use

Defines memory type and architecture

Defines width and density

Allows unique identification of SRAM vendor.

Indicates the presence of an ID register.

Scan Register Sizes

REGISTER NAME BIT SIZE(X36) BIT SIZE(X18)

Instruction

Bypass

ID

Boundary Scan Order

33

11

32 32

72 72

Identification Codes

INSTRUCTION CODE DESCRIPTION

EXTEST

IDCODE

SAMPLE Z

RESERVED

SAMPLE/PRELOAD

RESERVED

RESERVED

BYPASS

000

001

010

011

100

101

110

111

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.

Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.

Do Not Use: This instruction is reserved for future use.

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.

Do Not Use: This instruction is reserved for future use.

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.

Document #: 38-05238 Rev. *B Page 21 of 36

C

C

119-Ball BGA Boundary Scan Order

CY7C1381C (512K x 36)

CY7C1381

CY7C1383

BIT

#

1

2

3M439 N4

4F440 R6

5B441 T5

6A442 T3

7G443 R2

8C644 R3

9A645 P2

10 D6 46 P1

11 D7 4 7 N 2

12 E6 48 L2

13 G6 49 K1

14 H7 50 N1

15 E7 51 M2

16 F6 52 L1

17 G7 53 K2

18 H6 54 Not Bonded (Preset to 0)

19 T7 55 H1

20 K7 56 G2

21 L6 57 E2

22 N6 58 D1

23 P7 59 H2

24 K6 60 G1

25 L7 61 F2

26 M6 62 E1

27 N7 63 D2

28 P6 64 A5

29 B5 65 A3

30 B3 66 E4

31 C5 67 Internal

32 C3 68 L3

33 C2 69 G3

34 A2 70 G5

35 T4 71 L5

36 B6 72 Internal

BALL ID BIT

#

K4

H4

37 B2

38 P4

BALL ID

Document #: 38-05238 Rev. *B Page 22 of 36

C

C

119-Ball BGA Boundary Scan Order

CY7C1383C (1M x 18)

CY7C1381

CY7C1383

BIT

#

1

2

3M439 N4

4F440 R6

5B441 T5

6A442 T3

7G443 R2

8C644 R3

9 A6 45 Not Bonded (Preset to 0)

10 T6 46 Not Bonded (Preset to 0)

11 Not Bonded (Preset to 0) 47 Not Bonded (Preset to 0)

12 Not Bonded (Preset to 0) 48 Not Bonded (Preset to 0)

13 Not Bonded (Preset to 0) 49 P2

14 D6 50 N1

15 E7 51 M2

16 F6 52 L1

17 G7 53 K2

18 H6 54 Internal

19 T7 55 H1

20 K7 56 G2

21 L6 57 E2

22 N6 58 D1

23 P7 59 Not Bonded (Preset to 0)

24 Not Bonded (Preset to 0) 60 Not Bonded (Preset to 0)

25 Not Bonded (Preset to 0) 61 Not Bonded (Preset to 0)

26 Not Bonded (Preset to 0) 62 Not Bonded (Preset to 0)

27 Not Bonded (Preset to 0) 63 Not Bonded (Preset to 0)

28 Not Bonded (Preset to 0) 64 A5

29 B5 65 A3

30 B3 66 E4

31 C5 67 Internal

32 C3 68 Not Bonded (Preset to 0)

33 C2 69 Internal

34 A2 70 G3

35 T2 71 L5

36 B6 72 Internal

BALL ID BIT

#

K4

H4

37 B2

38 P4

BALL ID

Document #: 38-05238 Rev. *B Page 23 of 36

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C

165-Ball fBGA Boundary Scan Order

CY7C1381C (512K x 36)

BIT# BALL ID BIT# BALL ID

1B637N6

2B738R6

3A739P6

4B840R4

5A841R3

6B942P4

7A943P3

8B1044R1

9A1045N1

10 C11 46 L2

11 E 1 0 47 K2

12 F10 48 J2

13 G10 49 M2

14 D10 50 M1

15 D11 51 L1

16 E11 52 K1

17 F11 53 J1

18 G11 54 Not Bonded (Preset to 0)

19 H11 55 G2

20 J10 56 F2

21 K10 57 E2

22 L10 58 D2

23 M10 59 G1

24 J11 60 F1

25 K11 61 E1

26 L11 62 D1

27 M11 63 C1

28 N11 64 A2

29 R11 65 B2

30 R10 66 A3

31 R9 67 B3

32 R8 68 B4

33 P10 69 A4

34 P9 70 A5

35 P8 71 B5

36 P11 72 A6

CY7C1381

CY7C1383

Document #: 38-05238 Rev. *B Page 24 of 36

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C

165-Ball fBGA Boundary Scan Order

CY7C1383C (1M x 18)

BIT# BALL ID BIT# BALL ID

1B637N6

2B738R6

3A739P6

4B840R4

5A841R3

6B942P4

7A943P3

8B1044R1

9 A10 45 Not Bonded (Preset to 0)

10 A11 46 Not Bonded (Preset to 0)

11 Not Bonded (Preset to 0) 47 Not Bonded (Preset to 0)

12 Not Bonded (Preset to 0) 48 Not Bonded (Preset to 0)

13 Not Bonded (Preset to 0) 49 N1

14 C11 50 M1

15 D11 51 L1

16 E11 52 K1

17 F11 53 J1

18 G11 54 Not Bonded (Preset to 0)

19 H11 55 G2

20 J10 56 F2

21 K10 57 E2

22 L10 58 D2

23 M10 59 Not Bonded (Preset to 0)

24 Not Bonded (Preset to 0) 60 Not Bonded (Preset to 0)

25 Not Bonded (Preset to 0) 61 Not Bonded (Preset to 0)

26 Not Bonded (Preset to 0) 62 Not Bonded (Preset to 0)

27 Not Bonded (Preset to 0) 63 Not Bonded (Preset to 0)

28 Not Bonded (Preset to 0) 64 A2

29 R11 65 B2

30 R10 66 A3

31 R9 67 B3

32 R8 68 Not Bonded (Preset to 0)

33 P10 69 Not Bonded (Preset to 0)

34 P9 70 A4

35 P8 71 B5

36 P11 72 A6

CY7C1381

CY7C1383

Document #: 38-05238 Rev. *B Page 25 of 36

CY7C1381

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C

CY7C1383

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

Relative to GND........ –0.3V to +4.6V

DD

DC Voltage Applied to Outputs

in Tri-State........................................... –0.5V to V

DC Input Voltage....................................–0.5V to V

DDQ

DD

+ 0.5V

+ 0.5V

Electrical Characteristics Over the Operating Range

Operating Range

Range

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
Industrial -40°C to +85°C

[12, 13]

Ambient

Temperature V

DD

V

DDQ

to V

DD

Parameter Description Test Conditions Min. Max. Unit

V
V

V

V

V

V

I

I

I

I

DD

DDQ

OH

OL

IH

IL

X

OZ

OS

DD

Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage V

Output HIGH Voltage V

Output LOW Voltage V

Input HIGH Voltage

Input LOW Voltage

[12]

[12]

Input Load GND ≤ VI ≤ V

Input Current of MODE Input = V

Input Current of ZZ Input = V

Output Leakage Current GND ≤ VI ≤ V

Output Short Circuit
Current

VDD Operating Supply
Current

= 3.3V 3.135 V

DDQ

V

= 2.5V 2.375 2.625 V

DDQ

= 3.3V, VDD = Min., I

DDQ

V

= 2.5V, VDD = Min., I

DDQ

= 3.3V, VDD = Min., I

DDQ

= 2.5V, VDD = Min., I

V

DDQ

V

= 3.3V 2.0 VDD + 0.3V V

DDQ

= 2.5V 1.7 VDD + 0.3V V

V

DDQ

V

= 3.3V –0.3 0.8 V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

DDQ

SS

Input = V

Input = V

V

DD

V

DD

f = f

DD

SS

DD

= Max., V

= Max., I

= 1/t

MAX

Output Disabled –5 5 µA

DD,

= GND -300 µA

OUT

= 0 mA,

OUT

CYC

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

–5 5 µA

–30 µA

30 µA

–30 µA

30 µA

7.5-ns cycle, 133 MHz 210 mA

8.8-ns cycle, 117 MHz 190 mA

DD

10-ns cycle, 100 MHz 175 mA

I

SB1

Automatic CE
Power-down
Current—TTL Inputs

Max. VDD, Device Deselected,
V

≥ VIH or VIN ≤ VIL, f = f

IN

inputs switching

MAX,

7.5-ns cycle, 133 MHz 120 mA

8.8-ns cycle, 117 MHz 11 0 mA

10-ns cycle, 100 MHz 100

I

SB2

I

SB3

I

SB4

Notes:

12. Overshoot: V

13. T

Power-up

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—TTL Inputs

(AC) < VDD +1.5V (Pulse width less than t

IH

: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and V

Max. VDD, Device Deselected,
V

≥ VDD – 0.3V or VIN ≤ 0.3V,

IN

f = 0, inputs static

Max. VDD, Device Deselected,
V

IN

f = f

≥ V

– 0.3V or VIN ≤ 0.3V,

DDQ

, inputs switching

MAX

Max. VDD, Device Deselected,
V

≥ V

IN

f = 0, inputs static

– 0.3V or VIN ≤ 0.3V,

DD

/2), undershoot: VIL(AC) > -2V (Pulse width less than t

CYC

All speeds 70 mA

7.5-ns cycle, 133 MHz 105 mA

8.8-ns cycle, 117 MHz 100 mA

10-ns cycle, 100 MHz 95 mA

All Speeds 80 mA

DDQ

< V

DD

CYC

/2).

V

Document #: 38-05238 Rev. *B Page 26 of 36

CY7C1381

C

C

CY7C1383

Thermal Resistance

[14]

Parameter Description Test Conditions

Θ

JA

Θ

JC

Capacitance

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

[14]

Test conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA / JESD51.

Parameter Description Test Conditions

CIN Input Capacitance TA = 25°C, f = 1 MHz,

= 3.3V.

V

C

CLK

C

I/O

Notes:

14. Tested initially and after any design or process change that may affect these parameters

Clock Input Capacitance 5 8 9 pF

Input/Output Capacitance 5 8 9 pF

V

DD
DDQ

= 2.5V

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

Z

2.5V I/O Test Load

= 50Ω

0

VL= 1.5V

(a)

R

= 50Ω

L

3.3V

OUTPUT

5pF

INCLUDING

JIG AND

SCOPE

R = 317Ω

R = 351Ω

(b)

TQFP

Package

BGA

Package

fBGA

Package Unit

31 45 46 °C/W

6 7 3 °C/W

TQFP

Package

BGA

Package

fBGA

Package Unit

5 8 9 pF

V

GND

DD

≤ 1ns

ALL INPUT PULSES

10%

90%

90%

(c)

10%

≤ 1ns

OUTPUT

Z

= 50Ω

0

V

(a)

L

R

= 1.25V

L

2.5V

OUTPUT

= 50Ω

5pF

INCLUDING

JIG AND

SCOPE

Document #: 38-05238 Rev. *B Page 27 of 36

R = 1667Ω

R =1538Ω

(b)

V

GND

DD

≤ 1ns

ALL INPUT PULSES

10%

90%

90%

10%

≤ 1ns

(c)

CY7C1381

C

C

CY7C1383

Switching Characteristics Over the Operating Range

[19, 20]

133 MHz 117 MHz 100 MHz

Parameter Description

t

POWER

VDD(Typical) to the first Access

[15]

1 11ms

Clock

t

CYC

t

CH

t

CL

Clock Cycle Time 7.5 8.5 10 ns

Clock HIGH 2.1 2.3 2.5 ns

Clock LOW 2.1 2.3 2.5 ns

Output Times

t

CDV

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Data Output Valid After CLK Rise 6.5 7.5 8.5 ns

Data Output Hold After CLK Rise 2.0 2.0 2.0 ns

Clock to Low-Z

Clock to High-Z

OE

LOW to Output Val id

OE LOW to Output Low-Z

OE HIGH to Output High-Z

[16, 17, 18]

[16, 17, 18]

[16, 17, 18]

[16, 17, 18]

2.0 2.0 2.0 ns

0 4.0 0 4.0 0 5.0 ns

3.2 3.4 3.8 ns

0 0 0 ns

4.0 4.0 5.0 ns

Setup Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Address Set-up Before CLK Rise 1.5 1.5 1.5 ns

ADSP, ADSC Set-up Before CLK Rise

ADV Set-up Before CLK Rise

GW, BWE, BW
Rise

Set-up Before CLK

[A:D]

1.5 1.5 1.5 ns

1.5 1.5 1.5 ns

1.5 1.5 1.5 ns

Data Input Set-up Before CLK Rise 1.5 1.5 1.5 ns

Chip Enable Set-up 1.5 1.5 1.5 ns

Hold Times

t

AH

t

ADH

t

WEH

t

ADVH

t

DH

t

CEH

Notes:

15. This part has a voltage regulator internally; t
can be initiated.

, t

16. t

CHZ

CLZ,tOELZ

17. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions

18. This parameter is sampled and not 100% tested.

19. Timing reference level is 1.5V when V

20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Address Hold After CLK Rise 0.5 0.5 0.5 ns

ADSP, ADSC Hold After CLK Rise

GW

,

BWE, BW

Hold After CLK Rise

[A:D]

ADV Hold After CLK Rise

0.5 0.5 0.5 ns

0.5 0.5 0.5 ns

0.5 0.5 0.5 ns

Data Input Hold After CLK Rise 0.5 0.5 0.5 ns

Chip Enable Hold After CLK Rise 0.5 0.5 0.5 ns

is the time that the power needs to be supplied above VDD( minimum) initially, before a read or write operation

POWER

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

is less than t

OEHZ

= 3.3V and is 1.25V when V

DDQ

OELZ

and t

is less than t

CHZ

DDQ

= 2.5V.

to eliminate bus contention between SRAMs when sharing the same

CLZ

UnitMin. Max. Min. Max. Min. Max.

Document #: 38-05238 Rev. *B Page 28 of 36

C

C

Timing Diagrams

G

Read Cycle Timing

[21]

t

CYC

CY7C1381

CY7C1383

CLK

ADSP

ADSC

ADDRESS

W, BWE,BW

X

CE

ADV

t

ADS

t

t

AS

CES

A1

t

CH

t

ADH

t

AH

t

CEH

t

t

CL

WES

t

WEH

t

ADS

A2

t

ADH

t

ADVS

t

ADVH

Deselect Cycle

ADV suspends burst

OE

Data Out (Q)

High-Z

t

OEV

t

CLZ

t

CDV

Single READ

t

OEHZ

Q(A1)

t

OELZ

t

DOH

Q(A2)

t

CDV

Q(A2 + 1)

Q(A2 + 2)

BURST

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Burst wraps around
to its initial state

t

CHZ

Q(A2 + 2)

READ

DON’T CARE

UNDEFINED

Document #: 38-05238 Rev. *B Page 29 of 36

CY7C1381

C

C

D

CY7C1383

Timing Diagrams (continued)

10

Write Cycle Timing

CLK

[21, 22]

t

ADS

t

ADH

t

CYC

t

t

CL

CH

ADSP

t

t

ADH

ADS

ADSC

t

t

AH

AS

ADDRESS

A1

Byte write signals are ignored for first cycle when
ADSP initiates burst

BWE,

BW

X

GW

t

t

CEH

CES

CE

ADSC extends burst

t

ADS

A2 A3

t

t

WEH

WES

t

ADH

t

WES

t

ADVS

t

WEH

t

ADVH

ADV

OE

Data in (D)

ata Out (Q)

t

t

DH

DS

High-Z

BURST READ BURST WRITE

t

OEHZ

D(A1)

Single WRITE

D(A2)

D(A2 + 1)

D(A2 + 1)

DON’T CARE UNDEFINED

ADV suspends burst

D(A2 + 2)

D(A2 + 3)

D(A3 + 1)

D(A3)

Extended BURST WRITE

D(A3 + 2)

Document #: 38-05238 Rev. *B Page 30 of 36

C

C

Timing Diagrams (continued)

t

D

Read/Write Cycle Timing

[21, 23, 24]

CYC

CY7C1381

CY7C1383

CLK

ADSP

ADSC

ADDRESS

BWE, BW

CE

ADV

OE

Data In (D)

ata Out (Q)

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

High-Z

t

CES

Q(A1)

A2

t

CEH

Q(A2)

A1 A5 A6

X

Back-to-Back READs

A3 A4

t

OEHZ

Single WRITE

t

WES

t

DS

D(A3)

t

t

WEH

DH

t

OELZ

t

CDV

Q(A4) Q(A4+1)

BURST READ

Q(A4+2)

D(A5) D(A6)

Q(A4+3)

DON’T CARE UNDEFINED

Back-to-Back

WRITEs

Note:

21. On this diagram, when CE

22.

Full width write can be initiated by either GW

23.

The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by

24.

is HIGH.

GW

25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

26. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05238 Rev. *B Page 31 of 36

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

LOW; or by GW HIGH, BWE LOW and BWX LOW.

ADSP

or ADSC

.

C

C

Timing Diagrams (continued)

Z

[25, 26]

A

Z Mode Timing

CLK

CY7C1381

CY7C1383

t

ZZ

t

ZZREC

ZZ

I

SUPPLY

LL INPUTS

(except ZZ)

Outputs (Q)

t

ZZI

I

DDZZ

High-Z

DON’T CARE

t

RZZI

DESELECT or READ Only

Ordering Information

Speed

(MHz) Ordering Code

133 CY7C1381C-133AC

CY7C1383C-133AC

CY7C1381C-133BGC
CY7C1383C-133BGC

CY7C1381C-133BZC
CY7C1383C-133BZC

117 CY7C1381C-117AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

CY7C1383C-117AC

CY7C1381C-117BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and

CY7C1383C-117BGC

CY7C1381C-117BZC
CY7C1383C-117BZC

CY7C1381C-117AI
CY7C1383C-117AI

CY7C1381C-117BGI
CY7C1383C-117BGI

CY7C1381C-117BZI
CY7C1383C-117BZI

Package

Name Part and Package Type

A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and

JTAG

BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)

3 Chip Enables and JTAG

3 Chip Enables

JTAG

BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)

3 Chip Enables and JTAG

A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and

JTAG

BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)

3 Chip Enables and JTAG

Operating

Range

Commercial

Commercial

Industrial

Document #: 38-05238 Rev. *B Page 32 of 36

Ordering Information

Speed

(MHz) Ordering Code

100 CY7C1381C-100AC

CY7C1383C-100AC

CY7C1381C-100BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and

CY7C1383C-100BGC

CY7C1381C-100BZC BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)

CY7C1383C-100BZC

CY7C1381C-100AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

CY7C1383C-100AI

CY7C1381C-100BGI BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and

CY7C1383C-100BGI

CY7C1381C-100BZI BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)

CY7C1383C-100BZI

Shaded areas contain advance information.
Please contact your local sales representative for availability of these parts.

Package

Name Part and Package Type

A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

JTAG

3 Chip Enables and JTAG

3 Chip Enables

JTAG

3 Chip Enables and JTAG

Package Diagrams

CY7C1381C

CY7C1383C

Operating

Range

Commercial

Industrial

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

DIMENSIONS ARE IN MILLIMETERS.

SEATING PLANE

20.00±0.10

22.00±0.20

16.00±0.20

14.00±0.10

100

1

30

31 50

0° MIN.

R0.08MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

81

80

0.30±0.08

0.65
TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

12°±1°

(8X)

1.40±0.05

0.20 MAX.

1.60 MAX.

0.10

SEE DETAIL

A

51-85050-*A

Document #: 38-05238 Rev. *B Page 33 of 36

© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconducto r does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

C

C

Package Diagrams (continued)

CY7C1381

CY7C1383

51-85115-*B

Document #: 38-05238 Rev. *B Page 34 of 36

C

C

Package Diagrams (continued)

CY7C1381

CY7C1383

165-Ball FBGA (13 x 15 x 1.2 mm) BB165A

51-85122-*C

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05238 Rev. *B Page 35 of 36

CY7C1381

C

C

CY7C1383

Document History Page

Document Title: CY7C1381C/CY7C1383C 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
Document Number: 38-05238

REV. ECN NO. Issue Date

** 116278 08/27/02 SKX New Data Sheet

*A 121541 11/21/02 DSG Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122

*B 206081 See ECN RKF Final Datasheet

Orig. of
Change Description of Change

(BB165A) to rev. *C

Document #: 38-05238 Rev. *B Page 36 of 36