Datasheet CY7C1370CV25, CY7C1372CV25 Datasheet (CIRRUS LOGIC)

a b c d

C

查询CY7C1370CV25-167AC供应商

512K x 36/1M x 18 Pipelined SRAM

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 225, 200 and 167

MHz

• Internally self-timed output buffer control to eliminate the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined operation

• Byte Write capability

• Single 2.5V power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

• Clock Enable (CEN

• Synchronous self-timed writes

• Available in 100 TQFP, 119 BGA, and 165 fBGA packages

• IEEE 1149.1 JTAG Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

) pin to suspend operation

CY7C1370CV25

CY7C1372CV25

with NoBL™ Architecture

Functional Description

The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370CV25 and CY7C1372CV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370CV25 and CY7C1372CV25 are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects (BW

–BWd for CY7C1370CV25 and BWa–BWb for

a

CY7C1372CV25) and a Write Enable (WE

) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE asynchronous Output Enable (OE

, CE2, CE3) and an

1

) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

) signal,

Logic Block Diagram–CY7C1370CV25 (512K x 36)

A0, A1, A

MODE

CLK

C

EN

ADV/LD

BW

a

BW

b

BW

c

BW

d

WE

OE CE1 CE2 CE3

ZZ

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05235 Rev. *C Revised June 03, 2004

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

ADV/LD

C

WRITE ADDRESS

REGISTER 2

A1

D1D0Q1

A0

BURST LOGIC

A1' A0'

Q0

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER 1

O

S

U T

E

P

N

U T

S E

R E G

A

I

M

S T

P

E

S

R S

E

REGISTER 0

INPUT

O

D

U T

A

P

T

U

A

T B

S T E E R

I N G

E

DQs

U

DQP

F

DQP

F

DQP

E

DQP

R S

E

a b

C

Logic Block Diagram-CY7C1372CV25 (1M x 18)

A0, A1, A

MODE

CLK

C

EN

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

ADV/LD

C

WRITE ADDRESS

REGISTER 2

A1

D1D0Q1

A0

BURST LOGIC

Q0

CY7C1370CV25

CY7C1372CV25

A1' A0'

O U

T P

S

U

INPUT

E

T

N S

R

E

G

A

I

M

S

P

T

S

E

R

S

E

REGISTER 0

ADV/LD

BW

a

BW

b

WE

OE CE1 CE2 CE3

ZZ

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

Sleep

Control

WRITE

DRIVERS

MEMORY

ARRAY

REGISTER 1

INPUT

O U

T P

D

U

A

T

T A

B U

S

F

T

F

E

R

S

I N G

E

Selection Guide

CY7C1370CV25-250 CY7C1372CV25-250

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby

2.6 2.8 3.0 3.4 ns

350 325 300 275 mA

70 70 70 70 mA

Current

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

CY7C1370CV25-225 CY7C1372CV25-225

CY7C1370CV25-200 CY7C1372CV25-200

DQs DQP DQP

E

CY7C1370CV25-167 CY7C1372CV25-167 Unit

Document #: 38-05235 Rev. *C Page 2 of 27

Pin Configurations

a

100-pin TQFP Packages

CY7C1370CV25

CY7C1372CV25

DQPc

DQc DQc

V

DDQ

V

SS

DQc DQc

V

SS

V

DDQ

DQc

NC

V

DD

NC V

SS

DQd DQd

V

DDQ

V

SS

DQd DQd DQd

DQd

V

SS

V

DDQ

DQd DQd

DQPd

1CE2

A

CE

BWd

BWc

3

SS

CE

BWa

VDDV

CLKWECEN

BWb

OE

100999897969594939291908988878685848382

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CY7C1370CV25

(512K × 36)

17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

A

ADV/LD

A

81

DDQ SS

SS

DDQ

SS

DD

ZZ

DDQ

SS

DQa

SS

DDQ

DQPa

NC NC NC

V

DDQ

V

SS

NC

NC DQb DQb

V

SS

V

DDQ

DQb DQb

NC

V

DD

NC

V

SS

DQb DQb

V

DDQ

V

SS

DQb DQb

DQPb

NC

V

SS

V

DDQ

NC

DQPb

80

DQb

79

DQb

78

V

77

V

76

DQb

75

DQb

74

DQb

73

DQb

72

V

71

V

70

DQb

69

DQb

68

V

67

NC

66

V

65 64

DQa

63

DQa

62

V

61

V

60

DQa

59

DQa

58

DQa

57 56

V

55

V

54

DQa

53

DQa

52 51

50

1CE2

A

CE

100999897969594939291908988878685848382

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

bBWa

3

NC

BW

CE

VDDV

SS

CLKWECEN

CY7C1372CV25

(1M × 18)

OE

A

ADV/LD

A

81

A

80

NC

79

NC

78

V

77

DDQ

V

SS

76

NC

75

DQP

74

DQa DQa V

SS

V

DDQ

DQa DQa V

SS

NC V

DD

ZZ DQa DQa V

DDQ

V

SS

DQa DQa NC NC V

SS

V

DDQ

NC NC NC

73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

50

AAA

MODE

1A0

A

E(288)

V

E(144)

SS

DD

V

E(72)

E(36)

A

AAA

A

AAA

MODE

1A0

A

E(144)

E(288)

AAA

A

E(72)

A

E(36)

DD

SS

V

A

Document #: 38-05235 Rev. *C Page 3 of 27

Pin Configurations (continued)

V

A

B C

DQ

D

E

V

F G

DQ

H

V

J

DQ

K

DQ

L

V

M

DQ

N

DQ

P

R T

V

U

119-ball BGA Pinout

CY7C1370CV25 (512K × 36) – 14 × 22 BGA

2345 671

DDQ

NC

DQ

DDQ

DQ

DDQ

NC

DDQ

c

d

AA AAAV

CE

A

DQP

DQ

V

DD

DQ

DQd

DQ

DQP

A

E(72)

TMS

2

c

d

A

V

SS

V

SS

V

SS

BW

V

SS

NC

V

SS

BW

V

SS

V

SS

V

SS

MODE

A

ADV/LD

V

DD

NC DQP

CE

1

OE

c

A

WE V

DD

CLK

NC

d

CEN

A1

A0 V

V

DD

A

TCK

ACE3NC

AANC

V

SS

V

SS

V

SS

BW

b

V

SS

NC V

V

SS

BW

a

V

SS

V

SS

NC

A

b

DQ

b

DQ

b

DQ

b

DQ

b

DD

DQ

a

DQ

a

DQ

a

DQ

a

DQP

a

E(36)

NCTDI TDO V

CY7C1370CV25

CY7C1372CV25

DDQ

DQ

b

DQ

b

V

DDQ

DQ

b

DQ

b

V

DDQ

DQ

a

DQ

a

V

DDQ

DQ

a

DQ

a

NCA

ZZ

DDQ

CY7C1372CV25 (1M x 18)–14 x 22 BGA

2345671

V

A

B C D

E F

G H J

K

L M N

P

R

T U

DDQ

NC

V

DDQ

NC

DQ

V

DDQ

NC

DQ

V

DDQ

DQ

NC

E(72)

V

DDQ

b

AA AAAV

CE

A

NCDQ

DQ

NC

DQ

NC

V

DD

DQ

NC

DQ

NC

DQP

A

TMS

2

b

A

V

SS

V

SS

V

SS

BW

V

SS

NC

V

SS

V

SS

V

SS

V

SS

V

SS

MODE

A

ADV/LD

V

DD

NC NCDQP

CE

1

OE

b

AVSSNC

WE

V

DD

CLK

NC NC

CEN

A1

A0 V

V

DD

E(36)

A

AANC

V

SS

V

SS

V

SS

V

SS

NC V

SS

BW

a

V

SS

V

SS

NC

A

TCK

CE

3

NC

DQ

a

DQ

a

DD

NCV

DQ

a

NC V

DQ

a

NC

A

NCTDI TDO V

DDQ

NC

a

DQ

a

V

DDQ

DQ

a

NC

V

DDQ

DQ

a

DDQ

NC

DQ

a

NC

ZZ

DDQ

Document #: 38-05235 Rev. *C Page 4 of 27

Pin Configurations (continued)

234 5671

A

B C D

E F G

H J K L

M N P

R

A

B C D

E

G H

K

M N P

R

E(288)

NC

DQP

c

DQ

c

DQ

c

DQ

c

DQ

c

NC

DQ

d

DQ

d

DQ

d

DQ

d

DQP

d

NC

MODE

E(288)

NC

NC V

F

NC

NC NC

J

L

DQ

DQP

b

NC

MODE

A

NC

DQ

NC / V

DQ

NC

E(72)

E(36)

234 5671

A

NC

DQ

NC / V

NC

E(72)

E(36)

CE

CE2

V

c

V

c

V

c

V

c

NC

DD

V

d

V

d

V

d

V

d

V

CE

CE2

V

b

V

b

V

b

V

b

NC

DD

V

165-Ball fBGA Pinout

CY7C1370CV25 (512K × 36) – 13 × 15 fBGA

BW

c

d

BW

V

V V V

V

SS

NC

TDI

TMS

DDQ

A

1

BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

CY7C1372CV25 (1M × 18) – 13 × 15 fBGA

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

DDQ

A

1

BW

b

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

CE

b

CLK

a

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1

CEN

3

WE

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

CE

CLK

a

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1

CEN

3

WE

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

CY7C1370CV25

CY7C1372CV25

891011

V

A

DDQ

NC

DDQ

A

ADV/LD

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

891011

V

A

DDQ

NC

DDQ

A

ADV/LD

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

NC

E(144)

NC DQP

DQ

NC

DQ

NC

A

DQ

b

DQ

b

DQ

b

DQ

b

ZZ

DQ

a

DQ

a

DQ

a

DQ

a

DQP

NC

A

E(144)

NC DQP

NC

NC NC

DQ

NC

A

DQ

ZZ

a

NCV

NC

b

a

AA

A

a

AA

Document #: 38-05235 Rev. *C Page 5 of 27

CY7C1370CV25

CY7C1372CV25

Pin Definitions

Name I/O Type Pin Description

A0, A1, A Input-

Synchronous

BW BW

WE

a, BWb c, BWd

Input-

Synchronous

Input-

Synchronous

ADV/LD

Input-

Synchronous

CLK Input-

Clock

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

CEN

Input-

Synchronous

DQ DQ DQ DQ

DQP DQP

a b c d

DQP

a,

b

DQP

c,

d

I/O-

Synchronous

I/O-

Synchronous

MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved

TDO JTAG serial output

Synchronous

TDI JTAG serial input

Synchronous

TMS Test Mode Select

Synchronous

TCK JTAG-Clock Clock input to the JTAG circuitry.

V

DD

DDQ

SS

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

Ground Ground for the device. Should be connected to ground of the system. NC – No connects. This pin is not connected to the die. NC / VDD – Can either be left unconnected or connected to V

Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK.

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BW DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.

controls DQa and DQPa, BWb controls

a

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.

Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is

advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address.

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN

. CLK is only recognized if CEN is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device.

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.

Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A direction of the pins is controlled by OE and the internal control logic. When OE is

during the previous clock rise of the read cycle. The

[17:0]

asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc

[31:0]

is controlled by BWc, and DQPd is controlled by BWd.

burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

This pin controls the Test Access Port state machine. Sampled on the rising edge

of TCK.

Must not be connected to V

DD.

.

SS.

Document #: 38-05235 Rev. *C Page 6 of 27

CY7C1370CV25

CY7C1372CV25

Pin Definitions (continued)

Name I/O Type Pin Description

E(36,72, 144, 288) – These pins are not connected. They will be used for expansion to the 36M, 72M, 144M

ZZ Input-

Asynchronous

and 288M densities.

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating.

Functional Overview

The CY7C1370CV25 and CY7C1372CV25 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t

) is 3.0 ns (200-MHz device).

CO

Accesses can be initiated by asserting all three Chip Enables (CE

, CE2, CE3) active at the rising edge of the clock. If Clock

1

Enable (CEN

) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE conduct byte write operations.

Write operations are qualified by the Write Enable (WE writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE asynchronous Output Enable (OE All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN and CE signal WE

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.2 ns (200-MHz device) provided OE clock of the read access the output buffers are controlled by OE

and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise.

). If CEN is HIGH, the clock

). BW

can be used to

[a:d]

). All

, CE2, CE3) and an

1

) simplify depth expansion.

is asserted LOW, (2) CE1, CE2,

is active LOW. After the first

Burst Read Accesses

The CY7C1370CV25 and CY7C1372CV25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD

will increment the internal burst counter regardless of the state of chip enables inputs or WE

. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN and CE is asserted LOW. The address presented to A0–A16 is loaded

are ALL asserted active, and (3) the write signal WE

3

is asserted LOW, (2) CE1, CE2,

into the Address Register. The write signals are latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE allows the external logic to present the data on DQ (DQ for CY7C1372CV25). In addition, the address for the subse-

a,b,c,d

/DQP

for CY7C1370CV25 and DQ

a,b,c,d

input signal. This

and DQP

/DQP

a,b

quent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ

a,b,c,d

/DQP

(DQ CY7C1372CV25) (or a subset for byte write operations, see

for CY7C1370CV25 & DQ

a,b,c,d

a,b

/DQP

and DQP

for

a,b

Write Cycle Description table for details) inputs is latched into the device and the write is complete.

The data written during the Write operation is controlled by BW (BW CY7C1372CV25) signals. The CY7C1370CV25/

for CY7C1370CV25 and BW

a,b,c,d

a,b

for

CY7C1372CV25 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE (BW

) input will selectively write to only the desired bytes. Bytes

) with the selected Byte Write Select

not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations.

Because the CY7C1370CV25 and CY7C1372CV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE deasserted HIGH before presenting data to the DQ

) can be

and DQP

Document #: 38-05235 Rev. *C Page 7 of 27

CY7C1370CV25

CY7C1372CV25

a,b,c,d

/DQP

(DQ for CY7C1372CV25) inputs. Doing so will three-state the output drivers. As a safety precaution, DQ DQP CY7C1372CV25) are automatically three-stated during the

for CY7C1370CV25 and DQ

a,b,c,d

for CY7C1370CV25 and DQ

a,b,c,d

a,b

and DQP (DQ

/DQP

a,b

/DQP

a,b,c,d

for

a,b

data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1370CV25/CY7C1372CV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD

must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE CE

) and WE inputs are ignored and the burst counter is incre-

3

mented. The correct BW BW

for CY7C1372CV25) inputs must be driven in each

a,b

cycle of the burst write in order to write the correct bytes of

(BW

for CY7C1370CV25 and

a,b,c,d

, CE2, and

1

data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed.

considered valid nor is the completion of the operation

a,b

guaranteed. The device must be deselected prior to entering the “sleep” mode. CE

/

for the duration of t

, CE2, and CE3, must remain inactive

1

after the ZZ input returns LOW.

ZZREC

Interleaved Burst Address Table (MODE = Floating or V

First

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00

Second

Address

DD

)

Third

Address

Linear Burst Address Table (MODE = GND)

First

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10

Second

Address

Third

Address

Fourth

Address

Fourth

Address

Accesses pending when entering the “sleep” mode are not

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Operation

Deselect Cycle None H L L X X X L L-H Three-State Continue Deselect Cycle None X L H X X X L L-H Three-State Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Three-State Dummy Read (Continue Burst) Next X L H X X H L L-H Three-State Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Three-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Three-State IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H – SNOOZE MODE None X H X X X X X X Three-State

Notes:

1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE

3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE

= H inserts wait states.

5. CEN

6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE

7. OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQP

OE

is inactive or when the device is deselected, and DQs=data when OE is active.

Snooze mode standby current ZZ > VDD − 0.2V 60 mA Device operation to ZZ ZZ > VDD − 0.2V 2t ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to snooze current This parameter is sampled 2t ZZ Inactive to exit snooze current This parameter is sampled 0 ns

[1, 2, 3, 4, 5, 6, 7]

Address

Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ

stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid

and BW

. See Write Cycle Description table for details.

[a:d]

signal.

.

[a:d]

CYC

ns ns

CYC

= Three-state when

ns

Document #: 38-05235 Rev. *C Page 8 of 27

CY7C1370CV25

CY7C1372CV25

Partial Write Cycle Description

Function (CY7C1370CV25)

[1, 2, 3, 8]

WE

BW

d

BW

c

BW

b

BW

a

Read H X X X X

Write – No bytes written L H H H H

Write Byte a – (DQa and DQPa) LHHHL

Write Byte b – (DQ

and DQPb)LHHLH

b

Write Bytes b, a L H H L L

Write Byte c – (DQ

and DQPc)LHLHH

c

Write Bytes c, a L H L H L

Write Bytes c, b L H LL L H

Write Bytes c, b, a L H L L L

Write Byte d – (DQ

and DQPd)LLHHH

d

Write Bytes d, a L L H H L

Write Bytes d, b LLHLH

Write Bytes d, b, a L L H L L

Write Bytes d, c L L L H H

Write Bytes d, c, a L L L H L

Write Bytes d, c, b L L L L H

Write All Bytes L L L L L

Function (CY7C1372CV25) WE

BW

b

Read H x x

Write – No Bytes Written L H H

Write Byte a – (DQ

Write Byte b – (DQ

and DQPa)LHL

a

and DQPb)LLH

b

Write Both Bytes L L L

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1370CV25/CY7C1372CV25 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V or 2.5V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately be connected to V be left unconnected. Upon power-up, the device will come up

through a pull-up resistor. TDO should

DD

Test Access Port–Test Clock

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register.

in a reset state which will not interfere with the operation of the device.

Note:

8. Table only lists a partial listing of the byte write combinations. Any combination of BW

is valid. Appropriate write will be done based on which byte write is active.

[a:d]

BW

a

Document #: 38-05235 Rev. *C Page 9 of 27

CY7C1370CV25

CY7C1372CV25

Test Data Out (TDO)

The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

TAP R e gisters

Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The ×36 configuration has a 69-bit-long register, and the ×18 configuration has a 69-bit-long register.

The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.

) for five rising

DD

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard.

The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant.

Document #: 38-05235 Rev. *C Page 10 of 27

CY7C1370CV25

CY7C1372CV25

When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (t captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register.

and tCH). The SRAM clock input might not be

CS

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.

Bypass

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document #: 38-05235 Rev. *C Page 11 of 27

CY7C1370CV25

CY7C1372CV25

TAP Controller State Diagram

1

TEST-LOGIC RESET

0

TEST-LOGIC/

1

IDLE

[9]

1

SELECT DR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

1

EXIT1-DR

0

1

SELECT IR-SCAN

0

1

CAPTURE-DR

0

SHIFT-IR

0

1

EXIT1-IR

1

0

PAUSE-DR

1

0

EXIT2-DR

1

UPDATE-DR

1

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

0

PAUSE-IR

0

1

0

EXIT2-IR

1

UPDATE-IR

1

0

Document #: 38-05235 Rev. *C Page 12 of 27

TAP Controller Block Diagram

Selection Circuitry

TDI

Bypass Register

Instruction Register

CY7C1370CV25

CY7C1372CV25

0

012

Selection Circuitry

TDO

29

3031

012..

Identification Register

.

.68

012..

Boundary Scan Register

TCK

TMS

TAP Electrical Characteristics Over the Operating Range

TAP Controller

[10, 11]

Parameter Description Test Conditions Min. Max. Unit

V

I

OH1

OH2

OL1

OL2

IH

IL

X

Output HIGH Voltage I

Output LOW Voltage IOL = 1.0 mA V

Output LOW Voltage IOL = 100 µAV

Input HIGH Voltage V

Input LOW Voltage V

Input Load Current GND ≤ VI ≤ V

Input Load Current TMS and TDI GND ≤ VI ≤ V

= –1.0 mA V

OH

= –100 µAV

OH

DDQ

= 2.5V 1.7 V

= 2.5V 2.1 V

= 2.5V 0.4 V

= 2.5V 0.2 V

= 2.5V 1.7 VDD + 0.3 V

= 2.5V –0.3 0.7 V

–5 5 µA

TAP AC Switching Characteristics Over the Operating Range

[12, 13]

Parameter Description Min. Max. Unit

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 100 ns

TCK Clock Frequency 10 MHz

TCK Clock HIGH 40 ns

TCK Clock LOW 40 ns

Set-up Times

t

TMSS

t

TDIS

t

CS

TMS Set-up to TCK Clock Rise 10 ns

TDI Set-up to TCK Clock Rise 10 ns

Capture Set-up to TCK Rise 10 ns

Hold Times

t

TMSH

Notes:

10. All voltage referenced to ground.

11. Overshoot: V

12. t

and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

CS

13. Test conditions are specified using the load in TAP AC test conditions. t

TMS Hold after TCK Clock Rise 10 ns

(AC) < V

IH

+ 1.5V for t < t

DD

/2; undershoot: VIL(AC) > −0.5V for t < t

TCYC

R/tF

= 1 ns.

TCYC

/2.

Document #: 38-05235 Rev. *C Page 13 of 27

CY7C1370CV25

CY7C1372CV25

TAP AC Switching Characteristics Over the Operating Range

[12, 13]

(continued)

Parameter Description Min. Max. Unit

t

TDIH

t

CH

TDI Hold after Clock Rise 10 ns

Capture Hold after clock rise 10 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 20 ns

TCK Clock LOW to TDO Invalid 0 ns

TAP Timing and Test Conditions

TDO

1.25V for 2.5V V

= 50Ω

Z

0

(a)

Test Clock TCK

GND

50Ω

C

L

DDQ

= 20 pF

t

TMSS

ALL INPUT PULSES

2.5V

t

TCYC

1.25V

1.5 ns

V

SS

1.5 ns

TH

t

TL

t

TMSH

t

Test Mode Select TMS

t

TDIS

t

TDIH

Test Data-In TDI

Test Data-Out TDO

t

TDOV

t

TDOX

Identification Register Definitions

Instruction Field CY7C1370CV25 CY7C1372CV25 Description

Revision Number (31:29) 010 010 Reserved for version number.

Cypress Device ID (28:12) 01011001000100101 01011001000010101 Reserved for future use.

Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.

ID Register Presence (0) 1 1 Indicate the presence of an ID register.

Document #: 38-05235 Rev. *C Page 14 of 27

CY7C1370CV25

CY7C1372CV25

Scan Register Sizes

Register Name Bit Size(x18) Bit Size (x36)

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan 70 70

Identification Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.

TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

operation does not affect SRAM operation.

Forces all SRAM output drivers to a High-Z state.

Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant.

Document #: 38-05235 Rev. *C Page 15 of 27

119-ball BGA Boundary Scan Order

CY7C1370CV25

CY7C1372CV25

CY7C1370CV25 (512K x 36)

Bit# Ball ID Bit# Ball ID

1

2H437 N4

3M438 R6

4F439 T5

5B440 T3

6A441 R2

7G442 R3

8C643 P2

9A644 P1

10 D6 45 N2

11 D7 46 L2

12 E6 47 K1

13 G6 48 N1

14 H7 49 M2

15 E7 50 L1

16 F6 51 K2

17 G7 5 2 Not Bonded (Preset to 1)

18 H6 53 H1

19 T7 54 G2

20 K7 55 E2

21 L6 56 D1

22 N6 57 H2

23 P7 58 G1

24 K6 59 F2

25 L7 60 E1

26 M6 61 D2

27 N7 62 A5

28 P6 63 A3

29 B5 64 E4

30 B3 65 B2

31 C5 66 L3

32 C3 67 G3

33 C2 68 G5

34 A2 69 L5

35 T4 70 B6

K4

36 P4

CY7C1372CV25 (1M x 18)

Bit# Ball ID Bit# Ball ID

1

2H437N4

3M438R6

4F439T5

5B440T3

6A441R2

7G442R3

8 C 6 4 3 Not Bonded (Preset to 0)

9 A6 4 4 Not Bonded (Preset to 0)

10 T6 45 Not Bonded (Preset to 0)

11 Not Bonded (Preset to 0) 46 Not Bonded (Preset to 0)

12 Not Bonded (Preset to 0) 47 P2

13 Not Bonded (Preset to 0) 48 N 1

14 D6 49 M2

15 E7 50 L1

16 F6 51 K2

17 G7 52 Not Bonded (Preset to 1)

18 H6 53 H1

19 T7 54 G2

20 K7 55 E2

21 L6 56 D1

22 N 6 57 Not Bonded (Preset to 0)

23 P7 58 Not Bonded (Preset to 0)

24 Not Bonded (Preset to 0) 59 Not Bonded (Preset to 0)

25 Not Bonded (Preset to 0) 60 Not Bonded (Preset to 0)

26 Not Bonded (Preset to 0) 61 Not Bonded (Preset to 0)

27 Not Bonded (Preset to 0) 62 A5

28 Not Bonded (Preset to 0) 63 A3

29 B5 64 E4

30 B3 65 B2

31 C 5 66 Not Bonded (Preset to 0)

32 C3 67 G3

33 C 2 68 Not Bonded (Preset to 0)

34 A2 69 L5

35 T2 70 B6

K4

36 P4

Document #: 38-05235 Rev. *C Page 16 of 27

CY7C1370CV25

CY7C1372CV25

165-Ball fBGA Boundary Scan Order

CY7C1370CV25 (512K x 36)

Bit# Ball Id Bit# Ball Id

1B636 R6

2B737 P6

3A738 R4

4B839 R3

5A840 P4

6B941 P3

7A942 R1

8B1043 N1

9 A10 44 L2

10 C11 45 K2

11 E10 46 J2

12 F10 47 M2

13 G10 48 M1

14 D10 49 L1

15 D11 50 K1

16 E11 51 J1

17 F11 52 Not Bonded

(Preset to 1)

18 G11 53 G2

19 H11 54 F2

20 J10 55 E2

21 K10 56 D2

22 L10 57 G1

23 M10 58 F1

24 J11 59 E1

25 K11 60 D1

26 L11 61 C1

27 M11 62 A2

28 N11 63 B2

29 R11 64 A3

30 R10 65 B3

31 R9 66 B4

32 R8 67 A4

33 P10 68 A5

34 P9 69 B5

35 P8 70 A6

CY7C1372CV25 (1M x 18)

Bit# Ball ID Bit# Ball ID

1B636R6

2B737P6

3A738R4

4B839R3

5A840P4

6B941P3

7A942R1

8 B10 43 Not Bonded (Preset to 0)

9 A10 44 Not Bonded (Preset to 0)

10 A 11 45 Not Bonded (Preset to 0)

11 Not Bonded (Preset to 0) 46 Not Bonded (Preset to 0)

12 Not Bonded (Preset to 0) 47 N1

13 Not Bonded (Preset to 0) 48 M1

14 Not Bonded (Preset to 0) 49 L1

15 D11 50 K1

16 E11 51 J1

17 F11 52 Not Bonded

(Preset to 1)

18 G11 53 G2

19 H11 54 F2

20 J10 55 E2

21 K10 56 D2

22 L10 57 Not Bonded (Preset to 0)

23 M10 58 Not Bonded (Preset to 0)

24 Not Bonded (Preset to 0) 59 Not Bonded (Preset to 0)

25 Not Bonded (Preset to 0) 60 Not Bonded (Preset to 0)

26 Not Bonded (Preset to 0) 61 Not Bonded (Preset to 0)

27 Not Bonded (Preset to 0) 62 A2

28 Not Bonded (Preset to 0) 63 B2

29 R11 64 A3

30 R10 65 B3

31 R 9 66 Not Bonded (Preset to 0)

32 R 8 67 Not Bonded (Preset to 0)

33 P10 68 A4

34 P9 69 B5

35 P8 70 A6

Document #: 38-05235 Rev. *C Page 17 of 27

CY7C1370CV25

CY7C1372CV25

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

DC to Outputs in Tri-State ................... –0.5V to V

DC Input Voltage ....................................–0.5V to V

Relative to GND........ –0.5V to +4.6V

DD

+ 0.5V

DDQ

+ 0.5V

DD

Electrical Characteristics Over the Operating Range

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Operating Range

Range

Commercial 0°C to +70°C 2.5V–5%/+5% 2.5V –5% to

Industrial –40°C to +85°C

[14, 15]

Ambient

Temperat ure V

DD

V

DDQ

V

DD

Parameter Description Test Conditions Min. Max. Unit

V

I

DD

DDQ

OH

OL

IH

IL

X

Power Supply Voltage 2.375 2.625 V

I/O Supply Voltage V

Output HIGH Voltage VDD = Min., IOL= −1.0 mA, V

Output LOW Voltage VDD = Min., IOL= 1.0 mA, V

Input HIGH Voltage V

Input LOW Voltage

[14]

Input Load Current GND ≤ VI ≤ V

= 2.5V 2.375 V

DDQ

= 2.5V 2.0 V

DDQ

= 2.5V 0.4 V

DDQ

= 2.5V 1.7 VDD + 0.3V V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

–5 5 µA

DD

Input Current of MODE –30 30 µA

I

OZ

DD

Output Leakage Current GND ≤ VI ≤ V

VDD Operating Supply V

DD

f = f

= Max., I

= 1/t

MAX

Output Disabled –5 5 µA

DDQ,

OUT

CYC

= 0 mA,

4.0-ns cycle, 250 MHz 350 mA

4.4-ns cycle, 225 MHz 325 mA

5.0-ns cycle, 200 MHz 300 mA

6.0-ns cycle, 167 MHz 275 mA

I

SB1

Automatic CE Power-down Current—TTL Inputs

Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = f 1/t

CYC

MAX

4.0-ns cycle, 250 MHz 120 mA

=

4.4-ns cycle, 225 MHz 110 mA

5.0-ns cycle, 200 MHz 100 mA

6.0-ns cycle, 167 MHz 90 mA

I

SB2

I

SB3

Automatic CE Power-down Current—CMOS Inputs

Max. VDD, Device Deselected, VIN ≤ 0.3V or VIN > V f = 0

DDQ

− 0.3V,

Max. VDD, Device Deselected, VIN ≤ 0.3V or VIN > V f = f

MAX

= 1/t

CYC

DDQ

− 0.3V,

All speed grades 70 mA

4.0-ns cycle, 250 MHz 105 mA

4.4-ns cycle, 225 MHz 100 mA

5.0-ns cycle, 200 MHz 95 mA

6.0-ns cycle, 167 MHz 85 mA

I

SB4

Automatic CE Power-down

Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0

All speed grades 80 mA

Current—TTL Inputs

Shaded areas contain advance information.

Notes:

14. Overshoot: V

15. T

Power-up

IH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).

: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.

V

Document #: 38-05235 Rev. *C Page 18 of 27

CY7C1370CV25

CY7C1372CV25

Capacitance

[16]

Parameter Description Test Conditions BGA Max. fBGA Max. TQFP Max. Unit

C

Input Capacitance TA = 25°C, f = 1 MHz,

IN

C

CLK

C

I/O

Clock Input Capacitance 8 9 5 pF

Input/Output Capacitance 8 9 5 pF

VDD = 2.5V V

AC Test Loads and Waveforms

OUTPUT

= 50Ω

Z

0

(a) (b)

Thermal Resistance

V

[16]

L

R

= 1.25V

= 50Ω

L

2.5V

Output

5pF

INCLUDING

JIG AND

SCOPE

DDQ

= 2.5V

R=1667Ω

R = 1538Ω

895pF

[16]

90%

10%

< 1.0 ns

V

0V

DD

<

1.0 ns

ALL INPUT PULSES

90%

10%

1.25V

(c)

Parameters Description Test Conditions BGA Typ. fBGA Typ. TQFP Typ. Unit Notes

Q

JA

Q

JC

Switching Characteristics Over the Operating Range

Thermal Resistance (Junction to Ambient)

Thermal Resistance (Junction to Case)

Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51.

[ 21, 22]

45 46 31 °C/W 17

736°C/W 17

-250 -225 -200 -167

Parameter Description

t

Power

[17]

VCC (typical) to the first access read or write 1 111 ms

UnitMin. Max. Min. Max. Min. Max. Min. Max.

Clock

t

CYC

F

t

CH

t

CL

MAX

Clock Cycle Time 4.0 4.4 5 6 ns

Maximum Operating Frequency 250 225 200 166 MHz

Clock HIGH 1.7 2.0 2.0 2.2 ns

Clock LOW 1.7 2.0 2.0 2.2 ns

Output Times

t

CO

t

EOV

t

DOH

t

CHZ

t

CLZ

t

EOHZ

t

EOLZ

Data Output Valid After CLK Rise 2.6 2.8 3.0 3.4 ns

OE LOW to Output Valid 2.6 2.8 3.0 3.4 ns

Data Output Hold After CLK Rise 1.0 1.0 1.3 1.3 ns

Clock to High-Z

Clock to Low-Z

HIGH to Output High-Z

OE OE LOW to Output Low-Z

[18, 19, 20]

2.6 2.8 3.0 3.4 ns

1.0 1.0 1.3 1.3 ns

2.6 2.8 3.0 3.4 ns

0 000 ns

Set-up Times

t

AS

t

DS

Shaded areas contain advance information.

Notes:

16. Tested initially and after any design or process changes that may affect these parameters.

17. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be initiated.

, t

18. t

CHZ

CLZ

19. At any given voltage and temperature, t data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

20. This parameter is sampled and not 100% tested.

21. Timing reference is 1.25V when V

22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Address Set-up Before CLK Rise 1.2 1.4 1.4 1.5 ns

Data Input Set-up Before CLK Rise 1.2 1.4 1.4 1.5 ns

, t

EOLZ

, and t

are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

EOHZ

DDQ=

EOHZ

2.5V.

is less than t

EOLZ

and t

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

Document #: 38-05235 Rev. *C Page 19 of 27

123456789

10

I

[23,24,25]

CY7C1370CV25

CY7C1372CV25

Switching Characteristics Over the Operating Range (continued)

-250 -225 -200 -167

Parameter Description

t

CENS

t

WES

t

ALS

t

CES

CEN Set-up Before CLK Rise WE, BWx Set-up Before CLK Rise

ADV/LD Set-up Before CLK Rise Chip Select Set-up 1.2 1.4 1.4 1.5 ns

1.2 1.4 1.4 1.5 ns

Hold Times

t

AH

t

DH

t

CENH

t

WEH

t

ALH

t

CEH

Address Hold After CLK Rise 0.3 0.4 0.4 0.5 ns

Data Input Hold After CLK Rise 0.3 0.4 0.4 0.5 ns

CEN Hold After CLK Rise

WE, BWx Hold After CLK Rise

ADV/LD Hold after CLK Rise

0.3 0.4 0.4 0.5 ns

Chip Select Hold After CLK Rise 0.3 0.4 0.4 0.5 ns

Switching Waveforms

Read/Write/Timing

t

CYC

CLK

t

CEN

CENS

t

CES

t

CENH

t

CEH

t

CL

CH

[ 21, 22]

UnitMin. Max. Min. Max. Min. Max. Min. Max.

CE

ADV/LD

WE

BW

x

ADDRESS

Data

n-Out (DQ)

OE

A1 A2

t

AH

AS

WRITE

D(A1)

WRITE

D(A2)

A3

t

DH

DS

D(A1) D(A2) D(A5)Q(A4)Q(A3)

BURST WRITE

D(A2+1)

READ Q(A3)

A4

t

CO

t

CLZ

D(A2+1)

READ

Q(A4)

t

BURST

READ

Q(A4+1)

DOH

A5 A6 A7

t

OEV

Q(A4+1)

t

OEHZ

t

OELZ

WRITE

D(A5)

READ Q(A6)

DON’T CARE UNDEFINED

Notes:

23. For this waveform ZZ is tied low.

24. When CE

25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.

is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

t

CHZ

t

DOH

WRITE

D(A7)

Q(A6)

DESELECT

Document #: 38-05235 Rev. *C Page 20 of 27

Switching Waveforms (continued)

45678910

123

A

NOP,STALL AND DESELECT Cycles

CLK

CEN

CE

ADV/LD

WE

BWx

[23,24,26]

CY7C1370CV25

CY7C1372CV25

ADDRESS

A1

A2

Data

In-Out (DQ)

READ Q(A2)

ZZ Mode Timing

D(A1)

[27,28]

CLK

ZZ

I

SUPPLY

LL INPUTS

(except ZZ)

A3 A4

D(A1) Q(A2) Q(A3)

STALL NOP READ

READ Q(A3)

WRITE

D(A4)

STALLWRITE

A5

D(A4)

DESELECT CONTINUE

Q(A5)

DON’T CARE UNDEFINED

t

ZZ

t

ZZI

I

DDZZ

t

ZZREC

t

RZZI

DESELECT or READ Only

t

CHZ

Q(A5)

DESELECT

Outputs (Q)

High-Z

DON’T CARE

Notes:

26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN

27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

28. I/Os are in High-Z when exiting ZZ sleep mode.

being used to create a pause. A write is not performed during this cycle

Document #: 38-05235 Rev. *C Page 21 of 27

Ordering Information

Speed

(MHz) Ordering Code

250

225 CY7C1370CV25-225AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)

200 CY7C1370CV25-200AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)

167 CY7C1370CV25-167AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)

CY7C1370CV25-250AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial

CY7C1372CV25-250AC

CY7C1370CV25-250BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372CV25-250BGC

CY7C1370CV25-250BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)

CY7C1372CV25-250BZC

CY7C1372CV25-225AC

CY7C1370CV25-225BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372CV25-225BGC

CY7C1370CV25-225BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)

CY7C1372CV25-225BZC

CY7C1372CV25-200AC

CY7C1370CV25-200BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372CV25-200BGC

CY7C1370CV25-200BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)

CY7C1372CV25-200BZC

CY7C1372CV25-167AC

CY7C1370CV25-167BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372CV25-167BGC

CY7C1370CV25-167BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)

CY7C1372CV25-167BZC

Package

Name Package Type

CY7C1370CV25

CY7C1372CV25

Operating

Range

Document #: 38-05235 Rev. *C Page 22 of 27

Ordering Information (continued)

Speed

(MHz) Ordering Code

250

225

200

167 CY7C1370CV25-167AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

CY7C1370CV25-250AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial

CY7C1372CV25-250AI

CY7C1370CV25-250BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372CV25-250BGI

CY7C1370CV25-250BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)

CY7C1372CV25-250BZI

CY7C1370CV25-225AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)

CY7C1372CV25-225AI

CY7C1370CV25-225BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372CV25-225BGI

CY7C1370CV25-225BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)

CY7C1372CV25-225BZI

CY7C1370CV25-200AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)

CY7C1372CV25-200AI

CY7C1370CV25-200BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372CV25-200BGI

CY7C1370CV25-200BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)

CY7C1372CV25-200BZI

CY7C1372CV25-167AI

CY7C1370CV25-167BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372CV25-167BGI

CY7C1370CV25-167BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)

CY7C1372CV25-167BZI

Package

Name Package Type

CY7C1370CV25

CY7C1372CV25

Operating

Range

Document #: 38-05235 Rev. *C Page 23 of 27

Package Diagrams

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

CY7C1370CV25

CY7C1372CV25

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

20.00±0.10

22.00±0.20

16.00±0.20

14.00±0.10

100

1

30

31 50

0° MIN.

R0.08MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

81

80

0.30±0.08

0.65 TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

DIMENSIONS ARE IN MILLIMETERS.

12°±1°

(8X)

SEATING PLANE

1.40±0.05

0.20 MAX.

1.60 MAX.

0.10

SEE DETAIL

A

51-85050-*A

Document #: 38-05235 Rev. *C Page 24 of 27

Package Diagrams (continued)

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

CY7C1370CV25

CY7C1372CV25

51-85115-*B

Document #: 38-05235 Rev. *C Page 25 of 27

Package Diagrams (continued)

165-Ball FBGA (13 x 15 x 1.2 mm) BB165A

CY7C1370CV25

CY7C1372CV25

51-85122-*C

ZBT is a registered trademark of Integrated Device Technology. No Bus Latency and NoBL are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.

Document #: 38-05235 Rev. *C Page 26 of 27

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C1370CV25

CY7C1372CV25

Document History Page

Document Title: CY7C1370CV25/CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05235

REV. ECN No. Issue Date

** 116273 08/27/02 SKX New Data Sheet

*A 121536 11/21/02 DSG Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122

*B 206100 see ECN RKF Final Data Sheet

*C 231349 See ECN DIM Pin H2 (165 fBGA) changed from NC to NC/

Orig. of

Change Description of Change

(BB165A) to rev. *C

V

Updated ordering information: unshade active parts.

DD

.

Document #: 38-05235 Rev. *C Page 27 of 27

Datasheet CY7C1370CV25, CY7C1372CV25 Datasheet (CIRRUS LOGIC)

Specifications and Main Features

Frequently Asked Questions

User Manual