Datasheet CY7C1354B, CY7C1356B Datasheet (CYPRESS)

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查询CY7C1354B-166AC供应商

CY7C1354B

CY7C1356B

9-Mb (256K x 36/512K x 18) Pipelined SRAM

with NoBL™ Architecture

Features

• Pin-compatible and functionally equivalent to ZBT

• Supports 225-MHz bus operations with zero wait states

— Available speed grades are 225, 200, and 166 MHz

• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined op­eration

• Byte Write capability

• Separate V

• Single 3.3V power supply

• Fast clock-to-output times

— 2.8 ns (for 225-MHz device)

— 3.2ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

• Clock Enable (CEN

• Synchronous self-timed writes

• Available in 100 TQFP, 119 BGA, and 165 fBGA packag­es

• IEEE 1149.1 JTAG Boundary Scan

• Burst capability–linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

for 3.3V or 2.5V I/O

DDQ

) pin to suspend operation

Functional Description

The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and
512K x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1354B and CY7C1356B are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans­ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1354B and CY7C1356B are
pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle.

Write operations are controlled by the Byte Write Selects
(BW

–BWd for CY7C1354B and BWa–BWb for CY7C1356B)

a

and a Write Enable (WE

) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

, CE2, CE3) and an

1

) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

) signal,

Logic Block Diagram-CY7C1354B (256K x 36)

A0, A1, A

MODE

C

CLK

EN

ADV/LD

BW

a

BW

b

BW

c

BW

d

WE

OE
CE1
CE2
CE3

ZZ

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

ADV/LD

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

C

REGISTER 2

A1

D1D0Q1

A0

BURST
LOGIC

A1'
A0'

Q0

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER 1

O

S

U
T

E

P

N

U
T

S
E

R
E
G

A

I

M

S
T

P

E

S

R
S

E

E

REGISTER 0

INPUT

O

D

U
T

A

P

T

U

A

T
B

S
T
E
E
R

I
N
G

E

DQs

U

DQP

F

DQP

F

DQP

E

DQP

R
S

E

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05114 Rev. *C Revised June 16, 2004

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Logic Block Diagram-CY7C1356B (512K x 18)

CY7C1354B

CY7C1356B

CLK

A0, A1, A

MODE

C

EN

ADV/LD

BW

a

BW

b

WE

OE
CE1
CE2
CE3

ZZ

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

ADV/LD

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

Sleep

Control

C

REGISTER 2

A1

D1D0Q1

A0

BURST
LOGIC

A1'
A0'

Q0

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER 1

O
U
T
P

S

U

E

T

N
S

R

E

E
G

A

I

M

S

P

T

S

E
R
S

E

E

REGISTER 0

INPUT

O
U
T
P

D

U

A

T

T

A

B

DQs

U

S

F

T
E
E
R

I
N
G

E

DQP

F

DQP

E
R
S

E

Selection Guide

CY7C1354B-225
CY7C1356B-225

Maximum Access Time 2.8 3.2 3.5 ns
Maximum Operating Current 250 220 180 mA
Maximum CMOS Standby Current

Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.

35 35 35 mA

CY7C1354B-200
CY7C1356B-200

CY7C1354B-166
CY7C1356B-166

Unit

Document #: 38-05114 Rev. *C Page 2 of 29

Pin Configurations

a

CY7C1354B

CY7C1356B

100-pin TQFP Packages

DQPc

DQc
DQc

V

DDQ

V

SS

DQc
DQc

DQc
DQc

V

SS

V

DDQ

DQc

DQc

NC

V

DD

NC

V

SS

DQd
DQd

V

DDQ

V

SS

DQd
DQd
DQd

DQd

V

SS

V

DDQ

DQd
DQd

DQPd

1CE2

A

A

CE

BWd

BWc

BWa

BWb

CE3VDDV

SS

CLKWECENOEE(18)

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

CY7C1354B

(256K × 36)

17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

A

ADV/LD

A

A

81

DDQ
SS

SS

DDQ

SS

DD

ZZ

DDQ

SS

DQa

SS

DDQ

DQPa

NC
NC
NC

V

DDQ

V

NC

NC
DQb
DQb

V

SS

V

DDQ

DQb
DQb

NC

V

DD

NC

V

SS

DQb
DQb

V

DDQ

V

SS

DQb
DQb

DQPb

NC

V

SS

V

DDQ

NC

NC

NC

SS

DQPb

80

DQb

79

DQb

78

V

77

V

76

DQb

75

DQb

74

DQb

73

DQb

72

V

71

V

70

DQb

69

DQb

68

V

67

NC

66

V

65
64

DQa

63

DQa

62

V

61

V

60

DQa

59

DQa

58

DQa

57
56

V

55

V

54

DQa

53

DQa

52
51

50

1CE2

A

A

CE

NC

NC

BWb

BWa

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

CY7C1356B

(512K × 18)

18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

CE3VDDV

SS

CLKWECENOEE(18)

ADV/LD

A

A

A

81

A

80

NC

79

NC

78

V

77

DDQ

V

SS

76

NC

75

DQP

74

DQa
DQa
V

SS

V

DDQ

DQa
DQa
V

SS

NC
V

DD

ZZ
DQa
DQa
V

DDQ

V

SS

DQa
DQa
NC
NC
V

SS

V

DDQ

NC
NC
NC

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

AAA

MODE

1A0

A

A

E(288)

V

E(144)

SS

DD

V

E(72)

E(36)

A

AAA

A

A

A

A

AAA

MODE

1A0

A

E(144)

E(288)

AAA

A

E(72)

A

E(36)

DD

SS

V

V

A

A

Document #: 38-05114 Rev. *C Page 3 of 29

Pin Configurations (continued)

V

A

B
C
D

E

V

F
G
H

V

J
K
L

V

M
N
P

R
T

V

U

119-ball BGA Pinout

CY7C1354B (256K × 36) – 14 × 22 BGA

2345 671

DDQ

NC

NC

DQ

DQ

DDQ

DQ

DQ

DDQ

DQ

DQ

DDQ

DQ

DQ

NC

NC

DDQ

c

c

c

c

d

d

d

d

AA AAE(18) V

CE

A

DQP

DQ

DQ

DQ

DQ

V

DD

DQ

DQ

DQd

DQ

DQP

A

E(72)

TMS

2

c

c

c

c

c

d

d

d

d

A

A

V

SS

V

SS

V

SS

BW

V

SS

NC

V

SS

BW

V

SS

V

SS

V

SS

MODE

A

ADV/LD

V

DD

NC DQP

CE

1

OE

c

A

WE

V

DD

CLK

NC

d

CEN

A1

A0 V

V

DD

AE(36)

TCK

DDQ

ACE3NC

AANC

V

SS

V

SS

V

SS

BW

b

V

SS

NC V

V

SS

BW

a

V

SS

V

SS

SS

NC

A

DQ

DQ

DQ

DQ

DD

DQ

DQ

DQ

DQ

DQP

NCTDI TDO V

DQ

b

b

b

b

b

a

a

a

a

a

DQ

V

DQ

DQ

V

DQ

DQ

V

DQ

DQ

b

b

DDQ

b

b

DDQ

a

a

DDQ

a

a

NCA

ZZ

DDQ

CY7C1354B

CY7C1356B

CY7C1356B (512K x 18)–14 x 22 BGA

2345671

V

A

B
C
D

E
F

G
H
J

K
L

M
N

P

R

T

U

DDQ

NC

NC

NC

V

DDQ

NC

DQ

V

DDQ

NC

DQ

V

DDQ

DQ

NC

NC

E(72)

V

DDQ

b

b

b

b

AA AAE(18) V

CE

A

NCDQ

DQ

NC

DQ

NC

V

DD

DQ

NC

DQ

NC

DQP

A

A

TMS

2

b

b

b

b

b

A

A

V

SS

V

SS

V

SS

BW

V

SS

NC

V

SS

V

SS

V

SS

V

SS

V

SS

MODE

A

ADV/LD

V

DD

NC NCDQP

CE

1

OE

b

AVSSNC

WE

V

DD

CLK

NC NC

CEN

A1

A0 V

V

DD

E(36)

A

AANC

V

SS

V

SS

V

SS

V

SS

NC V

SS

BW

a

V

SS

V

SS

SS

NC

A

TCK

CE

3

a

NC

DQ

a

DQ

a

DD

NCV

DQ

a

NC V

DQ

a

NC

A

A

NCTDI TDO V

V

V

DDQ

NC

DQ

DDQ

DQ

NC

DDQ

DQ

DDQ

NC

DQ

NC

ZZ

DDQ

a

a

a

a

Document #: 38-05114 Rev. *C Page 4 of 29

Pin Configurations (continued)

234 5671

A

A

NC

DQ

DQ

DQ

DQ

NC

DQ

DQ

DQ

DQ

NC

E(72)

E(36)

234 5671

A

A

NC

DQ

DQ

DQ

DQ

NC

NC

NC

NC

NC

NC

E(72)

E(36)

CE

CE2

V

V

c

V

c

V

c

V

c

NC

V

d

V

d

V

d

V

d

V

CE

CE2

V

V

b

V

b

V

b

V

b

NC

V

V

V

V

V

M
N

R

M

E(288)

A

B
C
D

E
F
G

H
J
K
L

P

NC

DQP

DQ

DQ

DQ

DQ

NC

DQ

DQ

DQ

DQ

DQP

NC

c

c

c

c

c

d

d

d

d

d

MODE

E(288)

A

B
C
D

E
F
G

H

J
K
L

N
P

R

NC

NC

NC

NC V

NC

NC
NC

DQ

b

DQ

b

DQ

b

DQ

b

DQP

b

NC

MODE

165-Ball fBGA Pinout

CY7C1354B (256K × 36) – 13 × 15 fBGA

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

BW

1

BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

BW

c

BW

d

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

CE

b

a

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

3

NC

A1

CY7C1356B (512K × 18) – 13 × 15 fBGA

CE

3

CLK

a

V

SS

V

SS

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

BW

1

b

NC

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

CEN

WE

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

CEN

WE

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

CY7C1354B

CY7C1356B

891011

A AADV/LD

OE E(18)

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

V

V

V

V

V

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

A

NC DQP

DQ

b

DQ

b

DQ

b

DQ

b

NC

DQ

a

DQ

a

DQ

a

DQ

a

NC

A

891011

ADV/LD

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

A

A

A A

E(18)

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A

NC DQP

NC

NC

NC

NC
NC

DQ

a

DQ

a

DQ

a

DQ

a

NC

A

NC

E(144)

DQ

b

DQ

b

DQ

b

DQ

b

ZZ

DQ

a

DQ

a

DQ

a

DQ

a

DQP

NC

AA

A

E(144)

DQ

a

DQ

a

DQ

a

DQ

a

ZZ

NCV

NC

NC

NC

NC

NC

AA

b

a

a

Document #: 38-05114 Rev. *C Page 5 of 29

CY7C1354B

CY7C1356B

Pin Definitions

Pin Name I/O Type Pin Description

A0
A1

Input-

Synchronous

A

BW
BW
BW
BW

WE

a
b
c
d

Input-

Synchronous

Input-

Synchronous

ADV/LD

Input-

Synchronous

CLK Input-

Clock

CE

CE

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

CEN

Input-

Synchronous

DQ
DQ
DQ
DQ

DQP
DQP
DQP
DQP

a
b
c
d

a
b
c
d

I/O-

Synchronous

I/O-

Synchronous

MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

TDO JTAG serial output

Synchronous

TDI JTAG serial input

Synchronous

TMS Test Mode Select

Synchronous

TCK JTAG-Clock Clock input to the JTAG circuitry.

V

V

V

DD

DDQ

SS

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

Ground Ground for the device. Should be connected to ground of the system.

Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sam­pled on the rising edge of CLK. BW
controls DQ

and DQPc, BWd controls DQd and DQPd.

c

controls DQa and DQPa, BWb controls DQb and DQPb, BWc

a

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.

Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
new address can be loaded into the device for an access. After being deselected, ADV/LD

is asserted LOW) the internal burst counter is advanced. When LOW, a

should

be driven LOW in order to load a new address.

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN
CLK is only recognized if CEN

is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE3 to select/deselect the device.

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE3 to select/deselect the device.

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE2 to select/deselect the device.

1

Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a Write sequence, during the first clock when emerging from a dese­lected state and when the device has been deselected.

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN

can be used to extend the previous cycle when required.

does not

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins
is controlled by OE
as outputs. When HIGH, DQ
matically three-stated during the data portion of a write sequence, during the first clock when

and the internal control logic. When OE is asserted LOW, the pins can behave

–DQd are placed in a three-state condition. The outputs are auto-

a

emerging from a deselected state, and when the device is deselected, regardless of the state of
OE

.

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled

[a:d].

During

by BWc, and DQPd is controlled by BWd.

Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

.

Document #: 38-05114 Rev. *C Page 6 of 29

Pin Definitions (continued)

Pin Name I/O Type Pin Description

NC – No connects. This pin is not connected to the die.
E(18,36,

72, 144,

288)

ZZ Input-

– These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M

and 288M densities.

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

Asynchronous

with data integrity preserved. During normal operation, this pin can be connected to V
floating.

CY7C1354B

CY7C1356B

or left

SS

Introduction

Functional Overview

The CY7C1354B and CY7C1356B are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t

) is 2.8 ns (225-MHz device).

CO

Accesses can be initiated by asserting all three Chip Enables
(CE

, CE2, CE3) active at the rising edge of the clock. If Clock

1

Enable (CEN
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE
Writes are simplified with on-chip synchronous self-timed
Write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.8 ns
(225-MHz device) provided OE
clock of the read access the output buffers are controlled by
OE

and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one

). If CEN is HIGH, the clock signal is not

. All data

) is active LOW and ADV/LD is asserted LOW,

). BW

can be used to

[d:a]

). All

, CE2, CE3) and an

1

) simplify depth expansion.

is asserted LOW, (2) CE1, CE2,

is active LOW. After the first

of the chip enable signals, its output will three-state following
the next clock rise.

Burst Read Accesses

The CY7C1354B and CY7C1356B have an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD

must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi­ciently. A HIGH input on ADV/LD

will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to A0∠A16 is loaded

are ALL asserted active, and (3) the Write signal WE

3

is asserted LOW, (2) CE1, CE2,

into the Address Register. The write signals are latched into
the Control Logic block.

On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
CY7C1356B). In addition, the address for the subsequent

a,b,c,d

/DQP

for CY7C1354B and DQ

a,b,c,d

input signal. This

and DQP

a,b

/DQP

a,b

for

access (Read/Write/Deselect) is latched into the address
register (provided the appropriate control signals are
asserted).

On the next clock rise the data presented to DQ
(DQ
CY7C1356B) (or a subset for byte write operations, see Write

a,b,c,d

/DQP

for CY7C1354B and DQ

a,b,c,d

a,b

and DQP

/DQP

a,b

for

Cycle Description table for details) inputs is latched into the
device and the Write is complete.

The data written during the Write operation is controlled by BW
(BW
signals. The CY7C1354B/56B provides Byte Write capability

for CY7C1354B and BW

a,b,c,d

for CY7C1356B)

a,b

that is described in the Write Cycle Description table. Asserting
the Write Enable input (WE
Select (BW

) input will selectively write to only the desired

) with the selected Byte Write

bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify

Document #: 38-05114 Rev. *C Page 7 of 29

CY7C1354B

CY7C1356B

Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.

Because the CY7C1354B and CY7C1356B are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE
HIGH before presenting data to the DQ
(DQ
CY7C1356B) inputs. Doing so will three-state the output

a,b,c,d

/DQP

for CY7C1354B and DQ

a,b,c,d

drivers. As a safety precaution, DQ
DQP
CY7C1356B) are automatically three-stated during the data

for CY7C1354B and DQ

a,b,c,d

) can be deasserted

and DQP

/DQP

a,b

and DQP

a,b

(DQ

/DQP

a,b

a,b

a,b,c,d

for

for

portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1354B/56B has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address
inputs. ADV/LD

must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD
rise, the chip enables (CE
ignored and the burst counter is incremented. The correct BW
(BW
must be driven in each cycle of the burst write in order to write

for CY7C1354B and BW

a,b,c,d

is driven HIGH on the subsequent clock

, CE2, and CE3) and WE inputs are

1

for CY7C1356B) inputs

a,b

the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t

, CE2, and CE3, must remain inactive for

1

after the ZZ input returns LOW.

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

/

First

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11
01 00 11 10
10 11 00 01

11 10 01 00

Second

Address

DD

)

Third

Address

Linear Burst Address Table
(MODE = GND)

First

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11
01 10 11 00
10 11 00 01

11 00 01 10

Second

Address

Third

Address

Fourth

Address

Fourth

Address

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Sleep mode standby current ZZ > VDD − 0.2V 35 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to sleep current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

ns
ns
ns

Document #: 38-05114 Rev. *C Page 8 of 29

CY7C1354B

CY7C1356B

Truth Table

[1, 2, 3, 4, 5, 6, 7]

Address

Operation

Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ

Deselect Cycle None H L L X X X L L-H Three-State

Continue

None X L H X X X L L-H Three-State

Deselect Cycle

Read Cycle

External L L L H X L L L-H Data Out (Q)

(Begin Burst)

Read Cycle

Next X L H X X L L L-H Data Out (Q)

(Continue Burst)

NOP/Dummy

External L L L H X H L L-H Three-State
Read
(Begin Burst)

Dummy Read

Next X L H X X H L L-H Three-State
(Continue Burst)

Write Cycle

External L L L L L X L L-H Data In (D)
(Begin Burst)

Write Cycle

Next X L H X L X L L-H Data In (D)
(Continue Burst)

NOP/WRITE

None L L L L H X L L-H Three-State
ABORT
(Begin Burst)

WRITE ABORT

Next X L H X H X L L-H Three-State
(Continue Burst)

IGNORE

Current X L X X X X H L-H ­CLOCK EDGE
(Stall)

Sleep MODE None X H X X X X X X Three-State

Notes:

1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE

3. When a write cycle is detected, all I/Os are three-stated, even during Byte Writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE

= H inserts wait states.

5. CEN

6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP

7. OE
OE

is inactive or when the device is deselected, and DQs = data when OE is active.

and BW

. See Write Cycle Description table for details.

[a:d]

stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx =

signal.

.

[a:d]

= Three-state when

Document #: 38-05114 Rev. *C Page 9 of 29

CY7C1354B

CY7C1356B

Partial Write Cycle Description

Function (CY7C1354B)

[1, 2, 3, 8]

WE

BW

d

BW

c

BW

b

BW

a

Read H X X X X

Write –No bytes written L H H H H

Write Byte a– (DQ

Write Byte b – (DQ

and DQP

a

and DQP

b

a)

b)

LHHHL

LHHLH

Write Bytes b, a L H H L L

Write Byte c – (DQ

and DQP

c

c)

LHLHH

Write Bytes c, a L H L H L

Write Bytes c, b L H L L H

Write Bytes c, b, a L H L L L

Write Byte d – (DQ

and DQP

d

d)

LLHHH

Write Bytes d, a L L H H L

Write Bytes d, b LLHLH

Write Bytes d, b, a L L H L L

Write Bytes d, c L L L H H

Write Bytes d, c, a L L L H L

Write Bytes d, c, b L L L L H

Write All Bytes L L L L L

Note:

8. Table only lists a partial listing of the byte write combinations. Any combination of BW

is valid. Appropriate write will be done based on which byte write is active.

[a:d]

Function (CY7C1356B) WE BW

b

BW

a

Read Hxx

Write – No Bytes Written L H H

Write Byte a − (DQ

Write Byte b – (DQ

and DQP

a

and DQP

b

a)

b)

LHL

LLH

Write Both Bytes L L L

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1354B/CY7C1354B incorporates a serial boundary
scan Test Access Port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This port
operates in accordance with IEEE Standard 1149.1-1900, but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 3.3V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.

Test Access Port–Test Clock

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.

Test Data Out (TDO)

The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State

Document #: 38-05114 Rev. *C Page 10 of 29

CY7C1354B

CY7C1356B

Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.

TAP R e gisters

Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The ×36 configuration has a 69-bit-long
register, and the ×18 configuration has a 69-bit-long register.

The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc­tions can be used to capture the contents of the Input and
Output ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller

) for five rising

DD

is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data, or control signals into
the SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.

The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.

When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.

Document #: 38-05114 Rev. *C Page 11 of 29

CY7C1354B

CY7C1356B

The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK
boundary scan register.

and tCH). The SRAM clock input might not be

CS

captured in the

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.

Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.

Bypass

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

Document #: 38-05114 Rev. *C Page 12 of 29

TAP Controller State Diagram

CY7C1354B

CY7C1356B

1

TEST-LOGIC
RESET

1

0

TEST-LOGIC/
IDLE

1

SELECT
DR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

1

EXIT1-DR

0

PAUSE-DR

1

SELECT
IR-SCAN

0

1

CAPTURE-DR

0

0

SHIFT-IR

0

1

1

EXIT1-IR

1

0

0

PAUSE-IR

0

1

0

EXIT2-DR

1

UPDATE-DR

1

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

1

0

EXIT2-IR

1

UPDATE-IR

1

0

0

Document #: 38-05114 Rev. *C Page 13 of 29

CY7C1354B

CY7C1356B

0

Bypass Register

TDI

Selection
Circuitry

012

Instruction Register

Selection
Circuitry

TDO

29

3031

012..

Identification Register

.

.68

012..

Boundary Scan Register

TCK

TMS

TAP Electrical Characteristics Over the Operating Range

TAP Controller

[10, 11]

Parameter Description Test Conditions Min. Max. Unit

V

OH1

V

OH2

V

OL1

V

OL2

V

IH

V

IL

I

X

I

X

TAP AC Switching Characteristics Over the Operating Range

Output HIGH Voltage I

Output HIGH Voltage I

= 2.0 mA, V

OH

I

= 2.0 mA, V

OH

= 100 µA, V

OH

I

= 100 µA, V

OH

= 3.3V 2.0 V

DDQ

= 2.5V 1.7 V

DDQ

= 3.3V 2.0 V

DDQ

= 2.5V 2.0 V

DDQ

Output LOW Voltage IOL = 2.0 mA 0.7 V

Output LOW Voltage IOL = 100 µA0.2V

Input HIGH Voltage 1.7 VDD + 0.3 V

Input LOW Voltage –0.3 0.7 V

Input Load Current GND ≤ VI ≤ V

Input Load Current TMS and TDI GND ≤ VI ≤ V

DDQ

DDQ

[12, 13]

–30 30 µA

–30 30 µA

Parameter Description Min. Max. Unit

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 100 ns

TCK Clock Frequency 10 MHz

TCK Clock HIGH 40 ns

TCK Clock LOW 40 ns

Set-up Times

t

TMSS

t

TDIS

t

CS

Notes:

10. All voltage referenced to ground.

11. Overshoot: V
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

12. t

CS

13. Test conditions are specified using the load in TAP AC test conditions. t

TMS Set-up to TCK Clock Rise 10 ns

TDI Set-up to TCK Clock Rise 10 ns

Capture Set-up to TCK Rise 10 ns

(AC) < V

IH

+ 1.5V for t < t

DD

/2; undershoot: VIL(AC) > –0.5V for t < t

TCYC

R/tF

= 1 ns.

TCYC

/2.

Document #: 38-05114 Rev. *C Page 14 of 29

CY7C1354B

CY7C1356B

TAP AC Switching Characteristics

Over the Operating Range (continued)

[12, 13]

Parameter Description Min. Max. Unit

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 10 ns

TDI Hold after Clock Rise 10 ns

Capture Hold after clock rise 10 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 20 ns

TCK Clock LOW to TDO Invalid 0 ns

TAP Timing and Test Conditions

TDO

1.5V for 3.3V V

1.25V for 2.5V V

= 50Ω

Z

0

(a)

Test Clock
TCK

GND

50Ω

C

L

DDQ

DDQ

= 20 pF

t

TMSS

ALL INPUT PULSES

3.0V

t

TCYC

1.5V

1.5 ns

V

SS

1.5 ns

TH

t

TL

t

TMSH

t

Test Mode Select
TMS

t

TDIS

t

TDIH

Test Data-In
TDI

Test Data-Out
TDO

t

TDOV

t

TDOX

Identification Register Definitions

Instruction Field CY7C1354B CY7C1356B Description

Revision Number (31:29) 001 001 Reserved for version number.

Cypress Device ID (28:12) 01010001000100110 01010001000010110 Reserved for future use.

Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.

ID Register Presence (0) 1 1 Indicate the presence of an ID register.

Document #: 38-05114 Rev. *C Page 15 of 29

CY7C1354B

CY7C1356B

Scan Register Sizes

Register Name Bit Size

Instruction 3

Bypass 1

ID 32

Boundary Scan 69

Identification Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.

Boundary Scan Exit Order (×36)

Bit # 119-Ball ID 165-Ball ID

1K4 B6

2H4 B7

3M4 A7

4F4 B8

5B4 A8

6G4 A9

7C3 B10

8B3 A10

9D6 C11

10 H7 E10

11 G6 F10

12 E6 G10

13 D7 D10

14 E7 D11

15 F6 E11

16 G7 F11

17 H6 G11

18 T7 H11

19 K7 J10

20 L6 K10

21 N6 L10

22 P7 M10

23 N7 J11

TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

operation does not affect SRAM operation.

Forces all SRAM output drivers to a High-Z state.

Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1-compliant.

Boundary Scan Exit Order (×36) (continued)

Bit # 119-Ball ID 165-Ball ID

24 M6 K11

25 L7 L11

26 K6 M11

27 P6 N11

28 T4 R11

29 A3 R10

30 C5 P10

31 B5 R9

32 A5 P9

33 C6 R8

34 A6 P8

35 P4 R6

36 N4 P6

37 R6 R4

38 T5 P4

39 T3 R3

40 R2 P3

41 R3 R1

42 P2 N1

43 P1 L2

44 L2 K2

45 K1 J2

46 N2 M2

Document #: 38-05114 Rev. *C Page 16 of 29

CY7C1354B

CY7C1356B

Boundary Scan Exit Order (×36) (continued)

Bit # 119-Ball ID 165-Ball ID

47 N1 M1

48 M2 L1

49 L1 K1

50 K2 J1

51 Not Bonded

(Preset to 1)

52 H1 G2

53 G2 F2

54 E2 E2

55 D1 D2

56 H2 G1

57 G1 F1

58 F2 E1

59 E1 D1

60 D2 C1

61 C2 B2

62 A2 A2

63 E4 A3

64 B2 B3

65 L3 B4

66 G3 A4

67 G5 A5

68 L5 B5

69 B6 A6

Not Bonded

(Preset to 1)

Boundary Scan Exit Order (×18)

Bit # 119-Ball ID 165-Ball ID

1K4 B6

2H4 B7

3M4 A7

4F4 B8

5B4 A8

6G4 A9

7C3 B10

8B3 A10

9T2 A11

10 Not Bonded

(Preset to 0)

11 Not Bonded

(Preset to 0)

12 Not Bonded

(Preset to 0)

13 D6 C11

14 E7 D11

15 F6 E11

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Boundary Scan Exit Order (×18) (continued)

Bit # 119-Ball ID 165-Ball ID

16 G7 F11

17 H6 G11

18 T7 H11

19 K7 J10

20 L6 K10

21 N6 L10

22 P7 M10

23 Not Bonded

(Preset to 0)

24 Not Bonded

(Preset to 0)

25 Not Bonded

(Preset to 0)

26 Not Bonded

(Preset to 0)

27 Not Bonded

(Preset to 0)

28 T6 R11

29 A3 R10

30 C5 P10

31 B5 R9

32 A5 P9

33 C6 R8

34 A6 P8

35 P4 R6

36 N4 P6

37 R6 R4

38 T5 P4

39 T3 R3

40 R2 P3

41 R3 R1

42 Not Bonded

(Preset to 0)

43 Not Bonded

(Preset to 0)

44 Not Bonded

(Preset to 0)

45 Not Bonded

(Preset to 0)

46 P2 N1

47 N1 M1

48 M2 L1

49 L1 K1

50 K2 J1

51 Not Bonded

(Preset to 1)

52 H1 G2

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 1)

Document #: 38-05114 Rev. *C Page 17 of 29

Boundary Scan Exit Order (×18) (continued)

Bit # 119-Ball ID 165-Ball ID

53 G2 F2

54 E2 E2

55 D1 D2

56 Not Bonded

(Preset to 0)

57 Not Bonded

(Preset to 0)

58 Not Bonded

(Preset to 0)

59 Not Bonded

(Preset to 0)

60 Not Bonded

(Preset to 0)

61 C2 B2

62 A2 A2

63 E4 A3

64 B2 B3

65 Not Bonded

(Preset to 0

66 G3 Not Bonded

67 Not Bonded

(Preset to 0

68 L5 B5

69 B6 A6

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

(Preset to 0)

A4

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 18 of 29

CY7C1354B

CY7C1356B

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

DC to Outputs in Three-State.............. –0.5V to V

DC Input Voltage ....................................–0.5V to V

Relative to GND........ –0.5V to +4.6V

DD

+ 0.5V

DDQ

+ 0.5V

DD

Electrical Characteristics Over the Operating Range

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%

Industrial –40°C to +85°C

[14, 15]

Ambient

Tem per atur e V

DD

V

DDQ

to V

Parameter Description Test Conditions Min. Max. Unit

V

V

V

V

V

V

I

DD

DDQ

OH

OL

IH

IL

X

Power Supply Voltage 3.135 3.6 V

I/O Supply Voltage V

Output HIGH Voltage VDD = Min., I

Output LOW Voltage VDD = Min., IOL= 8.0 mA, V

Input HIGH Voltage V

Input LOW Voltage

[14]

Input Load Current GND ≤ VI ≤ V

= 3.3V 3.135 V

DDQ

V

= 2.5V 2.375 2.625 V

DDQ

= −4.0 mA, V

OH

V

= Min., I

DD

V

= Min., IOL= 1.0 mA, V

DD

= 3.3V 2.0 VDD + 0.3V V

DDQ

V

= 2.5V 1.7 VDD + 0.3V V

DDQ

V

= 3.3V –0.3 0.8 V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

= −1.0 mA, V

OH

DDQ

= 3.3V 2.4 V

DDQ

= 2.5V 2.0 V

DDQ

= 3.3V 0.4 V

DDQ

= 2.5V 0.4 V

DDQ

–5 5 µA

DD

Input Current of MODE –30 30 µA

I

I

OZ

DD

Output Leakage Current GND ≤ VI ≤ V

VDD Operating Supply V

DD

f = f

= Max., I

= 1/t

MAX

Output Disabled –5 5 µA

DDQ,

OUT

CYC

= 0 mA,

4.4-ns cycle, 225 MHz 250 mA

5-ns cycle, 200 MHz 220 mA

6-ns cycle, 166 MHz 180 mA

I

SB1

I

SB2

I

SB3

I

SB4

Shaded areas contain advance information.

Notes:

14. Overshoot: V

15. T

Power-up

Automatic CE
Power-down
Current—TTL Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—TTL Inputs

IH(AC) < VDD +1.5V (Pulse width less than t

: Assumes a linear ramp from 0V to V

Max. VDD, Device Deselected,

≥ VIH or VIN ≤ VIL, f = f

V

IN

1/t

CYC

Max. V
V

IN

f = 0

, Device Deselected,

DD

≤ 0.3V or VIN > V

DDQ

− 0.3V,

Max. VDD, Device Deselected,
V

≤ 0.3V or VIN > V

IN

MAX

= 1/t

f = f

CYC

DDQ

− 0.3V,

Max. VDD, Device Deselected,

≥ VIH or VIN ≤ VIL, f = 0

V

IN

/2), undershoot: VIL(AC)> –2V (Pulse width less than t

CYC

(min.) within 200 ms. During this time VIH < VDD and V

DD

All speed grades 50 mA

=

MAX

All speed grades 35 mA

All speed grades 50 mA

All speed grades 40 mA

DDQ

< V

DD

CYC

.

/2).

DD

V

Document #: 38-05114 Rev. *C Page 19 of 29

CY7C1354B

CY7C1356B

Capacitance

[16]

Parameter Description Test Conditions BGA Max. fBGA Max. TQFP Max. Unit

C

Input Capacitance TA = 25°C, f = 1 MHz,

IN

C

CLK

C

I/O

Clock Input Capacitance 5 5 5 pF

Input/Output Capacitance 7 7 5 pF

V

DD

= 3.3V V

DDQ

= 2.5V

555pF

AC Test Loads and Waveforms

V

OUTPUT

= 50Ω

Z

0

(a) (b)

Thermal Resistance

R

= 1.5V/1.25V

V

L

[16]

= 50Ω

L

DDQ

DQ

5pF

INCLUDING

JIG AND

SCOPE

Parameters Description Test Conditions BGA Typ. fBGA Typ. TQFP Typ. Unit Notes

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA
/ JESD51.

Switching Characteristics Over the Operating Range

Parameter Description

[17]

t

Power

Clock

t

CYC

F

MAX

t

CH

t

CL

Output Times

t

CO

t

EOV

t

DOH

t

CHZ

t

CLZ

t

EOHZ

t

EOLZ

Shaded areas contain advance information.

Notes:

16. Tested initially and after any design or process changes that may affect these parameters.

17. This part has a voltage regulator internally; t

initiated.

, t

18. t

CHZ

CLZ

19. At any given voltage and temperature, t

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.

20. This parameter is sampled and not 100% tested.

21. Timing reference level is 1.5V when V

22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

VCC (typical) to the First Access Read or
Write

Clock Cycle Time 4.4 56ns

Maximum Operating Frequency 225 200 166 MHz

Clock HIGH 1.8 2.0 2.4 ns

Clock LOW 1.8 2.0 2.4 ns

Data Output Valid after CLK Rise 2.8 3.2 3.5 ns

OE LOW to Output Valid 2.8 3.2 3.5 ns

Data Output Hold after CLK Rise 1.25 1.5 1.5 ns

Clock to High-Z

Clock to Low-Z

HIGH to Output High-Z

OE

OE LOW to Output Low-Z

, t

, and t

EOLZ

EOHZ

[18, 19, 20]

[18, 19, 20]

[18, 19, 20]

[18, 19, 20]

is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be

power

are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

is less than t

EOHZ

= 3.3V and is 1.25V when V

DDQ

EOLZ

and t

R=1667/317Ω

R = 1538/351Ω

V

0V

DD

<

10%

1.0 ns

ALL INPUT PULSES

90%

1.5/1.25V

[16]

90%

(c)

25 27 25 °C/W 17

669°C/W 17

[21, 22]

-225 -200 -166

Min. Max. Min. Max. Min. Max.

1 11ms

1.25 2.81.53.21.53.5 ns

1.25 1.5 1.5 ns

2.8 3.2 3.5 ns

0 00ns

is less than t

CHZ

= 2.5V.

DDQ

to eliminate bus contention between SRAMs when sharing the same

CLZ

10%

< 1.0 ns

Unit

Document #: 38-05114 Rev. *C Page 20 of 29

CY7C1354B

CY7C1356B

Switching Characteristics Over the Operating Range (continued)

-225 -200 -166

Parameter Description

Set-up Times

t

AS

t

DS

t

CENS

t

WES

t

ALS

t

CES

t

AH

Address Set-up before CLK Rise 1.4 1.5 1.5 ns

Data Input Set-up before CLK Rise 1.4 1.5 1.5 ns

CEN Set-up before CLK Rise

WE, BWx Set-up before CLK Rise

ADV/LD Set-up before CLK Rise
Chip Select Set-up 1.4 1.5 1.5 ns

Address Hold after CLK Rise 0.4 0.5 0.5 ns

Hold Times

t

DH

t

CENH

t

WEH

t

ALH

t

CEH

Data Input Hold after CLK Rise 0.4 0.5 0.5 ns

CEN Hold after CLK Rise

WE, BWx Hold after CLK Rise

ADV/LD Hold after CLK Rise
Chip Select Hold after CLK Rise 0.4 0.5 0.5 ns

Min. Max. Min. Max. Min. Max.

1.4 1.5 1.5 ns

1.4 1.5 1.5 ns

1.4 1.5 1.5 ns

0.4 0.5 0.5 ns

0.4 0.5 0.5 ns

0.4 0.5 0.5 ns

[21, 22]

Unit

Document #: 38-05114 Rev. *C Page 21 of 29

123456789

10

A

CT

6)

Switching Waveforms

CY7C1354B

CY7C1356B

Read/WriteTiming

CLK

t

CENS

CEN

t

CES

CE

ADV/LD

WE

BW

X

DDRESS

t

AS

Data

Out (DQ)

OE

[23,24,25]

t

CENH

t

CEH

t

A1 A2

t

AH

CH

t

CYC

t

CL

A3

t

t

DS

DH

D(A1) D(A2) D(A5)Q(A4)Q(A3)

A4

t

t

D(A2+1)

CO

CLZ

t

DOH

A5 A6 A7

t

OEHZ

t

OEV

t

OELZ

t

CHZ

Q(A4+1)

t

DOH

Q(A

WRITE

D(A1)

WRITE

D(A2)

BURST
WRITE

D(A2+1)

READ
Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELE

DON’T CARE UNDEFINED

Document #: 38-05114 Rev. *C Page 22 of 29

Switching Waveforms (continued)

45678910

123

CY7C1354B

CY7C1356B

NOP,STALL AND DESELECT CYCLES

[23,24,26]

CLK

CEN

CE

ADV/LD

WE

BW

X

ADDRESS

A1

A2

Data

A3 A4

D(A1) Q(A2) Q(A3)

A5

D(A4)

t

CHZ

Q(A5)

In-Out (DQ)

D(A1)

READ
Q(A2)

STALL NOP READ

READ

Q(A3)

WRITE

D(A4)

STALLWRITE

Q(A5)

DESELECT CONTINUE

DESELECT

DON’T CARE UNDEFINED

Document #: 38-05114 Rev. *C Page 23 of 29

Switching Waveforms (continued)

A

CY7C1354B

CY7C1356B

CLK

I

SUPPLY

LL INPUTS

Outputs (Q)

[27,28]

ZZ

t

ZZ

t

ZZI

I

DDZZ

High-Z

DON’T CARE

being used to create a pause. A write is not performed during this cycle

t

ZZREC

t

RZZI

DESELECT or READ Only

ZZ Mode Timing

(except ZZ)

Note:

23. For this waveform ZZ is tied low.

24. When CE

25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.

26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN

27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

28. I/Os are in High-Z when exiting ZZ sleep mode..

is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Ordering Information

Speed

(MHz) Ordering Code

225

CY7C1354B-225AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial

CY7C1356B-225AC

CY7C1354B-225AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial

CY7C1356B-225AI

CY7C1354B-225BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial

CY7C1356B-225BGC

CY7C1354B-225BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Industrial

CY7C1356B-225BGI

CY7C1354B-225BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Commercial

CY7C1356B-225BZC

CY7C1354B-225BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Industrial

CY7C1356B-225BZI

Package

Name Package Type

Operating

Range

Document #: 38-05114 Rev. *C Page 24 of 29

CY7C1354B

CY7C1356B

Ordering Information

Speed

(MHz) Ordering Code

200 CY7C1354B-200AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial

CY7C1356B-200AC

CY7C1354B-200AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial

CY7C1356B-200AI

CY7C1354B-200BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial

CY7C1356B-200BGC

CY7C1354B-200BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Industrial

CY7C1356B-200BGI

CY7C1354B-200BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Commercial

CY7C1356B-200BZC

CY7C1354B-200BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Industrial

CY7C1356B-200BZI

166 CY7C1354B-166AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial

CY7C1356B-166AC

CY7C1354B-166AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial

CY7C1356B-166AI

CY7C1354B-166BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial

CY7C1356B-166BGC

CY7C1354B-166BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Industrial

CY7C1356B-166BGI

CY7C1354B-166BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Commercial

CY7C1356B-166BZC

CY7C1354B-166BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Industrial

CY7C1356B-166BZI

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Package

Name Package Type

Operating

Range

Document #: 38-05114 Rev. *C Page 25 of 29

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams

CY7C1354B

CY7C1356B

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

20.00±0.10

22.00±0.20

16.00±0.20

14.00±0.10

100

1

30

31 50

0° MIN.

R0.08MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

81

80

0.30±0.08

0.65
TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

DIMENSIONS ARE IN MILLIMETERS.

12°±1°

(8X)

SEATING PLANE

1.40±0.05

0.20 MAX.

1.60 MAX.

0.10

SEE DETAIL

A

51-85050-*A

Document #: 38-05114 Rev. *C Page 26 of 29

Package Diagrams (continued)

CY7C1354B

CY7C1356B

119-Lead BGA (14 x 22 x 2.4mm) BG119

51-85115-*B

Document #: 38-05114 Rev. *C Page 27 of 29

Package Diagrams (continued)

CY7C1354B

CY7C1356B

165-Ball FBGA (13 x 15 x 1.2 mm) BB165A

51-85122-*C

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05114 Rev. *C Page 28 of 29

CY7C1354B

CY7C1356B

Document History Page

Document Title: CY7C1354B/CY7C1356B 9-Mb (256K x 36/512K x 18) Pipelined SRAM with
NoBL™ Architecture
Document Number: 38-05114

REV. ECN No. Issue Date

** 117904 08/28/02 RCS New Data Sheet

*A 126207 08/27/03 DPM Removed Preliminary status

*B 205060 See ECN NJY Removed footnote 13 “

*C 230388 See ECN VBL Modified ID code

Orig. of
Change Description of Change

Removed 250-MHz Speed bin
Added 225-MHz speed bin
Increased T
Updated JTAG revision number and device depth

CO

, T

EOV

, T

CHZ

, T

for 200 MHz to 3.2 ns from 3.0 ns

EOHZ

Updated JTAG boundary scan orders
Added t
Changed footnotes ordering

specification

Power

Added Industrial operating range
Changed Capacitance table to have TQFP, BGA, and fBGA columns.

Removed footnote 14 “TA is the case temperature.”

Minimum voltage equals –2.0V for pulse durations of less than 20 ns.”

Changed footnote 15 from “Overshoot: V

(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <

V

IL

200 ms.

“to footnote 13“Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2),

undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).

Added footnote 14 “

During this time V

Added footnote 20 “

= 2.5V.”

V

DDQ

T

: Assumes a linear ramp from 0V to VDD (min.) within 200ms.

Power-up

IH < VDD and VDDQ < VDD. “

Timing reference level is 1.5V when V

(AC) < VDD + 1.5V for t < t

IH

“

Changed footnote 21 from “Test conditions shown in (a), (b) and (c) of AC Test Loads. “to
“

Test conditions shown in (a) of AC Test Loads unless otherwise noted. “

Updated ZZ Mode Electrical Characteristics.
Updated I
Modified functional block diagram.

SB1

and I

currents in Electrical Characteristics table.

SB3

Modified Truth Table and Write Cycle Descriptions.
Updated Ordering Information.

Changed balls B4 and A5 from BWd and BWb to NC and ball A4 from BW
to BWb for 165-ball FBGA package for CY7C1356B
Changed balls C11 from DQPb to DQPa and balls D11,E11,F11 and G11
from DQb to DQa for CY7C1356B.
Update Ordering Info section: changed BZC to BZI in Industrial part

/2; undershoot:

TCYC

= 3.3V and is 1.25V when

DDQ

c

Document #: 38-05114 Rev. *C Page 29 of 29