Datasheet CY7C1353-66AC, CY7C1353-50AC, CY7C1353-40AC Datasheet (Cypress Semiconductor)

1

353

CY7C1353

256Kx18 Flow-Through SRAM with NoBL™ Architecture

Features

Pin compatible and fu ncti onally equivalent to ZBT

•

devices MCM63Z819 and MT55L256L18F

• Supports 66-MHz bus operations with zero wait states
—Data is transferred on every clock

• Internally self-timed output b uffer control to eliminate

the need to use OE

• Registered inputs for Flow-Through operation

• Byte Write capability

• 256K x 18 common I/O architecture

• Single 3.3V power supply

• Fas t clock-to-o u tp u t times
—11.0 ns (for 66-MHz device)
—12. 0 ns (for 50-MHz device)
—14.0 ns (for 40-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchr onous self-timed writes

• Asynchr onous Output Enable

• JEDEC-standard 100 TQFP package

• Burst Capabili ty—linear or inte rleaved bur st order

• Low standby power

Logic Block Diagram

CLK

ADV/LD

[17:0]

CEN

CE
CE

CE
WE

[1:0]

18

CONTROL

1

2
3

and WRI TE

LOGIC

A

BWS

Mode

Functional Description

The CY7C1353 is a 3.3V 256K by 18 Synchronous­Flow-Through Burst SRAM designed specifically to support
unlimited true b ac k-to- back Read /Write operat ions wi thout t he
insertion of wait states. The CY7C1353 is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutiv e Read/Write operati ons with data being transf erred
on every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems
that require frequent Write -Read transition s.The CY7C1353 is
pin/functional ly compati ble t o ZBT SRAMs MCM63Z819 and
MT55L256L18F.

All synchronous input s pass through i nput regist er s controll ed
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN
pends operation and extends the previous clock cycle. Maxi­mum access delay from the clock rise is 9.0 ns (66-MHz de­vice).

Write operations are controlled by the four Byte Write Select
(BWS

) and a Write Enable (WE) input. All writes are con-

[1:0]

ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE

asynchronous Output Enable (OE
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

D

Data-In REG.

CE

Q

18

256KX18

MEMORY

18

ARRAY

) signal, which when deasserted sus-

, CE2, CE3) and an

1

) provide for easy bank se-

18

18

DQ

[15:0]

DP

[1:0]

OE

Selection Guide

7C1353-66 7C1353-50 7C1353-40

Maximum Access Time (ns) 11 12.0 14.0
Maximum Operati ng Current (mA) Commercial 250 mA 200 mA 175 mA
Maximum CMOS Standby Curr ent (mA) Commercial 5 mA 5 mA 5 mA
NoBL is a trademark of Cypress Semiconductor Corporation .

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 3, 1999

Pin Configuration

CY7C1353

100-Pin TQFP

V

DQ
DQ

V
DQ
DQ

DQ
DQ
V

DQ
DQ

V

NC
NC
NC

DDQ

V

SS

NC
NC

V

SS

DDQ

V

SS

V

DD

V

DD

V

SS

DDQ

V

SS

DP

NC

V

SS

DDQ

NC
NC
NC

NC

95

1

BWS

BWS0CE3VDDV

94

93

CY7C1353

92

91

90

SS

89

CLK

WE

CEN

88

87

OE

86

ADV/LD

85

NC

84

NC

83

82

A

81
80
79

78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A

17

NC
NC
V

DDQ

V

SS

NC
DP
DQ
DQ
V

SS

V

DDQ

DQ
DQ
V

SS

VSS
V

DD

VSS
DQ
DQ

V

DDQ

V

SS

DQ
DQ
NC
NC
V

SS

V

DDQ

NC
NC
NC

0
7
6

5
4

3
2

1
0

8A9

1CE2

A6

A7

CE

100

99

98

97

NC

96

1
2
3
4
5
6
7
8

8

9

9

10
11
12

10

13

11

14
15
16
17
18

12

19

13

20
21
22

14

23

15

24

1

25
26
27
28
29
30

31

32

33

34

A5A4A3A2A1A

MODE

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

0

DNU

DNU

SS

DD

V

V

DNU

DNU

10

A11A12A13A

A

14

16

15

A

A

2

CY7C1353

Pin Definitions

Pin Number Name I/O Description

80, 50−44,
81−82, 99–
100, 32−37

94, 93

88

85

89 CLK Input-Clock Clock Input. Used t o capt ure all synchr ono us inp uts to the device . CLK is qual ifi ed

98

97 CE

92

86

87

23−22,
19−18,
13−12, 9−8,
73−72,
69−68,
63−62, 59−58

24, 74 DP

31 Mode Input

15, 16, 41, 65, 91V

4, 11, 20, 27,
54, 61, 70, 77

5, 10, 14, 17,
21, 26, 40, 55,
60, 64,
66−67, 71,
76, 90

A

[17:0]

BWS

[1:0]

WE

AD V/LD

CE

1

2

CE

3

OE

CEN

DQ

[15:0]

[1:0]

DD

V

DDQ

V

SS

Input­Synchronous

Input­Synchronous

Input­Synchronous

Input­Synchronous

Address Inputs used to select one of the 262,144 addr ess locations. Sampled a t
the rising edge of the CLK.

Byte Write Select Inputs, active LOW. Qualified wi th WE to conduct writes to the
SRAM. Sampled on the risi ng edge of CLK. BWS
control s D Q

and DP1. See Write Cycle Description Table for details.

[15:8]

controls DQ

0

and DP0, BWS1

[7:0]

Write Enable Input, activ e LOW . Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be ass erted LOW to i nitiate a write sequence.

Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN

is asserted LOW) the internal b urst counter is
advanc ed. When LOW , a new address can be loaded into the de vice f or an access.
After being deselected, ADV/LD

should be driven LOW in order to load a new

address.

Input­Synchronous

Input­Synchronous

Input­Synchronous

Input­Asynchronous

with CEN
Chip Enable 1 Inpu t, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 2 Inpu t, acti ve HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 3 Inpu t, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE
Output Enab le, active LO W . Combined with the synchro nous logi c bloc k insi de t he

device t o control the direction of t he I/O pins. When LO W , the I/O pins are al lowed

. CLK is only recogniz ed if CEN is active LOW.

, and CE3 to select/deselect the device.

2

and CE3 to select/desel ect the devi ce.

1

and CE2 to select/deselect the device.

to behav e as out puts . When de asserted HIGH, I/ O pins ar e three- state d, an d act
as input data pins. OE

is masked during the data portion of a write seq uence,
during the first clock wh en emerging fr om a deselec ted state, when the de vice has
been deselected.

Input­Synchronous

Clock Enable Input, acti ve LOW. When ass erted LOW the Clock signal i s recog­nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN

does not deselect the device, CEN can be used to extend the

prev ious cycle when required.

I/O­Synchronous

Bidirectiona l Data I/O Line s. As inputs, they f eed into an on- chip data regi ster that
is triggered by t he rising edge of CLK. As outp uts, they deliv e r the data containe d
in the memory location specified by A
read cycle. The direction of the pins is controlled by OE
logic. When OE
DQ

are placed in a three-state condition. The outputs are automatically

[15:0]

is asserted LOW, the pins can behave as outputs. When HIGH,

during the previous clock rise of the

[17:0]

and the internal control

three-stated d uring the data po rtion of a write sequence , during the fi rst clock when
emerging from a de sel ected st ate , and when t he device is des electe d, regar dless

I/O­Synchronous

of the state of OE
Bidirectional Data Parity I/O Li nes. Functionall y, these signals are identical to

DQ
by BWS

. During write sequences, DP0 is controlled by BWS0 and DP1 is controlled

[15:0]

.

1

.

Mode Input. Selec ts the burst order of the de vice. Tied HIGH sel ects the interleav ed

Strap pin

burst order. Pull ed LOW selects the linear burst order. MODE shou ld not change
states during operation. When left floating MODE will default HIGH, to an inter­leaved burst or d er.

Po wer Supply Power supply i nputs t o the cor e of t he dev ic e. Sh oul d be con nect ed to 3.3 V powe r

supply.

I/O Power

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

Supply
Ground Ground for the device. Should be connected to gro und of the system.

3

CY7C1353

Pin Definitions

(continued)

Pin Number Name I/O Description

1−3, 6−7, 25,

NC - No Connects. These pins are not connected to the internal device.
28−30,51−53,
56−57, 75,
78−79, 95−96

83, 84 NC - No Connects. Res erved for a ddress inputs f or depth e xpansion. Pin 83 wi ll be used

for 512K depth and pin 84 will be used for 1-Mb depth.

38, 39, 42, 43 DNU - Do Not Use Pins. These pins should be l eft floating or tied to VSS.

Introduction

must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Acces s section abov e.

Functional Overview

The CY7C1353 is a Synchronous Flow-Through Burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal i s not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN
rise (t

) is 9.0 ns (66-MHz device).

CD V

. Maximum acce ss dela y f rom the clock

Accesses can be initiated by asserting all three Chip Enables
(CE

, CE2, CE3) active at the rising edge of the clock. If clock

1

enable (CEN

) is activ e LO W and AD V/LD is asserted LO W , th e
address presented to the device will be latched. The access
can either be a r ead or write operation, depending on the sta­tus of the Write Enabl e (WE

). BWS

can be used t o conduct

[1:0]

byte write operations.
Write operations are qualified by the Write Enable (WE

). All
writes are s implifi ed with on-chi p synchr onou s s elf-ti med writ e
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

, CE2, CE3) and an

1

) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD

should be driven LOW once the devic e has been de-

selected in order to load a ne w addres s f or t he nex t operat i on.

Single Read Accesses

A read access is initiated when the following conditions are
satisfi ed at cl ock rise: (1) CEN
and CE
signal WE

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and 4) ADV/LD is assert ed
LOW. The address present ed to t he ad dress i nputs ( A
latched into the Address Register and present ed to t he mem-

is asserted LOW, (2) CE1, CE2,

) is

[17:0]

ory core and control logic. The con trol logic determines that a
read access is in progress and allows the requested data to
propagate to the output bu ffer s. The da ta is a vail able wi thin 9. 0
ns (66-MHz device) provided OE

is active LOW. After the first
clock of the read access the output buffers are controlled by
OE

and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one o f the chip enab le s ignals, i ts output will be three-state d
immediately.

Burst Read Accesses

The CY7C1353 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD

The sequence o f the b urst coun ter is determined b y the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enable inputs or WE

will increment t he internal b urs t counter regardl ess of

. WE is latched at the
beginning of a burst cycle. Theref ore , the ty pe of acces s (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are
satisfied at cl ock rise: (1) CEN
and CE
is asserted LOW. The address presented to A

are ALL asserted active, and (3) the write signal WE

3

into the Address Register. The write signals are latched into

is asserted LO W, (2) CE1, CE2,

is loaded

[17:0]

the Control Logic block. The data lines are automatically
three-stated r egardless of t he state of the OE
allows the external logic to present the data on DQ
DP

.

[1:0]

On the next clock rise the data presented to DQ
DP

(or a subset for byte write operations, see Write Cycle

[1:0]

Description table for details) inputs is latched into the device

input signal. This

and

[15:0]

and

[15:0]

and the write is complete. Additional accesses
(Read/Write/Deselect) can be initiated on this cycle.

The data written during the Write operation is controlled by
BWS
ity that is described in the Write Cycle Description Table. As­serting the Write Enable input (WE
Write Selec t (BWS
desired by tes. Bytes not selec ted during a byte write oper ation

signals. The CY7C1353 pro vides b y te write c apabil -

[1:0]

) with the selected Byte

) input will selec tively wr ite to on ly the

[1:0]

will remain unaltered. A synchronous self-timed write mecha­nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim­ple byte write opera ti ons.

Because the CY7C1353 is a common I/O device, data should
not be driven in to t he device whi le t he outputs are active. The
Output Enable (OE
ing data to the DQ
three-state t he output driv er s. As a sa f e ty pr ecauti on, DQ
and DP
tion of a write cycle, regardless of the state of OE

.are automat ical ly th ree-st ated d urin g the da ta por -

[1:0]

) can be deasserted HIGH before present-

[15:0]

and DP

inputs. Doing so will

[1:0]

[15:0]

.

Burst Write Accesses

The CY7C1353 ha s an On-Chip Burst Counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial ad-

4

CY7C1353

dress, as described in the Single Write Access section abo ve.
When ADV/LD
the chip enables (CE
nored and the burst counter is incremented. The correct

Cycle Description Truth Table

Operation

is driven HIGH on the subsequent clock rise,

, CE2, and CE3) and WE inputs are ig-

1

[1, 2, 3, 4, 5, 6]

Address

used CE CEN

ADV/

LD

BWS
in order to write the correct bytes of data.

WE BWSxCLK Comments

inputs must be driven i n each cyc le of the b urst write

[1:0]

Deselected External 1 0 L X X L-H I /Os thr ee-sta te f oll owing next rec-

ognized clock.

Suspend - X 1 X X X L-H Clock Ignored, all operations sus-

pended.
Begin Read External 0 0 0 1 X L-H Address Latched.
Begin Write External 0 0 0 0 Val id L-H Address Latched, da ta presented

two va li d clocks lat er.
Burst READ

Operation

Internal X 0 1 X X L-H Burst Read Operation . Previous

access was a Read operatio n. Ad-

dresses incremented internally in

conjuncti on with the state o f Mode.
Burst WR IT E

Operation

Internal X 0 1 X Valid L-H Burst Write Operation. Previous

access w as a W rite opera tion. Ad-

dresses incremented internally in

conjuncti on with the state of Mode.

Bytes written are determined by

Note:

1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW, CE
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE

3. The DQ and DP pins are controlled by the current cycle and the OE

4. CEN=1 inserts wait states .

5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

6. OE assumed LOW.

and BWS

. See Write Cycle Description table for details.

[1:0]

stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =

signal.

BWS

[1:0]

.

5

CY7C1353

Interleaved Burst Sequence

First

Address

Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Write Cycle Description

Second

Address

Third

Address

[1, 2]

Function

Fourth

Address

Linear Burst Sequence

First

Address

Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

WE

Third

Address

BWS

Fourth

Address

1

BWS

0

Read 1XX
Write - No bytes written 0 1 1
Write Byte 0-(DQ
Write Byte 1-(DQ

and DP0) 010

[7:0]

and DP1) 001

[15:8]

Write All Bytes 0 0 0

Maximum Ratings

(Abov e which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .....................................−65°C to +150°C

Ambient Temperature with

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage .................. ............ ............ >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current............ .......... .......... .. .......... ........ >200 mA

Operating Range

Power Applied..................................................−55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outp uts

in High Z State

[7]

DC Input Voltage

Note:

7. Minimum voltage equals

8. T

is the case temperature.

A

Relative to GND......... −0.5V to +4.6V

DD

.....................................−0.5V to V

[7]

..................................−0.5V to V

2.0V for pulse duration less than 20 ns.

−

DDQ
DDQ

+ 0.5V
+ 0.5V

Range

Com’l 0°C to +70°C 3.3V ±5%

Ambient

T em perature

[8]

VDD/V

DDQ

6

CY7C1353

Electrical Characteristics

Over the Op erating Range

Parameter Description T est Conditions Min. Max. Unit

V
V
V
V
V
V
I

I

I

X

OZ

CC

DD

DDQ
OH
OL

IH

IL

Power Supply Voltage 3.135 3.465 V
I/O Supply Voltage 3.135 3.465 V

[9]

[9]

2.4 V

0.4 V

Output HIGH Volt age VDD = Min., I

= –4.0 mA

OH

Out p ut LOW Voltage VDD = Min., IOL = 8.0 mA
Input HIGH Volt a g e 2.0 VDD +0.3V V
Input LOW Voltage

[7]

Input Load Current GND ≤ VI ≤ V
Input Current of MODE
Output Leakage

GND ≤ VI ≤ V

Current
VDD Operating Suppl y V

DD

f = f

= Max., I

= 1/t

MAX

DDQ

Output Disabled

DDQ,

= 0 mA,

OUT

CYC

15-ns cycle, 66 MHz 250 mA
20-ns cycle, 50 MHz 200 mA

−0.3

−5

−30

−5

0.8 V
5 mA

30 mA

5 mA

25-ns cycle, 40 MHz 175 mA

I

SB1

Automatic CE
Power-Down
Current-TTL Inputs

Max. VDD, Device D eselected,
V

≥ VIH or VIN ≤ V

IN

f = f

MAX

= 1/t

IL

CYC

15-ns cycle, 66 MHz 60 mA
20-ns cycle, 50 MHz 40 mA
25-ns cycle, 40 MHz 30 mA

I

SB2

I

SB3

Automatic CE
Power-Down
Current-CMOS Inputs

Automatic CE
Power-Down
Current-CMOS Inputs

Max. VDD, Device D eselected,
V

≤ 0.3V or VIN > V

IN

f = 0

DDQ

−0.3V,

Max. VDD, Device D eselec ted, or
V

≤ 0.3V or VIN > V

IN

f = f

MAX

= 1/t

CYC

DDQ

− 0.3V

All speed grades 5 mA

15-ns cycle, 66 MHz 50 mA
20-ns cycle, 50 MHz 40 mA
25-ns cycle, 40 MHz 30 mA

Note:

9. The load used for V

and VOL testing is shown in figure (b) of the A/C test conditions.

OH

7

Capacitance

Parameter Description T est Conditions Max. Unit

CY7C1353

[10]

CIN Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V

C
C

CLK
I/O

Clock Input Capacitance 4 pF
Input/Output Capacitance 4 pF

V

DD
DDQ

= 3.3V

4 pF

AC Test Loads and Waveforms

R=317

OUTPUT

3.3V

Z

=50

Ω

0

V

L

R

= 1.5V

L

(a) (b)

=50

OUTPUT

Ω

INCLUDING

JIG AND

SCOPE

5pF

Ω

R=351

1353-2

ALL INPUT PULSES

3.0V

Ω

GND

[11]

1353-3

Thermal Resistance

Description T est Conditions Symbol TQFP Ty p. Units Notes

Thermal Resistance
(Junction to Ambient)

Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board.

Thermal Resistance
(Junction to Case)

Note:

10. Tested initially and after any design or process change that may affect these parameters.

11. Unless otherwise noted, test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading shown in (a) of AC Test Loads.

Θ

JA

Θ

JC

28 °C/W 10

4 °C/W 10

8

CY7C1353

Switching C h aracteri sti cs

Over the Operating Range

[11, 12, 13]

–66 –50 –40

Param e t e r Description Min. Max. Min. Max. Min. Max. Unit

t

CYC

t

CH

t

CL

t

AS

t

AH

t

CO

t

DOH

t

CENS

t

CENH

t

WES

t

WEH

t

ALS

t

ALH

t

DS

t

DH

t

CES

t

CEH

t

CHZ

t

CLZ

t

EOHZ

t

EOLZ

t

EOV

Note:

12. t

CHZ

voltage.

13. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worstcase user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

14. This parameter is sampled and not 100% tested.

Clock Cycle Time 15.0 20.0 25.0 ns
Clock HIGH 5.0 6.0 7.0 ns
Clock LO W 5.0 6.0 7.0 ns
Address Set-Up Bef ore CLK Rise 2.0 2.0 2.5 ns
Address Hold After CLK Rise 0.5 1.0 1.0 ns
Data Output Valid After CLK Rise 11 12.0 14.0 ns
Data Output Hold After CLK Rise 1.5 1.5 1.5 ns
CEN Set-Up Before CLK Rise 2.0 2.0 2.5 ns
CEN Hold After CLK Rise 0.5 1.0 1.0 ns
WE, BWS
WE, BWS

Set-Up Before CLK Rise 2.0 2.0 2.5 ns

[1:0]

Hold After CLK Rise 0.5 1.0 1.0 ns

[1:0]

ADV/LD Set-Up Before CLK Rise 2.0 2.0 2.5 ns
ADV/LD Hold after CLK Rise 0.5 1.0 1.0 ns
Data Input Set-Up Bef ore CLK Rise 1.7 2.0 2.5 ns
Data Input Hold After CLK Rise 0.5 1.0 1.0 ns
Chip Select Set-Up 2.0 2.0 2.5 ns
Chip Select Hold After CLK Rise 0.5 1.0 1.0 ns
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
OE LOW to Output Valid

, t

, t

, t

CLZ

OEV

EOLZ

, and t

[10,12,13,14]

[10,12,13,14]

[10,12,13,14]

[10,12,13,14]

[12]

are specified with A/C test conditions shown in part (a) of AC Test Loads. T ransition is measured ± 200 mV from steady-state

EOHZ

is less than t

EOHZ

EOLZ

and t

is less than t

CHZ

2.0 2.0 2.0 ns

CLZ

5.0 5.0 5.0 ns

6.0 7.0 8.0 ns

0 0 0 ns

6.0 7.0 8.0 ns

to eliminate bus contention between SRAMs when sharing the same

9

CY7C1353

Switching Waveforms

Read/Write Waveforms

Read

CLK

t

RA1

t

WH

CENH

t

AH

t

CENS

CEN

t

AS

ADDRESS

WE

t

WS

WA2

Write

Read

DESELECT

t

t

CL

CH

RA3 RA4

Read

t

CYC

WA5

t

CENS

RA7

Read

Ignore

t

CENH

DESELECT

DESELECT

Write

Read

RA6

t

CES

t

CEH

CE

t

t

Data­In/Out

Device
originally

deselected

t

CLZ

t

CDV

t

DOH

Q1

Out

D2

In

Q3

Out

CHZ

WE is the combination of WE & BWSx to define a Write Cycle (see Write Cycle Description Table).
CE is the combination of CE1, CE2, and CE3. All Chip Selects need to be active in order to select

the device. Any Chip Select can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.

= DON’T CARE

DOH

Q4

Out

D5

In

= UNDEFINED

Q6
Out

Q7

Out

t

CHZ

10

CY7C1353

Switching Waveforms

Burst Sequences

Begin Read

CLK

RA1

t

WH

t

ALH

t

ALS

ADV/LD

ADDRESS

WE

t

WS

Burst Read

Burst Read

t

CH

Burst Read

t

CL

t

WS

t

AS

Begin Write

WA2

t

t

AH

WH

t

CYC

Burst Write

Burst Write

Burst Write

Begin Read

RA3

Burst Read

Burst Read

BWS

[1:0]

t

t

CES

CEH

CE

t

CLZ

D2+3

In

held

input signals.

[1:0]

Data­In/Out

Device

t

CLZ

t

CDV

t

DOH

Q1

Out

1a

t

CDV

Q1+1

Out

Q1+2

Out

Q1+3

Out

t

CHZ

t

DH

D2

In

t

DS

D2+1

In

D2+2

In

originally deselec te d

The combination of WE & BWS

defines a write cycle (see Write Cycle Description Table).

[1:0]

CE is the combination of CE1, CE2, and CE3. All Chip Enables need to be act ive in order to select
the device. Any Chip Enable can deselect the devic e. RAx stands for Read Address X, WAx stands for

Write Address X, Dx stands for Data-in for locati on X, Qx stands for Data-out for l ocation X. CEN
LOW. During burst writes, byte writes can be cond ucted by asserting the appr opriate BWS

Burst order determi ned by the state of the MODE input. CEN

held LOW. OE held L O W .

Q3
Out

Q3+1

Out

= DON’T CARE

= UNDEFINED

11

CY7C1353

Switching Waveforms

OE Timing

OE

t

EOV

EOLZ

I/O’s

t

EOHZ

Three-state

t

Ordering Information

Speed

(MHz)

66 CY7C1353-66A C A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial
50 CY7C1353-50A C A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial
40 CY7C1353-40A C A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial

Ordering Code

Package

Name

Pack age Type

Operating

Range

Document #: 38-00689-B

12

Package D iagra m

CY7C1353

100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A101

51-85050-A

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any l icense under patent or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.