Datasheet CY7C1333-66AC, CY7C1333-50AC Datasheet (Cypress Semiconductor)

CY7C1333

64Kx32 Flow-Thru SRAM with NoBL™ Architecture

Features

• Pin compatible and functionally equivalent to ZBT™
device MT55L64 L32F

• Supports 66-MHz bus oper ations with zero wait states

—D ata is transferred on every cl ock

• Internally self-timed outpu t buffer control to eliminate
the need to use OE

• Registere d input s for Flow-Through operation

• Byte Write capabi lity

• 64K x 32 common I/O arc hitecture

• Single 3.3V power supply

• Fast clock-to-output times

—12.0 ns (for 66- MHz device)
—14.0 ns (for 50- MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100-pin TQFP package

• Burst Capabi li ty—linear or interleaved burst order

• Low (16.5 mW) standby power

Logic Block Diagram

CLK

ADV/LD

[15:0]

CEN

CE
CE

CE

WE

[3:0]

Mode

16

CONTROL

1

2
3

and WRIT E

LOGIC

A

BWS

Functional Description

The CY7C1333 is a 3.3V, 64K by 32 Synchronous
Flow-Through Burst SRAM designed specifically to support
unlimited true bac k-to- back Read /Write operat ions wi thout the
insertion of wait states. The CY7C1333 is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to en­able consecut ive Read/ Write operat ions with data be ing trans ­ferred on e v ery c lock c ycle. Thi s f eat ure d ra matical ly improves
the throughput of data through the SRAM, especially in sys­tems that require frequent Write-Read transitions. The
CY7C1333 is pin/functionally compatible to ZBT SRAM
MT55L64L32F.

All synchronous input s pass through i nput regi ster s control led
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN
pends operation and extends the previous clock cycle. Maxi­mum access delay from the clock rise is 12.0 ns (66-MHz
device).

Write operations are controlled by the four Byte Write Select
(BWS

) and a Write Enable (WE) input. All writes are con-

[0:3]

ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE

asynchronous Output Enable (OE
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

D

Data-In REG.

CE

Q

32

64KX

32

MEMORY

16

ARRAY

) signal, which, when deass erted, sus-

, CE2, CE3) and an

1

) provide for easy bank se-

32

32

DQ

32

[31:0]

OE

Selection G uide

7C1333-66 7C1333-50

Maximum Access Time (ns) 12.0 14.0
Maximum Operating Curr ent (mA) Commercial 310 260
Maximum CMOS Standby Current (mA) Commercial 5.0 5.0

No Bus Latency and NoBL are tra demarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integ rated Devi ce Technology.

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 4, 1999

Pin Configuration

CY7C1333

100-Pin TQFP

DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V

DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ

NC

DDQ
SSQ

SSQ
DDQ

SSQ

V

DD

V

DD

V

DDQ

SSQ

SSQ

DDQ

NC

SS

A6A7CE1CE2BWS3BWS2BWS1BWS0CE3VDDVSSCLK

9998979695949392919089

100

WE

CEN

OE

ADV/LD

NC

88

87868584838281

NC

1

16
17

2
3
4
5

18
19
20
21

6
7
8
9
10
11

22
23

12
13

CY7C1333

14
15
16
17

24
25

18
19
20
21

26
27
28
29

22
23
24
25
26
27

30
31

28
29
30

A8A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

9

NC
DQ

15

DQ

14

V

DDQ

V

SSQ

DQ

13

DQ

12

DQ

11

DQ

10

V

SSQ

V

DDQ

DQ

9

DQ

8

V

SS

VSS
V

DD

NC
DQ

7

DQ

6

V

DDQ

V

SSQ

DQ

5

DQ

4

DQ

3

DQ

2

V

SSQ

V

DDQ

DQ

1

DQ

0

NC

31

32

3334353637

A5A4A3A2A1A

MODE

38

39

4041424344

0

DNU

DNU

SS

DD

V

V

DNU

4546474849

10A11A12A13A14

A

DNU

50

15

NC

A

2

CY7C1333

Pin Definitions

Pin Number Name I/O Description

49−44,
81–82, 99,
100, 32–37

96–93 BWS

88 WE Input-

85 ADV/LD Input-

89 CLK Input-Clock Clock Input . Used to capture all synchronous inputs to the devi ce. CLK is qual ified

98 CE

97 CE

92 CE

86 OE Input-

87 CEN Input-

29–28,25–22,
19–18,13–12,
9–6, 3–2,
79–78,75–72,
69–68,63–62
59–56,53–52

31 Mode Input

15, 16, 41, 65, 91V

17, 40, 67, 90 V
4, 11, 20, 27,

54, 61, 70, 77
5, 10, 14, 21,

26, 55, 60, 66,
71, 76

64 NC - No Connect. Reserved for drive strength control input .

A

DQ

V

V

[15:0]

1

2

3

[31:0]

DD

SS
DDQ

SSQ

[3:0]

Input­Synchronous

Input­Synchronous

Address Input s used to sel ect one of the 65, 536 address locati ons. Sam pled at the
rising edge of the CLK.

Byte Write Select Input s, active LOW. Qualified with WE to con duct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
DQ

, BWS2 controls DQ

[15:8]

, BWS0 controls DQ

[23:16]

controls DQ

0

[31:24]

, BWS1 controls

[7:0]

.

Write Enable Input, active LO W . Sampled on the rising edge of CLK if CEN is active

Synchronous

LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to adv ance the on-chip address counter or load a new

Synchronous

address. When HIGH (and CEN

is asserted LOW) the internal b urst counter is
advance d. When LOW , a new address can be loaded into the de vice f or an access.
After being deselected, AD V/LD

should be driven LOW in order to load a new

address.

Input­Synchronous

Input­Synchronous

Input­Synchronous

with CEN
Chip Enable 1 Input, active LO W. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 3 Input, active LO W. Sampled on the rising edge of CLK. Used in

conjunction with CE

. CLK is only recogniz ed if CEN is active LOW.

and CE3 to select/deselect the device.

2

and CE3 to select/deselect the device.

1

and CE2 to select/dese lect the device.

1

Output Enabl e, acti ve LO W . Combin ed with the s ynchronous l ogic bl ock insi de the

Asynchronous

device t o c ontrol the di rect ion of the I /O p ins. When LO W , t he I/ O pins ar e all o wed
to behave as outputs. When deasserted HIGH, I/O pins are three-st ated, and act
as input data pins. OE

is masked during the data portion of a write sequence,
during the first clock wh en emerging fr om a deselecte d state, when the de vice has
been deselected.

Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-

Synchronous

nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
the deasserting CEN

does not deselect the device, CEN can be used to extend

the previous cycle when required.

I/O­Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by t he rising edge of CLK. As output s, the y deliv er the data conta ined
in the memory location specified by A
read cycle. The direction of the pins is controlled by OE
logic. When OE
DQ
three-stated d uring the data po rtion of a write sequence, during the firs t clock when

are placed in a three-state condition. The outputs are automat ically

[31:0]

is asserted LOW, the pins ca n behave as outputs. When HIGH,

during the previous clock rise of the

[15:0]

and the internal control

emerging from a de sel ected st ate , and when the device i s desele cted, r egardl ess
of the state of OE

.

Mode Input. Selec ts the burst order of the de vice. Tied HIGH select s the interleave d

Strap pin

burst order. Pulled LOW selects the linear burst order. MODE should not change
states during ope ration. When left float ing Mode will default HIGH, t o an interleaved
burst order.

Power Supply Po wer s uppl y inp uts t o the cor e of t he de vice . Sho uld be conn ect ed to 3.3 V po wer

supply.

Ground Ground for the core of the de vice. Should be conne cted to ground of the system.
I/O Power

Power supply for the I/O circui try. Should be connected to a 3.3V power supply.

Supply
I/O Ground Ground for the I/O circuitry. Should be connected to ground of the syst em .

3

CY7C1333

Pin Definitions

(continued)

Pin Number Name I/O Description

50, 83, 84 NC - No connects. Reserv ed for address inputs for dep th expansion. Pins 50, 83, and

84 will be used for 128K, 256K, and 512K depths respectively.

1, 30, 51, 80 NC - No connects. Reserved f or p arity I/O s ign als on x36 de vic es. Thes e input s are not

connected to the device.

38, 39, 42, 43 DNU - Do Not Use pins. These pi ns should be left floating or tied to VSS.

Introduction

input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both

Functional Overview

The CY7C1333 is a Synchronous Flow-Through Burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signa l i s not recogni zed and
all internal states are maintained. All synchronous operations
are qualified wi th CEN
rise (t

) is 12.0 ns (66-MHz device).

CDV

. Maximum access del a y from the clock

Accesses can be initiated by asserting all three chip enables
(CE

, CE2, CE3) activ e at the rising edge of t he clock. If Clock

1

Enable (CEN

) is active LOW and ADV/ LD is asserted LOW , the
address presented to the device will be latched. The access
can either be a read or write operati on, depending on t he sta­tus of the Write Enabl e (WE
byte write operat ions.

Write operations are qualified by the Write Enable (WE

). BWS

can be used to conduct

[3:0]

). All
writes are simpl ifi ed wit h on- chi p synchr onou s self -tim ed write
circuitry.

Three synchronous Chip enables (CE
asynchronous output enable (OE
ADV/LD

should be driven LOW once the device has been de-

, CE2, CE3) and an

1

) simplify depth expansion.

selected in order to load a ne w addr ess f or the ne x t operat ion.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and 4) ADV/LD is assert ed
LOW. The address presented to the address inputs (A
is latched into the Address Register and presented to the

is asserted LOW, (2) CE1, CE2,

0–A15

memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the output buffers. The data is available
within 12.0 ns (66-MHz device) provided OE

is active LOW.
After the first clock of the read access the output buffers are
controlled by OE

and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. On the subsequent clock, another operation
(Read/Write/De select) can be initi ated. When the SRAM is de­selected at clock rise by one of the chip enable signals, its
output will be three-stated immediately.

burst counters use A
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD

will increment the internal burst counter rega rdless of

the state of chip enable inputs or WE

and A1 in the burst sequence, and will

0

. WE is latched at the
beginning of a burst cycle. Theref ore , the type of acces s (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

A write access is initiated when the following conditions are
satisfied at cl oc k rise : (1) CEN
and CE
is asserted LOW. The address presented to A0–A15 is loaded

are ALL asserted active, and (3) the write signal WE

3

is asserted LO W, (2) CE1, CE2,

into the Address Register. The write signals are latched into
the Control Logic block. The data lines are automatically
three-stated r egardless of the s tate of the OE

input signal. This

allows the e xternal logic to present the data on DQ
On the nex t cloc k ris e the dat a present ed to DQ

–DQ31 inputs

0

(or a subset for b yte write op erations , see W rite Cycle Des crip­tion table for details) is latche d into the de vice and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.

The data written during the Write operation is controlled by
BWS
ity that is described in the Write Cycle Description table. As­serting the Write Enable input (WE
Write Selec t (BW S
desired byte s. Bytes not selected during a byt e write opera tion

signals. The CY7C1333 provides byte write capabil-

[3:0]

) with the selected Byte

) input will sele ctively wr ite to on ly the

[3:0]

will remain unaltered. A Synchr onous self-timed write mecha­nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-

)

ple byte write operations.
Because the CY7C1333 is a common I/O device, d ata should

not be driven into the devic e while the outputs ar e active. The
Output Enable ( O E
ing d a ta to the D Q
output drivers. As a safety precaution, DQ
matically three-stated during the data portion of a write cycle,
regardless of the state of OE

) can be deasserted HIGH before present­–DQ31 inputs. Doing so wil l three- st ate the

0

–DQ31 are auto-

0

.

Burst Write Accesses

The CY7C1333 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to

–DQ31.

0

four Write operations without reasserting the address inputs.

Burst Read Accesses

The CY7C1333 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as de scribed in t he Singl e Read Ac cess secti on abov e.
The sequenc e of the b urst c ounter is determined b y the MODE

ADV/LD

must be driven LOW in order to load the initial ad­dress, as described in the Single Write Accesses section
above . When ADV/L D
rise, the Chip Enables (CE
ignored and the burst counter is incremented. The correct
BWS
in order to write the correct bytes of data.

inputs must be driven i n each cyc le of the burs t write

[3:0]

is drive n HIGH on the subseque nt cloc k

, CE2, and CE3) and WE inputs ar e

1

4

CY7C1333

.

Cycle Description Truth Table

Address

Operation

Used CE CEN

[1, 2, 3, 4, 5, 6]

ADV/

LD

WE BWS

CLK Comments

x

Deselected External 1 0 L X X L-H I/Os three-stated
Suspend - X 1 X X X L-H Clock ignored, all operations sus-

pended
Begin Read External 0 0 0 1 X L-H Address latched
Begin Write External 0 0 0 0 Valid L-H Address latched, data present ed

one valid clock l a t e r
Burst Read

Operation

Internal X 0 1 X X L-H Burst Read operation. Previous ac-

cess was a Read oper ation. Ad-

dresses incremented internally in

conjuncti on wit h the state of Mode.
Burst Write

Operation

Internal X 0 1 X Valid L-H Burst Write operation. Previous ac-

cess was a Write operation. Ad-

dresses incremented internally in

conjuncti on wit h the state of Mode.

Bytes written are determined by

BWS

[3:0]

Interleave d B u rst S eq u en ce

First

Address

Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Second

Address

Third

Address

Fourth

Address

Linear Burst Sequence

First

Address

Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

Third

Address

Fourth

Address

Notes:

1. X=”Don’t Care”, 1=Logic HIGH, 0=Logic LOW, CE

2. Write is defined by WE

3. The DQ pins are controlled by the current cycle and the OE

4. CEN=1 inserts wait states.

5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

6. OE assumed LOW.

= Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

BWS

x

and BWS

. See Write Cycle Description table for details.

[3:0]

stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active,

signal.

5

CY7C1333

Write Cycle D escriptio n

Function WE BWS

[7, 8]

3

BWS

2

BWS

1

BWS

0

Read 1 X X X X
Write - N o byte s wr it te n 0 1 1 1 1
Write Byte 0 - DQ
Write Byte 1 - DQ

[7:0]
[15:8]

01110

01101
Write Bytes 1, 0 01100
Write Byte 2 - DQ

[23:16]

01011
Write Bytes 2, 0 01010
Write Bytes 2, 1 01001
Write Bytes 2, 1, 0 0 1 0 0 0
Write Byte 3 - DQ

[31:24]

00111
Write Bytes 3, 0 00110
Write Bytes 3, 1 00101
Write Bytes 3, 1, 0 0 0 1 0 0
Write Bytes 3, 2 00011
Write Bytes 3, 2, 0 0 0 0 1 0
Write Bytes 3, 2, 1 0 0 0 0 1
Write All B yt e s 0 0 0 0 0

Notes:

7. X=”Don’t Care”, 1=Logic HIGH, 0=Logic LOW.

8. Write is initiated by the combination of WE
I/Os are three-stated during byte writes.

and BWSx. Bytes written are determined by BWS

. Bytes not selected during byte writes remain unaltered. All

[3:0]

6

CY7C1333

Maximum Ratings

(Abov e which the useful life may be impaired. For use r gui de­lines, not tested.)

Storage Temperature .....................................−65°C to +150°C

Ambient Temperature with

Curre n t in to Out p ut s (L OW )............... .......................... 20 mA

Static Discharge Voltage ........... .. .......... .. .. .......... .. ... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current............. .......... ..................... ........ >200 mA

Operating Range

Po wer Applied.................................................. −55°C to +12 5°C

Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V

DC Voltage Applied to Output s
in High Z State

DC Input Voltage

Electrical Characteristics

[9]

.....................................−0.5V to V

[9]

..................................−0.5V to V

Over the Operating Range

DDQ
DDQ

+ 0.5V
+ 0.5V

Range

Com’l 0°C to +70°C 3.3V ± 5%

Ambient

Temperature

[10]

VDD/V

DDQ

Parameter Description Test Conditions Min. Max. Unit

V
V
V
V
V
V
I

X

DD
DDQ
OH
OL
IH
IL

Power Supply Voltage 3.135 3.465 V
I/O Supply Voltage 3.135 3.465 V

[11]

[11]

2.4 V

0.4 V
+ 0.3V

DD

−0.3

−5

0.8 V

5

Output HIGH Voltage VDD = Min., I

= −4.0 mA

OH

Output LOW Volt age VDD = Min., IOL = 8.0 mA
Input HIG H Voltage 2.0 V
Input LOW Voltage
Input Load Current GND ≤ VI ≤ V

[9]

DDQ

Input Current of MODE –30 30

V

µA
µA

I

OZ

I

CC

I

SB1

I

SB2

I

SB3

Capacitance

Output Leakage
Current

VDD Operating Suppl y V

Auto matic CE
Power-Down
Current—TTL Inputs

Auto matic CE
Power-Down
Current—CMOS Inp uts

Auto matic CE
Power-Down
Current—CMOS Inp uts

[12]

GND ≤ VI ≤ V

= Max., I

DD

f = f

MAX

= 1/t

Output Disabled

DDQ,

= 0 mA,

OUT

CYC

Max. VDD, Device Deselected,
V

≥ VIH or VIN ≤ V

IN

f = f

MAX

= 1/t

IL

CYC

Max. VDD, Device Dese lected, VIN
≤ 0.3V or V
f = 0

IN

> V

DDQ

– 0.3V,

Max. VDD, Device Deselected, or
V

≤ 0.3V or VIN > V

IN

f = f

MAX

= 1/t

CYC

DDQ

– 0.3V

15-ns cycle, 66 MHz 310 mA
20-ns cycle, 50 MHz 260 mA
15-ns cycle, 66 MHz 40 mA
20-ns cycle, 50 MHz 35 mA

All speed grades 5.0 mA

15-ns cycle, 66 MHz 30 mA
20-ns cycle, 50 MHz 25 mA

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V.

C

CLK

C

I/O

Notes:

9. Minimum voltage equals –2.0V for pulse duration less than 20 ns.

10. T

is the case temperature.

A

11. The load used for V

12. Tested initially and after any design or process change that may affect these parameters.

Clock Input Capa citance 4 pF
Input/Output Capacitance 6 pF

and VOL testing is shown in figure (b) of the AC test conditions.

OH

V

DD
DDQ

= 3.3V

−5

5

4 pF

µA

7

AC Test Loads and Waveforms

R=317

OUTPUT

3.3V

Z

=50

Ω

0

V

L

R

= 1.5V

L

(a) (b)

=50

OUTPUT

Ω

INCLUDING

JIG AND

SCOPE

5pF

Ω

R=351

1333-2

ALL INPUT PULSES

3.0V

Ω

GND

Thermal Resistance

Description Tes t Condi ti ons Symbol TQFP Typ. Units Notes

Thermal Resistance
(Junc t ion to Ambie nt)

Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circ uit board

Θ

JA

28 °C/W 12

CY7C1333

[13]

Thermal Resistance

Θ

JC

4 °C/W 12

(Junction to Case)

Switching Characteristics

Over the Operating Range

[13, 14, 15]

CY7C1333-66 CY7C1333-50

Parameter Description Min. Max. Min. Max. Unit

t

CYC

t

CH

t

CL

t

CDV

t

DOH

t

AS

t

AH

t

CENS

t

CENH

t

WES

t

WEH

t

DS

t

DH

t

CES

t

CEH

t

CHZ

t

CLZ

t

EOHZ

t

EOLZ

t

EOV

Notes:

13. Unless otherwise noted, test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading shown in (a) of AC test loads.

14. t

, t

CHZ

CLZ

voltage.

15. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.

16. This parameter is sampled and not 100% tested.

Clock C y cle Time 15.0 20.0 ns
Clock HIGH 5.0 6.0 ns
Clock L OW 5.0 6.0 ns
Data Output Valid After CLK Rise 12.0 14.0 ns
Data Output Hold After CLK Rise 2.0 2.0 ns
Address Set-Up Before CLK Rise 2.0 2.5 ns
Address Hold After CLK Rise 0.5 1.0 ns
CEN Set-Up Before CLK Rise 2.0 2.5 ns
CEN Hold After CLK Rise 0.5 1.0 ns
WE, BWS
WE, BW

Set-Up Before CLK Rise 2.0 2.5 ns

[3:0]

Hold After CLK Rise 0.5 1.0 ns

[3:0]

Data Input Set-Up Before CLK Rise 2.0 2.5 ns
Data Input Hold After CLK Rise 0.5 1.0 ns
Chip Select Set-Up 2.0 2.5 ns
Chip Select Hold After CLK Rise 0.5 1.0 ns
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
OE LOW to Output Valid

, t

, t

EOLZ

, and t

EOV

[12, 14, 15 , 16]

[12, 14, 15, 16]

[12, 14, 15 , 16]

[12, 14, 15 , 16]

[14]

are specified with A/C test conditions shown in part (a) of AC T est Loads. Transition is measured ± 200 mV from steady-state

EOHZ

is less than t

EOHZ

EOLZ

and t

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

2.0 5.0 2.0 5.0 ns

3.0 3.0 ns

6.0 7.0 ns

1.0 1.0 ns

6.0 7.0 ns

8

CY7C1333

Sw itching Wave fo rms

Read/Write/Deselect Timing

Read

CLK

RA1

t

WH

t

CENH

t

AH

t

CEH

WA2

t

CENS

CEN

t

AS

ADDRESS

WE

CE

t

CES

t

WS

Write

Read

DESELECT

t

t

CL

CH

RA3 RA4

Read

t

CYC

WA5

Write

Read

RA6

t

CENS

RA7

Read

Suspend

t

CENH

DESELECT

DESELECT

t

Data­In/Out

Device
originally
deselected

t

CLZ

t

CDV

t

DOH

Q1

Out

1a

D2

In

Q3

Out

t

1a

CHZ

Q4

Out

DOH

D5

In

Q6
Out

WE is the combi nation of WE & BWSx to define a write cycle (see Writ e Cycle Description ta ble).

CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select
the device. Any chip select can deselect the devi ce. RAx stands for Read Address X, WAx stands for

Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.

= DON’T CARE

= UNDEFINED

Q7

Out

t

CHZ

9

CY7C1333

Sw itching Wave fo rms

Read/Write/Deselect Timing

Begin Read

CLK

RA1

t

WH

t

ALH

t

ALS

ADV/LD

ADDRESS

WE

t

WS

(continued)

Burst Read

Burst Read

t

CH

Burst Se quences

Burst Read

t

CL

t

WS

t

AS

WA2

Begin Write

t

t

AH

t

WH

CYC

Burst Write

Burst Write

Burst Write

Begin Read

RA3

Burst Read

Burst Read

BWS

[3:0]

t

t

CES

CEH

CE

t

CHZ

Q1+3

Out

Data­In/Out

t

CLZ

Device

t

CDV

t

DOH

Q1

Out

1a

t

CDV

Q1+1

Out

Q1+2

Out

originally deselected

The combination of WE & BWS

define a write cycle (see Wr ite Cycle Description table).

[3:0]

CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for

Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for locat ion X. CEN
LOW. During burst writes, byte writes can be conducted by asserting the appr opriate BWS

Burst order determined by the state of the Mode input. CEN

t

DH

D2

In

t

DS

D2+1

In

held LOW. OE held LOW.

D2+2InD2+3

In

t

CLZ

[3:0]

Q3
Out

held

input signals.

Q1+1

Out

= DON’T CARE

= UNDEFINED

10

CY7C1333

Sw itching Wave fo rms

OE

Timing

(continued)

OE

t

EOV

EOLZ

I/Os

t

EOHZ

Three-state

t

Ordering Information

Speed

(MHz)

66 CY7C1333-66AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pac k Commercial
50 CY7C1333-50AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat P ack Commercial

Document #: 38-00642-C

Ordering Code

Package

Name

Package Type

Operating

Range

11

Package Diagram

CY7C1333

100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A101

51-85050-A

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.