Datasheet CY7C1049V33L-20VC, CY7C1049V33L-15VC, CY7C1049V33-15VC Datasheet (Cypress Semiconductor)
Page 1
512K x 8 Static RAM
CY7C1049V33
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 2, 1999
3
Features
• High speed
—t
AA
= 15 ns
• Low active power
—504 mW (max.)
• Low CMOS standby power (Commercial L version)
—1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automat ic power-down when deselected
• TTL-compatibl e inputs and outputs
• Easy memory expansion with CE
and OE fe atures
Functional Description
The CY7C1049V33 is a high-performance CMOS Static RAM
organized as 524,288 words by 8 bits. Easy memory expan-
sion is provided by an active LO W Chip Enable (CE
), an acti ve
LOW Output Enable (OE
), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE
) and
Write Enable ( WE
) inputs LOW . Data on the ei ght I/ O pins ( I/O
0
through I/O7) is then written into the location specified on the
address pins (A
0
through A18).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enab le (OE) LO W whi le f orci ng Write
Enable (WE
) HIGH. Under these conditions, the contents of
the memory locati on specified by the address pins wil l appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
LOW, and WE LOW).
The CY7C1049V33 is available in a standard 400-mil-wide
36-pin SOJ package with cent er power and groun d (revol utionary) pinout.
14
15
Logic Block Diagram Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A13A
12
ACEA
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14
23
24
28
27
26
25
29
32
31
30
Top View
SOJ
12
13
33
36
35
34
16
15
21
22
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
WE
V
CC
A
18
A
15
A
12
A
14
I/O
5
I/O
4
1049V33–1
A
9
A
0
I/O
0
I/O
1
I/O
2
OE
A
17
A
16
A
13
CE
1049V33–2
A
9
A
18
18
17
19
20
GND
I/O
7
I/O3
I/O
6
V
CC
A
10
A
11
NC
NC
A
10
Selectio n Gu ide
1049V33-12 1049V33-15 1049V33-17 1049V33-20 1049V33-25
Maximum Access Time (ns) 12 15 17 20 25
Maximum Operating Current (mA) 150 140 130 120 110
Maximum CMOS Standby
Current (mA)
Com’l/Ind’l 8888 8
Com’l L 0.5 0.5 0.5 0.5 0.5
Shaded areas contain preliminary information.
Page 2
CY7C1049V33
2
Maximum Ratings
(Above which the useful lif e m ay be impaired. For user guidelines, not tested.)
Storage Temperature ................... ........... .. .–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND
[1]
....–0.5V to +4.6V
DC V oltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to VCC + 0.5V
DC Input Voltage
[1]
................................–0.5V to VCC + 0.5V
Curre n t in to Out p ut s (L OW )........ ......... .......... .......... .... 20 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial 0°C to +70°C 3.3V ± 0.3V
Industrial –40°C to +85°C
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
7C1049V33-12 7C1049V33-15 7C1049V33-17
Min. Max. Min. Max. Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min.,
I
OH
= –4.0 mA
2.4 2.4 2.4 V
V
OL
Outp u t LOW Voltage VCC = Min.,
I
OL
= 8.0 mA
0.4 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
+ 0.5
2.2 V
CC
+ 0.5
2.2 V
CC
+ 0.5
V
V
IL
Input LOW Voltage
[1]
–0.5 0.8 –0.5 0.8 –0.5 0.8 V
I
IX
Input Load Current GND < VI < V
CC
–1 +1 –1+1–1+1µA
I
OZ
Output Leakage
Current
GND < V
OUT
< VCC,
Output Disabled
–1 +1 –1+1–1+1µA
I
CC
VCC Operating
Supply Current
VCC = Max.,
f = f
MAX
= 1/t
RC
150 140 130 mA
I
SB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > V
IH
VIN > VIH or
V
IN
< VIL, f = f
MAX
30 30 30 mA
I
SB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE
> VCC – 0.3V,
V
IN
> VCC – 0.3V,
or V
IN
< 0.3V, f=0
Com’l/Ind’l
888mA
Com’lL
0.5 0.5 0.5 mA
Shaded areas contain preliminary information.
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
Page 3
CY7C1049V33
3
Electrical Characteristics
Over the Operating Range (continued)
7C1049V33-20 7C1049V33-25
Parameter Description Test Conditions Min. Max. Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min.,
I
OH
= –4.0 mA
2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min.,
I
OL
= 8.0 mA
0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
+ 0.5 2.2 VCC + 0.5 V
V
IL
Input LOW Voltage
[1]
–0.5 0.8 –0.5 0.8 V
I
IX
Input Load Current GND < VI < V
CC
–1+1–1+1µA
I
OZ
Output Leakage
Current
GND < V
OUT
< VCC,
Output Disabled
–1+1–1+1µA
I
CC
VCC Operating
Supply Current
VCC = Max.,
f = f
MAX
= 1/t
RC
120 110 mA
I
SB1
Autom a t i c C E
Po wer-Down Current
—TTL Inpu ts
Max. VCC, CE > V
IH
VIN > VIH or
V
IN
< VIL, f = f
MAX
30 30 mA
I
SB2
Autom a t i c C E
Po wer-Down Current
—CMOS Inputs
Max. V
CC
,
CE
> VCC – 0.3V,
V
IN
> VCC – 0.3V,
or V
IN
< 0.3V, f=0
Com’l/Ind’l8 8mA
Com’lL 0.5 0.5 mA
Capacitance
[3]
Parameter Description Te st Condi tions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 MHz,
V
CC
= 3.3V
8pF
C
OUT
I/O Capacitance 8 pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
1049V33–3
1049V33–4
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
OUTPUT
(a)
(b)
≤
3 ns
≤
3ns
R1 317
Ω
167
Ω
R2
351
Ω
VENIN EQUIVALENT
THÉ
1.73V
Page 4
CY7C1049V33
4
Switching Characteristics
[5]
Over the Operating Range
7C1049V33-12 7C1049V33-15 7C1049V33-17
Parameter Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 12 15 17 ns
t
AA
Address to Data Valid 12 15 17 ns
t
OHA
Data Hold from Address Change 3 33ns
t
ACE
CE LOW to Data Valid 12 15 17 ns
t
DOE
OE LOW to Data Valid 678ns
t
LZOE
OE LOW to Low Z 0 00ns
t
HZOE
OE HIGH to High Z
[5, 6]
678ns
t
LZCE
CE LOW to Low Z
[6]
3 33ns
t
HZCE
CE HIGH to High Z
[5, 6]
678ns
t
PU
CE LOW to Power-Up 0 00ns
t
PD
CE HIGH to Power-Down 12 15 17 ns
WRITE CYCLE
[7, 8]
t
WC
Write Cycle Time 12 15 17 ns
t
SCE
CE LOW to Write End 10 12 13 ns
t
AW
Address Set-Up to Write End 10 12 13 ns
t
HA
Address Hold from Write End 0 00ns
t
SA
Address Set-Up to Write Start 0 00ns
t
PWE
WE Pulse Width 10 12 13 ns
t
SD
Data Set -U p to Write End 7 89ns
t
HD
Data Hold from Write End 0 00ns
t
LZWE
WE HIGH to Low Z
[6]
3 33ns
t
HZWE
WE LOW to High Z
[5, 6]
678ns
Shaded areas contain preliminary information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
and 30-pF load cap acitance.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified wi th a loa d capac itance of 5 pF as i n part (b) of A C Test Loads. Transition is measured ±500 mV from steady-sta te v ol tage .
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any giv en de vi ce.
7. The internal write time of the memory is defined by the overlap of CE
LOW , and WE LOW . CE and WE must be LOW to initi ate a write, a nd the tr ansition of either of these
signals can terminate the write . The i nput data set-up and ho ld timing s hould be ref er enced to the leadi ng edge o f the signal that terminates t he write.
8. The minimum write cycle time for Write Cycle no. 3 (WE
contro lle d , OE LOW) is the sum of t
HZWE
and tSD.
Page 5
CY7C1049V33
5
Switching Characteristics
[5]
Over the Operating Range (continued)
Parameter Description
7C1049V33-20 7C1049V33-25
UnitMin. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 20 25 ns
t
AA
Address to Data Valid 20 25 ns
t
OHA
Data Hold from Address Change 3 5 ns
t
ACE
CE LOW to Data Valid 20 25 ns
t
DOE
OE LOW to Data Valid 8 10 ns
t
LZOE
OE LOW to Low Z 0 0 ns
t
HZOE
OE HIGH to High Z
[5, 6]
810ns
t
LZCE
CE LOW to Low Z
[6]
35ns
t
HZCE
CE HIGH to High Z
[5, 6]
810ns
t
PU
CE LOW to Po wer-Up 0 0 ns
t
PD
CE HIGH to Power-Down 20 25 ns
WRITE CYCLE
[7]
t
WC
Write Cycle Time 20 25 ns
t
SCE
CE LOW to Write End 13 15 ns
t
AW
Address Set-Up to Write End 13 15 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 ns
t
PWE
WE Pulse Width 13 15 ns
t
SD
Data Set-Up to Write End 9 10 ns
t
HD
Data Hold from Write End 0 0 ns
t
LZWE
WE HIGH to Low Z
[6]
35ns
t
HZWE
WE LOW to High Z
[5, 6]
810ns
Data Rete n ti o n C h ar acteristic s
Over the Operating Range (For L version only)
Parameter Description Conditions
[10]
Min. Max Un it
V
DR
VCC for Data Retention 2.0 V
I
CCDR
Data Retention Curren t VCC = VDR = 2.0V,
CE
> VCC – 0.3V
V
IN
> VCC – 0.3V or VIN < 0.3V
330 µA
t
CDR
[3]
Chip Deselect to Data Retention
Time
0ns
t
R
[9]
Operation Recovery Time t
RC
ns
Notes:
9. t
r
< 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
10. No input may exceed V
CC
+ 0.5V.
Page 6
CY7C1049V33
6
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1
[11, 12]
Read Cycle No. 2 (OE Controll ed)
[12, 13]
Notes:
11. Device is continuously selected. OE
, CE = VIL.
12. WE
is HIGH for read cycle.
13. Address valid prior to or coincident with CE tr ansitio n LO W.
1049V33-5
3.0V3.0V
t
CDR
VDR> 2V
DATA RETENTION MODE
t
R
CE
V
CC
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
1049V33–6
ADDRESS
DATA OUT
1049V33–7
50%
50%
DATA VALI D
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
I
CC
I
SB
IMPEDANCE
ADDRESS
DA TA OUT
V
CC
SUPPLY
CURRENT
Page 7
CY7C1049V33
7
Write Cycle No. 1(WE
Controlled, OE HIGH During Write)
[14, 15]
Write Cycle No. 2 (WE Controlled, OE LOW)
[15]
Notes:
14. Data I/O is high impedance if OE
= VIH.
15. If CE
goes HIGH simu ltaneousl y with WE g oing HI GH, the output remain s in a hi gh-impedanc e state.
16. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms
(continued )
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATAINVALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 16
1049V33–8
1049V33-9
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
NOTE
16
Truth Table
CE OE WE I/O0 – I/O
7
Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Page 8
CY7C1049V33
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38–00643–B
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
12 CY7C1049V33-12VC V36 36-Lead (400-Mil) Molded SOJ
Commercial
CY7C1049V33L-12VC V36 36-Lead (400-Mil) Molded SOJ
15 CY7C1049V33-15VC V36 36-Lead (400-Mil) Molded SOJ
CY7C1049V33L-15VC V36 36-Lead (400-Mil) Molded SOJ
17 CY7C1049V33-17VC V36 36-Lead (400-Mil) Molded SOJ
CY7C1049V33L-17VC V36 36-Lead (400-Mil) Molded SOJ
20 CY7C1049V33-20VC V36 36-Lead (400-Mil) Molded SOJ
CY7C1049V33L-20VC V36 36-Lead (400-Mil) Molded SOJ
CY7C1049V33-20VI V36 36-Lead (400-Mil) Mold ed SOJ Industrial
25 CY7C1049V33-25VC V36 36-Lead (400-Mil) Molded SOJ Commercial
CY7C1049V33-25VI v36 36-Lead (4 00-Mil) Molded SOJ Industrial
Package Diagram
36-Lead (400-Mil) Molded SOJ V36
51-85090
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