Datasheet CY7C1021V33-12BAC, CY7C1021L-15ZCT, CY7C1021-15ZCT, CY7C1021-15VCT, CY7C1021-12ZCT Datasheet (Cypress Semiconductor)

64K x 16 Static RAM

CY7C1021

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 20, 2000

Features

• High speed
—t

AA

= 12 ns

• CMOS for optimum speed/power

• Low active pow er
—1320 mW (max.)

• Automatic power-down when deselected

• Independent Control of Upper and Lower bits

• Av ailable in 44-pin TSOP II and 400-mil SOJ

Functional Description

The CY7C1021 is a high-performance CMOS static RAM or­ganized as 65,536 words by 16 bits. This device has an auto­matic power-down feature that significantly reduces power
consumption when deselected.

Writing to the device is accomplished by taking Chip Enable
(CE

) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE

) is LOW, then data from I/O pins (I/O1 through I/O8), is

written into the location specified on the address pins (A

0

through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O

9

through I/O16) is written into the location

specified on the address pins (A

0

through A15).

Reading from the device is accomplished by taking Chip En­able (CE

) and Output En able (O E) LOW whil e forc ing the write

enable (WE

) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/ O

1

to I/O8. If Byte High Enable (BHE) is LOW,

then data from memory will appear on I/O

9

to I/O16. See the
truth table a t the bac k of this data s heet f or a complete des crip­tion of read and write modes.

The input/output pins (I/O

1

through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disab led (OE HIGH ), the BHE and BLE
are disab led (BHE, BL E HIGH), or during a write operation (CE
LOW, and WE LOW).

The CY7C1021 is available in standard 44-pin TSOP Type II
and 400-mil-wide SOJ packages.

WE

Logic Block Diagram

Pin Configuration

1
2
3
4
5
6
7
8
9
10
11

14

31

32

36
35
34
33

37

40
39
38

Top View

SOJ / TSOP II

12
13

41

44
43
42

16

15

29

30

V

CC

A

15

A

14

A

13

A

12

NC

A

4

A

3

OE

V

SS

A

5

I/O

16

A

2

CE

I/O

3

I/O

1

I/O

2

BHE

NC

A

1

A

0

1021-2

18

17

20

19

I/O

4

27

28

25

26

22

21

23

24

NC

V

SS

I/O

7

I/O

5

I/O

6

I/O

8

A

6

A

7

BLE

V

CC

I/O

15

I/O

14

I/O

13

I/O

12

I/O

11

I/O

10

I/O

9

A

8

A

9

A

10

A

11

64K x 16

RAM Array

I/O

1

– I/O

8

ROW DECODER

A

7

A

6

A

5

A

4

A

3

A

0

COLUMN DECODER

A

9

A10A11A

12A13A14

A

15

512 X 2048

SENSE AMPS

DATA IN DRIVERS

OE

A

2

A

1

I/O9 – I/O

16

CE

WE

BLE

BHE

A

8

Selection G uide

7C1021-10 7C1021-12 7C1021-15 7C1021-20

Maximum Access Time (ns) 10 12 15 20
Maximum Operating Current (mA) Commercial 220 220 220 220
Maximum CMOS Standby Current (mA) Commercial 5 5 5 5

L 0.5 0.5 0. 5 0.5

Shaded areas contain preliminary information.

CY7C1021

2

Maximum Ratings

(Above which the useful lif e m ay be impaired. For user guide­lines, not tested.)

Storage Temperature ...... ...........................–65°C to +150°C

Ambient Temperature with

Power Applied .............................................–55°C to +125°C

Supply Voltage on V

CC

to Relative GND

[1]

....–0.5V to +7.0V

DC V oltage Applied to Outputs
in High Z State

[1]

......................................–0.5V to VCC+0.5V

DC Input Voltage

[1]

...................................–0.5V to VCC+0.5V

Curre n t in to Out p ut s (L OW)..... ... ................................. 20 mA

Static Discharge Voltage .......... ......................... .. ......>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Range

Ambient

Temperature

[2]

V

CC

Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85 °C 5V ± 10%

Electrical Characteristics

Over the Operating Range

Parameter Description

T est Conditions 7C1021-10 7C1021-12 7C1021-15 7C1021-20

UnitMin. Max. Min. Max. Min. Max. Min. Max.

V

OH

Output HIGH Voltage VCC = Min.,

I

OH

= –4.0 mA

2.4 2.4 2.4 2.4 V

V

OL

Output LOW Voltage VCC = Min.,

I

OL

= 8.0 mA

0.4 0.4 0.4 0.4 V

V

IH

Input HIGH Voltage 2.2 6.0 2.2 6.0 2.2 6.0 2.2 6.0 V

V

IL

Input LOW Voltage

[1]

−0.5

0.8 –0.5 0.8 –0.3 0.8 –0.3 0.8 V

I

IX

Input Load Current GND < VI < V

CC

−1

+1 –1 +1 –1 +1 –1 +1

µA

I

OZ

Output Leakage
Current

GND < VI < VCC,
Output Disabled

−1

+1 –1 +1 –5 +5 –5 +5

µA

I

OS

Output Short
Circuit Current

[3]

VCC = Max.,
V

OUT

= GND

−300

–300 –300 –300 mA

I

CC

VCC Operating
Supply Current

VCC = Max.,
I

OUT

= 0 mA,

f = f

MAX

= 1/t

RC

220 220 220 200 mA

I

SB1

Automati c C E
Po wer-Down Current
—TTL Inputs

Max. VCC,
CE

> V

IH

VIN > VIH or
V

IN

< VIL, f = f

MAX

40 40 40 40 mA

I

SB2

Automati c C E
Po wer-Down Current
—CMOS Inputs

Max. VCC,
CE

> VCC – 0.3V,

V

IN

> VCC – 0.3V,

or V

IN

< 0.3V, f=0

5 5 5 5 mA

L 0.5 0.5 0.5 0.5 mA

Shaded areas contain preliminary information.

Capacitance

[4]

Parameter Description T est Condi tions Max. Unit

C

IN

Input Capacitance TA = 25°C, f = 1 MHz,

V

CC

= 5.0V

8 pF

C

OUT

Output Capacitance 8 pF

Notes:

1. V

IL

(min.) = –2.0V for pulse durations of less t han 20 ns.

2. T

A

is the case temper ature .

3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

4. Tested initially and after any design or process changes that may affect these parameters.

CY7C1021

3

AC Test Loads and Wa veforms

1021-3

1021-4

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

5V

OUTPUT

30 pF

INCLUDING
JIG AND
SCOPE

5V

OUTPUT

5 pF

INCLUDING
JIG AND
SCOPE

(a)

(b)

< 3 ns < 3 ns

OUTPUT

R 481

Ω

R 481

Ω

R2

255

Ω

R2

255

Ω

167

Equivalent to:

THÉVENIN

EQUIVALENT

1.73V

30 pF

Switching Characteristics

[5]

Over the Operating Range

Parameter Description

7C1021-10 7C1021-12 7C1021-15 7C1021-20

UnitMin. Max. Min. Max. Min. Max. Min . Max.

READ CYCLE

t

RC

Read Cycle Time 10 12 15 20 ns

t

AA

Address to Data Valid 10 12 15 20 ns

t

OHA

Data Hold from Address Change 3 3 3 3 ns

t

ACE

CE LOW to Data Valid 10 12 15 20 ns

t

DOE

OE LOW to Data Valid 5 6 7 9 ns

t

LZOE

OE LOW to Low Z

[6]

0 0 0 0 ns

t

HZOE

OE HIGH to High Z

[6, 7]

5 6 7 9 ns

t

LZCE

CE LOW to Low Z

[6]

3 3 3 3 ns

t

HZCE

CE HIGH to High Z

[6, 7]

5 6 7 9 ns

t

PU

CE LOW to P ower-Up 0 0 0 0 ns

t

PD

CE HIGH to Power- Down 10 12 15 20 ns

t

DBE

Byte Ena ble to D a ta Valid 5 6 7 9 ns

t

LZBE

Byte Enable to Low Z 0 0 0 0 ns

t

HZBE

Byte Di s a ble to High Z 5 6 7 9 ns

WRITE CYCLE

[8]

t

WC

Write Cycle Time 10 12 15 20 ns

t

SCE

CE LOW to Write End 8 9 10 12 ns

t

AW

Address Set-Up to Write End 7 8 10 12 ns

t

HA

Address Hold from Write End 0 0 0 0 ns

t

SA

Address Set-Up to Write Start 0 0 0 0 ns

t

PWE

WE Pulse Width 7 8 10 12 ns

t

SD

Data Set-Up to Write End 5 6 8 10 ns

t

HD

Data Hold from Write End 0 0 0 0 ns

t

LZWE

WE HIGH to Low Z

[6]

3 3 3 3 ns

t

HZWE

WE LOW to High Z

[6, 7]

5 6 7 9 ns

t

BW

Byte Enable to End of W r ite 7 8 9 12 ns

Shaded areas contain preliminary information.

Notes:

5. T est conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I

OL/IOH

and 30-pF load capac itance .

6. At any given temperature and voltage condition, t

HZCE

is less than t

LZCE

, t

HZOE

is less than t

LZOE

, and t

HZWE

is less than t

LZWE

for any given device.

7. t

HZOE

, t

HZBE

, t

HZCE

, and t

HZWE

are specified with a load capac itance of 5 pF as i n part (b) of A C Test Loads. Transition is measure d ±500 mV from stead y-state vol tag e.

8. The internal write time of the memory is defined by the overlap of CE

LOW, WE LOW and BHE / BLE LOW . CE, WE and BHE / BLE must be LOW to initiate a write,

and the transition of these signa ls can terminate t he write. The input data s et-up and hol d timing sho uld be refer enced to the leading edge of t he signal tha t terminates the write.

CY7C1021

4

Switchin g W aveforms

Notes:

9. Device is continuously selected. OE

, CE, BHE and/or BHE = VIL.

10. WE

is HIGH for r ead cycle .

11. Address valid prior to or coincident with CE transition LOW .

Read Cycle No. 1

PREVIOUS DATA VALID DATA VALID

t

RC

t

AA

t

OHA

1021-5

ADDRESS

DATA OUT

[9, 10 ]

Read Cycle No. 2

(OE

Controlled)

1021-6

50%

50%

DATA VALID

t

RC

t

ACE

t

DOE

t

LZOE

t

LZCE

t

PU

HIGH IMPEDANCE

t

HZOE

t

HZBE

t

PD

HIGH

OE

CE

ICC
ISB

IMPEDANCE

ADDRESS

DATA OUT

V

CC

SUPPLY

t

DBE

t

LZBE

t

HZCE

BHE,BLE

[10, 11]

CURRENT

I

CC

I

SB

CY7C1021

5

Notes:

12. Data I/O is high impedance if OE

or BHE and/or BLE = VIH.

13. If CE

goes HIGH sim ultaneous ly with WE going HI GH, the output rem ains in a high-i mpedance state.

Switchin g W aveforms

(continued)

Write Cycle No. 1 (CE

Controlled)

1021-7

t

HD

t

SD

t

SCE

t

SA

t

HA

t

AW

t

PWE

t

WC

BW

DATA I/O

ADDRESS

CE

WE

BHE, BLE

[12, 13]

t

WriteCycleNo. 2 (BLEor BHE Controlled)

t

HD

t

SD

t

BW

t

SA

t

HA

t

AW

t

PWE

t

WC

t

SCE

DATA I/O

ADDRESS

BHE

,BLE

WE

CE

1021-8

CY7C1021

6

Switchin g W aveforms

(continued)

Write Cycle No.3

(WE

Controlled,LOW)

1021-10

t

HD

t

SD

t

SCE

t

HA

t

AW

t

PWE

t

WC

t

BW

DATA I/O

ADDRESS

CE

WE

BHE

,BLE

t

SA

t

LZWE

t

HZWE

Truth Table

CE OE WE BLE BHE I/O1–I/O

8

I/O9–I/O

16

Mode Power

H X X X X High Z High Z Power-Down Stan dby (ISB)
L L H L L Data Out Data Out Read - All bits Active (ICC)

L H Data Out High Z Read - Lower bits only Active (ICC)
H L Hi gh Z Data Out Read - Upper bits only Active ( ICC)

L X L L L Data In Data In Write - All bits Active (ICC)

L H Data In High Z Write - Lower bits only Active ( ICC)

H L Hi gh Z D a ta In Write - Upper bits only Active ( ICC)
L H H X X Hi gh Z High Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)

CY7C1021

7

Document #: 38-00224-D

Ordering Information

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

10 CY7C1021-10VC V34 44-Lead (400-Mil) Molded SOJ Commercial

CY7C1021-10ZC Z44 44-Lead TSOP Type II Commercial
CY7C1021L-10ZC Z44 44-Lead TSOP Type II Commercial

12 CY7C1021-12VC V34 44-Lead (400-Mil) Molded SOJ Commercial

CY7C1021-12VI V34 44-Lead (400-Mil) Molded SOJ Industrial
CY7C1021-12ZC Z44 44-Lead TSOP Type II Commercial

15 CY7C1021-15VC V34 44-Lead (400-Mil) Molded SOJ Commercial

CY7C1021-15VI V34 44-Lead (400-Mil) Molded SOJ Industrial
CY7C1021-15ZC Z44 44-Lead TSOP Type II Commercial
CY7C1021-15ZI Z44 44-Lead TSOP Type II Industrial
CY7C1021L-15ZC Z44 44-Lead TSOP Type II Commercial

20 CY7C1021-20VC V34 44-Lead (400-Mil) Molded SOJ Commercial

CY7C1021-20ZC Z44 44-Lead TSOP Type II Commercial

Shaded areas contain preliminary information.

Package Diagrams

44-Lead (400-Mil) Molded SOJ V34

51-85082-B

CY7C1021

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams

(continued)

44-Pin TSOP II Z44

51-85087-A