Datasheet CY7C1011BV33-15ZI, CY7C1011BV33-15ZC, CY7C1011BV33-12ZI, CY7C1011BV33-12ZC Datasheet (Cypress Semiconductor)

Features

• 3.0 – 3.6V Operation

• High speed
—t

= 12, 15 ns

AA

• CMOS for optimum speed/power

• Low active power
—684 mW (Max.)

• Automatic power-down when deselected

• Independent control of upper and lower bits

• Available in 44-pin TSOP II

Functional Description

The CY7C1011BV33 is a high-performance CMOS static
RAM organized as 131, 072 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

) and Write Enable (WE) inputs LOW. If Byte Low Enable

(CE

CY7C1011BV33

128K x 16 Static RAM

(BLE

) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A

Reading from the device is accomplished by taking Chip En­able (CE

) and Output Enable (OE) LOW while f orcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LO W, then
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a com plete descrip­tion of read and write modes.

The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).

The CY7C1011BV33 is available in standard 44-pin TSOP
Type II package.

through I/O16) is written into the location

9

to I/O8. If Byte High Enable (BHE) is LOW,

1

through A16).

0

through I/O16) are placed in a

1

0

Logic Block Diagram

DATA IN DRIVERS

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

ROW DECODER

128K x 16

RAM Array

512 X 2048

COLUMN DECODER

9

8

A

A

A10A11A12A13A

I/O

–I/O

1

8

SENSE AMPS

14

16

A15A

I/O9–I/O

BHE
WE

CE
OE

BLE

1011B-1

16

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05021 Rev. *A Revised June 6, 2001

Pin Configuration

CE

I/O
I/O

I/O
I/O

V

V
I/O
I/O
I/O
I/O

WE
A16
A

A
A

A12

A
A
A
A
A

CC

SS

4
3
2
1
0

1
2

3
4

5
6
7
8

15
14

13

TSOP II

Top View

1
2
3
4
5
6
7
8
9
10
11

12
13
14
15
16

17
18
19
20
21
22

CY7C1011BV33

44

A

5

43

A

6

42

A

7

41

OE

40

BHE

39

BLE

38

I/O

16

37

I/O

15

36

I/O

14

35

I/O

13

34

V

SS

33

V

CC

32

I/O

12

31

I/O

11

30

I/O

10

29

I/O

9

28

NC

27

A

8

26

A

9

25

A

10

A

24

11

23

NC

1011B-2

Selection Guide

1011BV33-12 1011BV33-15

Maximum Access Time (ns) Commercial 12 15
Maximum Operating Current (mA) Commercial 190 170
Maximum CMOS Standby Current (mA) Commercial 10 10

Maximum Ratings

(Above which the useful life may be impai red. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High Z State

[1]

DC Input Voltage

to Relative GND

CC

......................................–0.5V to VCC+0.5V

[1]

..................................–0.5V to VCC+0.5V

[1]

....–0.5V to +7.0V

Current into Outputs (LOW)........................................ 20 mA

Static Discharge Voltage...........................................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Range

Temperature

Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%

Ambient

[2]

Electrical Characteristics Ov er the Op erat ing Range

1011BV33-12 1011BV33-15

2.4 2.4 V

0.4 0.4 V

Parameter Description

V

OH

V

OL

Output HIGH Voltage VCC = Min.,

Output LOW Voltage VCC = Min.,

= –4.0 mA

I

OH

= 8.0 mA

I

OL

Test

Conditions

V

CC

UnitMin. Max. Min. Max.

Document #: 38-05021 Rev. *A Page 2 of 10

Electrical Characteristics Ov er the Op erat ing Range (continued)

Parameter Description

V

IH

V

IL

I

IX

I

OZ

Input HIGH Voltage 2.2 2.2 V
Input LOW Voltage
Input Load Current GND < VI < V
Output

Leakage
Current

I

OS

I

CC

Output Short
Circuit

[3]

Current
VCC

Operating
Supply
Current

I

SB1

Automatic CE
Power-Down Current
—TTL Inputs

I

SB2

Automatic CE
Power-Down Current
—CMOS
Inputs

[1]

GND < VI < VCC,
Output Disabled

VCC = Max.,
V

OUT

VCC = Max.,
I

OUT

f = f

Max. VCC,

> V

CE
VIN > VIH or
VIN < VIL,
f = f

Max. VCC,

> VCC – 0.3V , VIN

CE

VCC – 0.3V,

>
or VIN < 0.3V, f = 0

Conditions

= GND

= 0 mA,

= 1/t

MAX

IH

MAX

Test

CC

RC

L 0.5 0.5

CY7C1011BV33

1011BV33-12 1011BV33-15

UnitMin. Max. Min. Max.

–0.3 0.8 –0.3 0.8 V

–1 +1 –1 +1 µA
–1 +1 –1 +1 µA

–300 –300 mA

190 170 mA

40 40 mA

10 10 mA

Capacitance

[4]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 5.0V

Output Capacitance 8 pF

CC

8 pF

AC Test Loads and Waveforms

(b)

R 481Ω

1011B-3

1.73V

R2

255

3.0V

GND

Ω

Rise Time: 1 V/ns Fall Time:1 V/ns

ALL INPUT PULSES

90%

10%

Ω

5V

OUTPUT

30 pF

INCLUDING
JIG AND
SCOPE

Equivalent to:

Notes:

(min.) = –2.0V for pulse durations of less than 20 ns.

1. V

IL

is the “instant on” case temp erature.

2. T

A

3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

R 481

(a)

THÉVENIN
EQUIVALENT

OUTPUT

R2

Ω

255

OUTPUT

5V

5 pF

INCLUDING
JIG AND
SCOPE

167

30 pF

90%

10%

1011B-4

Document #: 38-05021 Rev. *A Page 3 of 10

CY7C1011BV33

Switching Characteristics

[5]

Over the Operating Range

1011BV33-12 1011BV33-15

Parameter Description

UnitMin. Max. Min. Max.

READ CYCLE

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

t

DBE

t

LZBE

t

HZBE

Notes:

4. Tested initially and after any design or process changes that may affect these parameters.

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

6. At any given temperature and voltage condition, t

7. t

and 30-pF load c apacitan ce.

I

OL/IOH

, t

HZOE

HZBE

Read Cycle T ime 12 15 ns
Address to Data V a lid 12 15 ns
Data Hold from Address Change 3 3 ns
CE LOW to Data Valid 12 15 ns
OE LOW to Data Valid 6 7 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z

[6]

[6]

[6, 7]

[6, 7]

0 0 ns

6 7 ns

3 3 ns

6 7 ns
CE LOW to Power-Up 0 0 ns
CE HIGH to Power-Down 12 15 ns
Byte Enable to Data Valid 6 7 ns
Byte Enable to Low Z 0 0 ns
Byte Disable to High Z 6 7 ns

, t

HZCE

, and t

is less than t

are specified w ith a load ca pacit ance of 5 pF as in part (b ) of AC Test L oads. T ransiti on i s measured ±500 mV from steady-state voltage.

HZWE

HZCE

LZCE

, t

HZOE

is less than t

LZOE

, and t

HZWE

is less than t

for any given device.

LZWE

Document #: 38-05021 Rev. *A Page 4 of 10

CY7C1011BV33

Switching Characteristics

[5]

Over the Operating Range

Parameter Description

WRITE CYCLE

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

t

BW

[8]

Write Cycle Time 12 15 ns
CE LOW to Write End 10 12 ns
Address Set-Up to Write End 10 12 ns
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start 0 0 ns
WE Pulse Width 10 12 ns
Data Set-Up to Write End 7 8 ns
Data Hold from Write End 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write 10 12 ns

Switching Waveforms

Read Cycle No. 1

ADDRESS

[9, 10]

[6]
[6, 7]

1011BV33-12 1011BV33-15

UnitMin. Max. Min. Max.

3 3 ns

6 7 ns

t

RC

t

t

OHA

DATA OUT

Note:

8. The internal write time of the memory is defined by the overlap of CE
and the transition of these sign als can terminate the write. The inpu t data set-up and hold timing should be refer enced to the leading edge of the si gnal that terminates the write.

9. Device is continuously selected. OE

10. WE

is HIGH for read cycle .

PREVIOUS DATA VALID DATA VALID

, CE, BHE and/or BHE = VIL.

AA

LOW, W E LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,

1011B-5

Document #: 38-05021 Rev. *A Page 5 of 10

Switching Waveforms (continued)

CY7C1011BV33

Read Cycle No. 2

(OEControlled)

ADDRESS

CE

OE

BHE, BLE

DATA OUT

V

CC

SUPPLY

HIGH IMPEDANCE

t

LZCE

t

PU

CURRENT

Write Cycle No. 1 (CE Controlled)

[10, 11]

t

ACE

t

DOE

t

LZOE

t

DBE

t

LZBE

[12, 13]

50%

t

RC

DATA VALID

t

HZOE

t

HZCE

t

HZBE

t

PD

50%

HIGH

IMPEDANCE

1011B-6

I

ICC

CC

I

ISB

SB

ADDRESS

t

CE

SA

WE

BHE, BLE

DATA I/O

Notes:

11. Address valid prior to or coincident with CE

12. Data I/O is high impedance if OE

13. If CE

goes HIGH simultaneousl y with WE going HIGH, the o utput remains in a hig h-imped ance stat e.

or BHE and/or BLE= VIH.

transition LOW .

t

AW

t

WC

t

SCE

t

PWE

t

BW

t

HA

t

SD

t

HD

1011B-7

Document #: 38-05021 Rev. *A Page 6 of 10

Switching Waveforms (continued)

CY7C1011BV33

Write Cycle No. 2 (BLE

ADDRESS

BHE

,BLE

WE

CE

DATA I/O

Write Cycle No. 3

ADDRESS

(WE

orBHE Controlled)

t

SA

Controlled, OE LOW)

t

WC

t

BW

t

AW

t

WC

t

PWE

t

SCE

t

SD

t

HA

t

HD

1011B-8

t

CE

t

SA

SCE

t

AW

t

PWE

t

HA

WE

t

BW

BHE

, BLE

t

HZWE

t

SD

t

HD

DATA I/O

t

LZWE

1011B-10

Document #: 38-05021 Rev. *A Page 7 of 10

Truth Table

CY7C1011BV33

CE OE WE BLE BHE I/O1–I/O

H X X X X High Z High Z Power-Down Standby (ISB)
L L H L L Data Out Data Out Read - All bits Active (ICC)

L H Data Out High Z Read - Lower bits only Active (ICC)
H L High Z Data Out Read - Upper bits only Active (ICC)

L X L L L Data In Data In Write - All bits Active (ICC)

L H Data In High Z Write - Lower bits only Active (ICC)

H L High Z Data In Write - Upper bits only Active (ICC)
L H H X X High Z Hi gh Z Selected, Output s Di sa bled Active (ICC)
L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)

8

I/O9–I/O

16

Mode Power

Document #: 38-05021 Rev. *A Page 8 of 10

CY7C1011BV33

ng so indemnifies Cypress Semiconductor against all charges.

Ordering Information

Speed

(ns) Ordering Code

12 CY7C1011BV33-12ZI Z44 44-Lead TSOP Type II Industrial

CY7C1011BV33-12ZC Z44 44-Lead TSOP Type II Commercial

15 CY7C1011BV33-15ZC Z44 44-Lead TSOP Type II Commercial

CY7C1011BV33-15ZI Z44 44-Lead TSOP Type II Industrial

Package Diagrams

Package

Name Package Type

44-Pin TSOP II Z44

Operating

Range

Document #: 38-05021 Rev. *A Page 9 of 10

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi

51-85087-A

CY7C1011BV33

Document Title: CY7C1011BV33 128K X 16 Static RAM
Document Number: 38-05021

REV. ECN NO.

** 106652 04/26/01 MPR New Data Sheet

*A 107728 07/11/01 DFP Remov e S OJ T QF P Pac k age s. R emov e 8 , 10 ns. changed Low Acti ve Power

Issue

Date

Orig. of
Change Description of Change

to 684. Change words/array/ added 2 addresses.

Document #: 38-05021 Rev. *A Page 10 of 10