Datasheet CY74FCT257TQCT, CY74FCT257TQC, CY74FCT257CTSOCT, CY74FCT257CTSOC, CY74FCT257CTQCT Datasheet (Texas Instruments)

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Quad 2-Input Multiplexe
r
CY74FCT257T
SCCS019 - May 1994 - Revised February 2000
Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Function, pinout, and drive compatible with FCT and
F logic
FCT-C speed at 4.3 ns max.
FCT-A speed at 5.0 ns max.
Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
Matched rise and fall times
Fully compatible with TTL input and output logic levels
• ESD > 2000V
Extended commercial range of 40˚C to +85˚C
• Sink current 64 mA Source current 32 mA
Functional Description
The FCT257T has four identical two-input multiplexers which select four bits of data from two sources under the control of a commondataSelectinput(S).The I
0
inputsareselectedwhen
the Select input is LOW and the I
1
inputs are selected when the Select input is HIGH. Data appears at the output in true non-inverted form for the FCT257T.
The FCT257T is a logic implementation of a four-pole, two position switch where the position of the switch is determined by the logic levels supplied to the select input. Outputs are forced to a high-impedance “OFF” state when the Output Enable input (
OE) is HIGH.
All but one device must be in the high-impedance state to avoid currents exceeding the maximum ratings if outputs are tiedtogether.Design of theOutputEnablesignals must ensure that there is no overlap when outputs of three-state devices are tied together.
The outputs are designed with a power-off disable feature to allow for liv e insertion of boards.
Logic Block Diagram Pin Configurations
I
0a
SI
1a
I
0b
I
1b
I
0c
I
1c
I
0dI1d
Y
a
Y
b
Y
c
Y
d
OE
1 2 3 4 5 6 7 8
V
CC
GND
Top View
SOIC/QSOP
16 15 14 13 12 11
10
9
Y
a
S
I
1a
I
0a
I
1c
I
0c
OE
Y
b
I
1b
I
0b
I
1d
I
0d
Y
c
Y
d
Y
a
S
I
1a
I
0a
I1dI
0d
Y
b
I1bI
0b
I1cI
0c
Y
c
Y
d
OE
LogicSymbol
Pin Description
Name Description
I Data Inputs S Common Select Input OE Enable Inputs (Active LOW) Y Data Outputs
Function Table
[1]
Inputs Outputs
OE S I
0
I
1
Y
H
L L L L
X H H L L
X X X L H
X
L H X X
H L H L H
Note:
1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, Z = High impedance (OFF) state.
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CY74FCT257T
2
Maximum Ratings
[2,3]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−65°C to +135°C
Supply Voltage to Ground Potential..................−0.5V to +7.0V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ......120 mA
Power Dissipation..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Operating Range
Range Range
Ambient
Temperature V
CC
Commercial All 40°C to +85°C 5V ± 5%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.
[4]
Max. Unit
V
OH
Output HIGH Voltage VCC=Min., IOH=32 mA 2.0 V
V
OL
Output LOW Voltage VCC=Min., IOL=64 mA 0.3 0.55 V
V
IH
Input HIGH Voltage 2.0 V
V
IL
Input LOW Voltage 0.8 V
V
H
Hysteresis
[5]
All inputs 0.2 V
V
IK
Input Clamp Diode Voltage VCC=Min., IIN=18 mA 0.7 1.2 V
I
I
Input HIGH Current VCC=Max., VIN=V
CC
5 µA
I
IH
Input HIGH Current VCC=Max., VIN=2.7V ±1 µA
I
IL
Input LOW Current VCC=Max., VIN=0.5V ±1 µA
I
OZH
Off State HIGH-Level Output Current VCC= Max., V
OUT
= 2.7V 10 µA
I
OZL
Off State LOW-Level Output Current
VCC = Max., V
OUT
= 0.5V 10 µA
I
OS
Output Short Circuit Current
[6]
VCC=Max., V
OUT
=0.0V 60 120 225 mA
I
OFF
Power-Off Disable VCC=0V, V
OUT
=4.5V ±1 µA
Capacitance
[5]
Parameter Description Typ.
[4]
Max. Unit
C
IN
Input Capacitance 5 10 pF
C
OUT
Output Capacitance 9 12 pF
Notes:
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4. Typical values are at V
CC
=5.0V, TA=+25˚C ambient.
5. This parameter is specified but not tested.
6. Not morethanone output should beshorted ata time. Duration ofshort should notexceed one second. Theuse of high-speed test apparatusand/or sample and holdtechniques are preferableinorder to minimize internalchipheating and more accuratelyreflect operational values.Otherwise prolonged shorting of a high output mayraise the chip temperature well above normal and therebycauseinvalid readings in other parametric tests. In anysequence of parameter tests, I
OS
tests should be performed last.
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CY74FCT257T
3
Document #: 3800289B
Power Supply Characteristics
Parameter Description Test Conditions Typ.
[4]
Max. Unit
I
CC
Quiescent Power Supply Current VCC=Max., VIN≤0.2V, VIN≥VCC−0.2V 0.1 0.2 mA
I
CC
Quiescent Power Supply Current (TTL inputs HIGH)
VCC=Max., VIN=3.4V, f1=0, Outputs Open
[7]
0.5 2.0 mA
I
CCD
Dynamic Power Supply Current
[8]
VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, OE=GND, VIN≤0.2V or VIN≥VCC−0.2V
0.06 0.12 mA/MHz
I
C
Total Power Supply Current
[9]
VCC=Max., 50% Duty Cycle, Outputs Open, One Inputt Toggling at f
1
=10 MHz,
OE=GND, VIN≤0.2V or VIN≥VCC−0.2V
0.7 1.4 mA
VCC=Max.,50% Duty Cycle, Outputs Open, One Input Toggling at f
1
=10 MHz,
OE=GND, VIN=3.4V or VIN=GND
1.0 2.4 mA
VCC=Max., 50% Duty Cycle, Outputs Open, Four Bits Toggling at f
1
=2.5 MHz,
OE=GND, VIN≤0.2V or VIN≥VCC−0.2V
0.7 1.4
[10]
mA
VCC=Max., 50% Duty Cycle, Outputs Open, Four Bits Toggling at f
1
=2.5 MHz,
OE=GND, VIN=3.4V or VIN=GND
1.7 5.4
[10]
mA
Switching Characteristics Over the Operating Range
Parameter Description
CY74FCT257T CY74FCT257AT CY74FCT257CT
Unit Fig. No.
[12]
Min.
[11]
Max. Min.
[11]
Max. Min.
[11]
Max.
t
PLH
t
PHL
Propagation Delay I to Y 1.5 6.0 1.5 5.0 1.5 4.3 ns 1, 3
t
PLH
t
PHL
Propagation Delay S to O 1.5 10.5 1.5 7.0 1.5 5.2 ns 1, 3
t
PZH
t
PZL
Output Enable Time 1.5 8.5 1.5 7.0 1.5 6.0 ns 1, 7, 8
t
PHZ
t
PLZ
Output Disable Time 1.5 6.0 1.5 5.5 1.5 5.0 ns 1, 7, 8
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
4.3 CY74FCT257CTQCT Q1 16-Lead (150-Mil) QSOP Commercial CY74FCT257CTSOC/SOCT S1 16-Lead (300-Mil) Molded SOIC
5.0 CY74FCT257ATQCT Q1 16-Lead (150-Mil) QSOP Commercial
6.0 CY74FCT257TQCT Q1 16-Lead (150-Mil) QSOP Commercial
Notes:
7. Per TTL driven input (V
IN
=3.4V); all other inputs at VCC or GND.
8. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
9. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
IC=ICC+ICCDHNT+I
CCD(f0
/2 + f1N1)
I
CC
= Quiescent Current with CMOS input levels
I
CC
= Power Supply Current for a TTL HIGH input (VIN=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
10. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
11. Minimum limits are specified but not tested on Propagation Delays.
12. See “Parameter Measurement Information” in the General Information section.
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CY74FCT257T
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Package Diagrams
16-Lead Quarter Size Outline Q1
16-Lead Molded SOIC
S1
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Copyright 2000, Texas Instruments Incorporated
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