Page 1
查询CY62146CV30供应商
CY62146CV30 MoBL™
256K x 16 Static RAM
Features
• High speed:
—55 ns and 70 ns availability
• Voltage range:
—CY62146CV30: 2.7V – 3.3V
• Pin compatible with CY62146V
• Ultra-low active power
—Typical active current: 1.5 mA @ f = 1 MHz
—Ty pical active curre nt: 7 mA @ f = f
(70 ns speed)
max
• Low standby power
• Easy memory expansion with CE
and OE features
• Automatic power-down when deselec ted
• CMOS for optimum speed/power
Functional Description
The CY62146CV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL™) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by 99% when deselected (CE
HIGH). The input/output pins (I/O0 – I/ O15) are placed in a
high-impeda nce state when : deselected (CE
are disabled (OE
Enable are disabled (BHE
operation (CE
HIGH), both Byte High Enable an d Byte Low
, BLE HIGH), or during a Write
LOW and WE LOW).
HIGH), outputs
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
) is LOW, then data from I/O pins (I/O0 – I/O7), is written
(BLE
into the location specified on the address pins (A
Byte High Enable (BHE
– I/O15) is written into the location specified on the
(I/O
8
address pins (A
– A17).
0
) is LOW, then data from I/O pins
– A17). If
0
Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the Truth Table on page 9 for a complete description of Read
– I/O7. If Byte High Enable (BHE) is
0
to I/O15. See
8
and Write mode s.
The CY62146CV30 is available in 48-ball FBGA packaging.
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K × 16
RAM Array
2048 × 2048
COLUMN DECODER
11
12
A
A
15
13
A
16
14
A
A
A
– I/O
I/O
0
7
SENSE AMPS
17
A
I/O8 – I/O
BHE
WE
CE
OE
BLE
15
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05203 Rev. ** Revised December 17, 2001
Page 2
CY62146CV30 MoBL™
Pin Configuration
[1,2]
Product Portfolio
1
BLE
I/O
I/O
V
SS
V
CC
I/O
I/O
NC
2
OE
BHE
8
I/O
10
9
I/O
11
I/O
12
I/O
13
14
NC
15
A
8
FBGA (Top View)
4
3
A
A
0
1
A
A
4
3
A
A
5
6
A
A
DNU
7
17
A
16
A
A
15
14
A
A
13
12
A
A
10
9
A
CE
I/O
I/O
I/O
I/O
WE
A
5
6
NC
2
I/O
I/O
1
V
3
V
4
I/O
5
I/O
NC
11
A
B
0
C
2
cc
D
ss
E
F
6
G
7
H
Power Dissipation (Industrial)
V
Range
Product
V
CC(min.)VCC(typ.)
CY62146CV302.7V3.0V3.3V
Maximum Ratings
(Above which the useful life may be im pa ired . Fo r us er gui delines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...–0.5V to V
DC Voltage Applied to Outputs
in High-Z State
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or V
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
4. V
IL(min.)
[4]
....................................–0.5V to VCC + 0.5V
= –2.0V for pulse durations less than 20 ns.
CC
[3]
V
CC(max.)
ccmax
to ensure proper appl ication.
SS
Speed
Typ.
55 ns 1.5 mA 3 mA 12 mA 25 mA
70 ns 1.5 mA 3 mA 7 mA 15 mA
DC Input Voltage
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current........................................... ........ > 200 mA
Operating Range
+ 0.5V
CY62146CV30 Industrial –40°C to +85°C 2.7V to 3.3V
Operating, I
CC
f = 1 MHz f = f
[3]
Max. Typ.
[3]
[4]
....................................−0.5V to VCC + 0.5V
Device Range
max
Max. Typ.
7 µA15 µA
Ambient
Temperature V
= V
CC
CC(typ.)
, TA = 25°C.
Standby (I
[3]
SB2
Max.
)
CC
Document #: 38-05203 Rev. ** Page 2 of 12
Page 3
Electrical Characteristics Over the Operating Range
CY62146CV30 MoBL™
Parame-
ter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Capacitance
Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 2.4 V
Output LOW Voltage IOL = 2.1mA VCC = 2.7V 0.4 0.4 V
Input HIGH Voltage 2.2 VCC +
Input LOW Voltage –0.3 0.8 –0.3 0.8 V
Input Leakage Current GND < VI < V
Output Leakage Cur-
GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA
CC
rent
VCC Operating Supply
Current
Automatic CE Pow-
er-Down Current—
CMOS Inputs
Automatic CE Power-Down Current—
CMOS Inputs
[5]
f = f
f = 1 MHz
CE > VCC – 0.2V
V
f = f
f=0 (OE
CE > VCC – 0.2V
V
f = 0, Vcc=3.3V
= 1/t
MAX
> VCC – 0.2V or VIN < 0.2V,
IN
max
> VCC – 0.2V or VIN < 0.2V,
IN
RC
(Address and Data Only),
,WE,BHE and BLE)
Parameter Description Test Conditions Max. Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 8 pF
VCC = 3.3V
= 0 mA
I
OUT
CMOS Levels
VCC = V
CC(typ.)
-55 -70
[3]
Max. Min. Typ.
0.3V
1.8 VCC +
[3]
Max.
0.3V
UnitMin. Typ.
V
–1 +1 –1 +1 µA
12 25 7 15
1.5 3 1.5 3
mA
7 15 7 15 µA
6 pF
Thermal Resistance
Description Test Conditions Symbol BGA Units
Thermal Resistance
(Junction to Ambie nt)
Thermal Resistance
(Junction to Case)
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
[5]
[5]
Document #: 38-05203 Rev. ** Page 3 of 12
Still Air, soldered on a 4.25 × 1.125 inch, four-layer
printed circuit board
Θ
JA
Θ
JC
55 °C/W
16 °C/W
Page 4
AC Test Loads and Waveforms
CY62146CV30 MoBL™
30 pF
SCOPE
R1
VCC Typ
R2
Equivalent to: THÉ VENIN EQUIVALENT
GND
Rise TIme: 1 V/ns Fall Time: 1 V/ns
OUTPUT V
10%
ALL INPUT PULSES
90%
R
TH
TH
V
CC
OUTPUT
INCLUDING
JIG AND
Parameters 3.0V Unit
R1 1.105 KOhms
R2 1.550 KOhms
R
TH
V
TH
0.645 KOhms
1.75V Volts
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.
V
DR
I
CCDR
[5]
t
CDR
[6]
t
R
Note:
6. Full device AC operation requires linear V
VCC for Data Retention 1.5 V
VCC= 1.5V
Data Retention Current
Chip Deselect to Data
CE > VCC – 0.2V ,
> VCC – 0.2V or
V
IN
< 0.2V
V
IN
0 ns
Retention Time
Operation Recovery Time t
ramp from V
CC
DR
to V
> 100µs or stable at V
CC(min.)
CC(min.)
RC
>100 µs.
90%
10%
[3]
Max. Unit
ccmax
3 10 µA
V
ns
Document #: 38-05203 Rev. ** Page 4 of 12
Page 5
Data Retention Wavef orm
CY62146CV30 MoBL™
V
V
CC
CC(min)
t
CDR
VDR> 1.5 V
V
CC(min)
t
R
CE
DATA RETENTION MODE
Switching Characteristics Over the Operating Range
[7]
-55 -70
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
[9]
t
LZBE
t
HZBE
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
the specified I
8. At any given temperature and voltage condition, t
any given device.
9. If both byte enables are toggled together, this value is 10 ns.
10. t
HZOE
11. The internal Write time of the memory is defined by the overlap of WE
any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the Write.
, t
HZCE
[11]
and 30 pF load capacitance.
OL/IOH
, t
, and t
HZBE
Read Cycle Time 55 70 ns
Address to Data Valid 55 70 ns
Data Hold from Address Change 10 10 ns
CE LOW to Data Valid 55 70 ns
OE LOW to Data Valid 25 35 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[8]
[8,10]
[8]
[8, 10]
5 5 ns
20 25 ns
10 10 ns
20 25 ns
CE LOW to Power-Up 0 0 ns
CE HIGH to Power-Down 55 70 ns
BHE / BLE LOW to Data Valid 25 35 ns
BHE / BLE LOW to Low Z 5 5 ns
BHE / BLE HIGH to High Z 20 25 ns
Write Cycle Time 55 70 ns
CE LOW to Write End 45 60 ns
Address Set-Up to Write End 45 60 ns
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start 0 0 ns
WE Pulse Width 45 50 ns
BHE / BLE Pulse Width 50 60 ns
Data Set-Up to Write End 25 30 ns
Data Hold from Write End 0 0 ns
WE LOW to High Z
WE HIGH to Low Z
HZCE
transitions are measured when the outputs enter a high-impedance state.
HZWE
[8, 10]
[8]
is less than t
20 25 ns
5 5 ns
/2, input pulse levels of 0 to V
CC(typ.)
, t
LZCE
is less than t
HZBE
, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a Write and
LZBE
, t
HZOE
is less than t
LZOE
, and t
CC(typ.)
HZWE
, and output loading of
is less than t
UnitMin Max Min Max
LZWE
for
Document #: 38-05203 Rev. ** Page 5 of 12
Page 6
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
ADDRESS
t
OHA
DATA OUT PREVIOUS DATA VALID
[12, 13]
t
AA
CY62146CV30 MoBL™
t
RC
DATAIN VALID
Read Cycle 2 (OE Controlled)
ADDRESS
CE
OE
BHE/BLE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
PU
t
t
LZCE
[13, 14]
LZBE
t
ACE
t
t
LZOE
LZOE
t
DBE
t
DOE
50%
t
RC
t
PD
t
HZCE
t
HZOE
t
HZBE
HIGH
IMPEDANCE
DATA VALID
I
50%
CC
I
SB
Notes:
12. Device is continuously selected. OE
13. WE
is HIGH for Read cycle.
14. Address valid prior to or coincident with CE
, CE = VIL, BHE, BLE = VIL.
, BHE, BLE transition LOW.
Document #: 38-05203 Rev. ** Page 6 of 12
Page 7
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)
ADDRESS
CE
[11, 15, 16]
t
SCE
t
CY62146CV30 MoBL™
WC
WE
BHE/BLE
OE
DATA I/O
NOTE
17
Write Cycle 2 (CE Controlled)
ADDRESS
CE
WE
t
SA
t
HZOE
[11, 15, 16]
t
AW
t
PWE
t
BW
t
SD
DATA
t
WC
t
SA
t
AW
t
PWE
IN
t
SCE
VALID
t
HA
t
HD
t
HA
t
BHE/BLE
BW
OE
t
SD
DATA I/O
Notes:
15. Data I/O is high-impedance if OE
16. If CE
17. During this period, the I/Os are in output state and input signals should not be applied.
goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
NOTE
17
t
HZOE
= VIH.
DATA
IN
VALID
t
HD
Document #: 38-05203 Rev. ** Page 7 of 12
Page 8
Switching Waveforms (continued)
CY62146CV30 MoBL™
Write Cycle 3 (WE Controlled, OE LOW)
[16]
ADDRESS
CE
BHE/BLE
t
SA
WE
17
DATAI/O
NOTE
t
HZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)
[16]
t
AW
t
t
BW
SCE
t
t
WC
WC
t
PWE
t
SD
DATAIN VALID
t
HA
t
LZWE
t
HD
ADDRESS
CE
BHE/BLE
WE
DATA I/O
NOTE
t
SCE
t
AW
t
BW
t
SA
t
PWE
t
SD
IN
VALID
17
DATA
t
HA
t
HD
Document #: 38-05203 Rev. ** Page 8 of 12
Page 9
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested.
Typical values are measured at V
Operating Current vs. Supply Voltage
14.0
12.0
10.0
MoBL2
8.0
6.0
(mA)
4.0
CC
I
2.0
0.0
SUPPLY VOLTAGE (V)
2.7
3.0
3.3
= V
CC
, 55 ns)
(f = f
max
, 70 ns)
(f = f
max
(f = 1 MHz)
CC(typ.)
, TA = 25°C.)
Standby Current vs. Supply Voltage
12.0
10.0
MoBL2
8.0
6.0
(mA)
4.0
SB
I
2.0
0
2.7
SUPPLY VOLTAGE (V)
Truth Table
3.0
3.3
CY62146CV30 MoBL™
Access Time vs. Supply Voltage
MoBL2
60
50
40
30
(ns)
AA
20
T
10
0
3.0
2.7
SUPPLY VOL TAGE (V)
3.3
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Standby (ISB)
L X X H H High Z Output Disabled Active (ICC)
L H L L L Data Out (I/OO – I/O15) Read Active (ICC)
L H L H L Data Out (I/OO – I/O7);
– I/O
I/O
8
in High Z
15
L H L L H Data Out (I/O8 – I/O15);
– I/O7 in High Z
I/O
0
Read Active (ICC)
Read Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (I/OO – I/O15) Write Active (ICC)
L L X H L Data In (I/OO – I/O7);
I/O8 – I/O
in High Z
15
L L X L H Data In (I/O8 – I/O15);
– I/O7 in High Z
I/O
0
Write Active (ICC)
Write Active (ICC)
Document #: 38-05203 Rev. ** Page 9 of 12
Page 10
CY62146CV30 MoBL™
Ordering Information
Speed (ns) Ordering Code Package Name Package Type Operating Range
70 CY62146CV30LL-70BAI BA48B 48-ball Fine Pitch BGA (7 mm × 8.5 mm × 1.2 mm) Industrial
CY62146CV30LL-70BVI BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm)
55 CY62146CV30LL-55BAI BA48B 48-ball Fine Pitch BGA (7 mm × 8.5 mm × 1.2 mm)
CY62146CV30LL-55BVI BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm)
Package Diagrams
48-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA48B
51-85106-*C
Document #: 38-05203 Rev. ** Page 10 of 12
Page 11
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
CY62146CV30 MoBL™
48-ball (6.0 mm × 8.0 mm × 1.0 mm) Fine Pitch BGA BV48A
51-85150-**
MoBL, MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All products and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05203 Rev. ** Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
Page 12
TM
Document Title: CY62146CV30 MoBL
Document Number: 38-05203
REV. ECN NO. Is sue
Date
** 112395 01/18/02 GAV New Data Sheet
256K x 16 STATIC RAM
Orig. of
Change
CY62146CV30 MoBL™
Description of Change
Document #: 38-05203 Rev. ** Page 12 of 12
Loading...