Datasheet CXP88624, CXP88616 Datasheet (Sony)

Description

The CXP88616/88624 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuits, PWM output, VISS/ VASS circuit, remote control receiving circuit, VSYNC separator and the measurement circuit which measure signals of capstan FG amplifier and drum FG/PG amplifier and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip.

Also, CXP88616/88624 provides sleep/stop function which enables to lower power consumption.

Features

• A wide instruction set (213 instructions) which cover various types of data

— 16-bit arithmetic/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation

• Incorporated ROM capacity 16K bytes (CXP88616)

24K bytes (CXP88624)

• Incorporated RAM capacity 672 bytes (including PPG RAM)

• Peripheral function

— A/D converter 8 bits, 14 channels, successive approximation system

(Conversion time of 20µs/16MHz)

— Serial interface Incorporated 8-bit, 8-stage FIFO for data

(Auto transfer for 1 to 8 bytes), 1 channel

— Timer 8-bit timer/counter, 2 channels

19-bit time base timer

— High precision timing pattern generation PPG 19 pins 32-stage programmable circuit

RTG 5 pins, 1 channel

5-bit, 8-satge FIFO (RECCTL control), 1channel

— PWM/DA gate output 12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)

DA gate pulse output, 13 bits, 2 channels

— Analog signal input circuit Capstan FG amplifier circuit

Drum FG amplifier circuit Drum PG amplifier circuit

PBCTL amplifier circuit — CTL write/rewrite circuit Recording current control circuit — Servo input control Capstan FG, Drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — VISS/VASS circuit Pulse duty auto detection circuit — 32kHz timer/event counter 32kHz oscillation circuit, ultra-low speed instruction mode — Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO — Tri-state output PPG 1 pin, output 8 pins — Pseudo HSYNC output function — High speed head switching circuit

• Interruption 20 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 100-pin plastic QFP

• Piggyback/evaluation chip CXP88800 100-pin ceramic QFP

– 1 –

CXP88616/88624

100 pin QFP (Plastic)

E96108-ST

CMOS 8-bit Single Chip Microcomputer

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Structure

Silicon gate CMOS IC

– 2 –

CXP88616/88624

SI0

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0, 1, 6, 7

PE2 to PE5

PF0 to PF3

PF4 to PF7

PG0, 1

PI0 to PI7

Vss V

DD

MP

RST

XTAL

EXTAL

CLOCK

GENERATOR/

SYSTEM CONTROL

RAM

672 BYTES

SPC700

CPU CORE

ROM

16K/24K BYTES

INTERRUPT CONTROLLER

2

FIFO

FRC

CAPTURE UNIT

PROGRAMABLE

PATTERN

GENERATOR

RAM

2

AVss

AV

REF

AV

DD

2

A/D CONVERTER

8 BIT TIMER/COUNTER 0

V SYNC SEPARATOR

12 BIT PWM GENERATOR CH0

SERVO INPUT

CONTROL

GAIN

CONTROL

AMP

2

3

2

12 BIT PWM GENERATOR CH1

4

PWM1

PWM0

RMC

CTLAMP

DPG

DFG

CFG

EXI1

EXI0

SYNC

EC

SO0

CS0

AN0 to AN13

REALTIME PULSE

GENERATOR

INT2

INT0

14

8

PORT A

8

PORT B

8

PORT C

PORT D

4

PORT E

4

PORT F

2

PORT G

8

PORT H

8

PORT I

PH0 to PH7

INT1/NMI

PRESCALER/

TIME BASE TIMER

VISS/VASS

REMOCON INPUT

FIFO

SERIAL

INTERFACE UNIT

(CH0)

CH0

CH1

PPO0 to PPO18

RTO3 to RTO7

8 BIT TIMER/COUNTER1

EC

SELECT

PSEUDO HSYNC GENERATOR

HGO

2

DAA1

DAA0

TO

PULSE WIDTH

COUNTER

FIFO

8

19

5

CTL R/W CONTROL

RECCTL

CTLCIN

AMPV

SS

AMPV

DD

DDO

5

NMI

SCK0

FIFO

Block Diagram

– 3 –

CXP88616/88624

Pin Assignment (Top View)

PE5/EXI1

PH7

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70 69 68 67

63

64

65

66

61

62

71

72

73

74

75

76

77

78

79

80

2 3 4

5 6 7 8 9

10

11 12 13 14 15 16 17

18 19

20

21

22

23

24 25

26

27

28

29 30

1

81

82

83

84

88

87

86

85

89

90

100

99

98

97

96

95

94

91

92

93

PE6/PWM0/DAA0 PE7/PWM1/DAA1 CFG DFG DPG VREFOUT AMPV

SS

CTLSAMPI CTLFAMPO CTLAG CTLAMP (+) CTLAMP (–) CTLCIN (–) CTLCIN (+) RECCTL (+) RECCTL (–) AMPV

DD

RECCAP V

DD

AN0/ANOUT AN1 AN2 AN3 PF0/AN4 PF1/AN5 AV

DD

AVREF AVSS PF2/AN6

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

V

SS

XTAL

EXTAL

PG1/AN13

PG0/AN12

PF7/AN11

PF6/AN10

PF5/AN9

PF4/AN8

PF3/AN7

PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10

PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4

PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16

PI7 PI6 PI5 PI4 PI3 PI2

PI1/EC/INT2

PI0/INT0/ENV-DET

PD7/SI0

PD6/SO0

PD5/SCK0

PD4/CS0

PD3/TO/DDO/ADJ/SRVO

PD2

PD1/RMC

PD0/INT1/NMI

PB6/PPO14

PB7/PPO15

PA0/PPO0/HGO

PA1/PPO1

PA2/PPO2

PA3/PPO3

PA4/PPO4

PA5/PPO5

PA6/PPO6

PA7/PPO7

NC

V

DD

V

SS

NC

PE0

PE1

PE2

PE3/SYNC

PE4/EXI0

Note) 1. NC (Pin 90) is always connected to VDD. NC (Pins 86 and 87) are left open.

2. VDD (Pins 61 and 89) are both connected to VDD

3. Vss (Pins 41 and 88) are both connected to GND.

4. MP (Pin 39) must be connected to GND. – 4 –

CXP88616/88624

Pin Description

(Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins)

(Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. Tri-state control is possible. (8 pins)

(Port C) 8-bit output port. I/O can be set in a unit of single bits. Data is gated with PPO or RT contents by OR-gate and they are output. (8 pins)

(Port D) 8-bit output port. I/O can be set in a unit of single bits. (8 pins)

(Port E) 8-bit port. Bits 2, 3, 4 and 5 are for inputs; bits 0, 1, 6 and 7 are for outputs. (8 pins)

Programmable pattern generator (PPG) output. Functions as high precision realtime pulse output port.

(19 pins)

PA0 can be tri-state controlled with PPG.

Pseudo HSYNC output pin.

Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. (5 pins)

Input pin to request external interruption and non-maskable interruption.

Remote control receiving circuit input pin.

Timer/counter, CTL duty detector and servo amplifier output pin.

Serial chip select (CH0) input pin.

Serial clock (CH0) I/O pin. Serial data (CH0) output pin.

Serial data (CH0) input pin.

Composite sync signal input pin. External input pin for FRC capture unit.

(2 pins)

Symbol I/O Description

PA0/PPO0 /HGO

PA1/PPO1

to

PA7/PPO7

PB0/PPO8

to

PB7/PPO15

PC0/PPO16

to

PC2/PPO18

PC3/RTO3

to

PC7/RTO7 PD0/INT1/

NMI PD1/RMC PD2 PD3 /TO

DDO/SRVO PD4/CS0

PD5/SCK0 PD6/SO0

PD7/SI0 PE0 PE1 PE2 PE3/SYNC PE4/EXI0 PE5/EXI1 PE6/PWM0/

DAA0 PE7/PWM1/

DAA1

PWM output pin. (2 pins)

DA gate pulse output pin. (2 pins)

Output/Real-time output/Output

Output/ Real-time output

I/O/ Real-time output

I/O/Input/Input I/O/Input

I/O I/O/Output/Output/

Output I/O/Input

I/O/I/O I/O/Output

I/O/Input Output Output Input Input/Input Input/Input Input/Input

Output/Output

– 5 –

CXP88616/88624

AN0/ANOUT AN1 to AN3

PF0/AN4

to

PF3/AN7 PF4/AN8

to

PF7/AN11 PG0/AN12

PG1/AN13

PH0 to PH7

PI0/INT0/ ENV-DET

PI1/EC/ INT2

PI2 to PI7 CFG DFG DPG RECCTL (+)

RECCTL (–) CTLCIN (+)

CTLCIN (–) CTLAMP (+)

CTLAMP (–) CTLFAMPO CTLSAMPI

RECCAP

VREFOUT CTLAG

AMPVSS AMPVDD

Input/Output Input

Input/Input

Output/Input

Input/Input

Output

I/O/Input

I/O/Input/Input

I/O Input Input Input

I/O

Output

Input Output

Input I/O

Output Output

Description I/O

Description

(Port F) Lower 4 bits are for inputs; upper 4 bits are for outputs. Lower 4 bits are standby release input pins. (8 pins)

(Port G) 2-bit input port. (2 pins)

Analog circuit internal waveform output pin.

(Port H) 8-bit output port; N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins)

(Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Function as standby release input can be set in a unit of single bits. (8 pins)

Input pin to request external interruption. Active when falling edge.

External event input pin for timer/counter.

Trigger pulse input pin for head switching.

Input pin to request external interruption. Active when falling edge.

Capstan FG input pin. Drum FG input pin. Drum PG input pin. RECCTL signal output pin.

(2 pins) Connected to RECCTL (+) and RECCTL (–) with the internal switch for

playback. (2 pins) Input PBCTL signal with capacitor coupled.

(2 pins) PBCTL signal 1st amplifier output. PBCTL signal 2nd amplifier input. Capacitor connecting pin for the slope setting of the CTL writing

trapezoidal wave. Capacitor connecting pin for the VREF level smoothing of DPG, DFG

and CFG. Capacitor connecting pin for the CTL and AGND smoothing. Analog signal input circuit GND pin. Analog signal input circuit power supply pin.

PBCTL signal input pin. (2 pins)

Analog input pin for A/D converter. (14 pins)

– 6 –

CXP88616/88624

EXTAL XTAL RST

NC MP AVDD AVREF AVSS VDD VSS

Input Output

Input

Symbol I/O

Description

Connecting pin of crystal oscillator for system clock. When supplying the external clock, input it to EXTAL pin and input the opposite phase clock to XTAL pin.

System reset pin; Low level active. NC pin. Connect Pin 90 to VDD and leave Pins 86 and 87 open. Test mode input pin. Always connect to GND. Positive power supply pin for A/D converter. Reference voltage input pin for A/D converter. GND pin for A/D converter. Positive power supply pin. GND pin. Connect both Vss pins to GND.

– 7 –

CXP88616/88624

When resetPin

Circuit format

Input/Output Circuit Formats for Pins

PPO data

Data bus

Output becomes active from high impedance by data writing to port.

Port A data

RD (Port A)

Port A

Hi-Z

PA1/PPO1

PA2/PPO2

to

PA7/PPO7

Port B

6 pins

8 pins

Hi-Z

PB0/PPO8

to

PB7/PPO15

Port A

Data bus

RD (Port A)

PA0

Data bus

RD (Port A)

PA1

PPO1

PPG control status register bit 0 Tri-state control selection

PPO1

MPX

PPO0

HOUT

HOUTE

HSEL

Output becomes active from high impedance by data writing to port.

Data bus

Port B data

RD (Port B)

Port B tri-state control

RTO data

PA0/PPO0/ HGO

1 pin

– 8 –

CXP88616/88624

When resetPin

Circuit format

PPO, RTO data

Data bus

RD (Port C)

Port C direction

Port C data

IP

Input protection circuit

RD (Port C direction)

Port D

8 pins

Hi-Z

PC0/PPO16

to

PC2/PPO18

PC3/RTO3

to

PC7/RTO7

PD0/INT1/ NMI PD1/RMC PD4/CS0 PD7/SI0

Port D

4 pins

Hi-Z

PD3/TO/ DDO/SRVO

Port D

1 pin

Port C

MPX

Port D data

IP

Data bus

RD (Port D)

Port D direction

Port D function select

PD3... Timer/counter, CTL duty detection circuit, 32kHz timer, amplifier circuit

Hi-Z

PD2

Port D data

IP

Data bus

RD (Port D)

Port D direction

Port D data

IP

Data bus

RD (Port D)

Port D direction

PD1...Remote control circuit PD0...Interruption circuit PD4, 7...Serial CH0

Schmitt input

– 9 –

CXP88616/88624

When resetPin

Circuit format

IP

RD (Port E)

Schmitt input

Data bus

RD (Port E)

Hi-Z control

AAA

Port E data

A

MPX

Port D data

IP

Data bus

RD (Port D)

Port D direction

Port D function select

MPX

SI0 CH0

SI0

CH0

Note) PD5 is schmitt input PD6 is inverter input

Port E

2 pins

Hi-Z

PD5/SCK0 PD6/SO0

PE0 PE1

Port E

2 pins

1 pin

3 pins

Hi-Z

PE2

PE3/SYNC PE4/EXI0 PE5/EXI1

Port D

IP

RD (Port E)

Data bus

Schmitt input

PE3 PE4 Servo input PE5

Note) For PE3/SYNC, CMOS schmitt input or TTL schmitt input can be selected

with the mask option.

A A

– 10 –

CXP88616/88624

4 pins

2 pins

Hi-Z

When reset

PE6/PWM0/ DAA0 PE7/PWM1/ DAA1

PF4/AN8

to

PF7/AN11

AN0/ANOUT

1 pin

3 pins

AN1

to

AN3

4 pins

High level

PF0/AN4

to

PF3/AN7

Port E

Circuit format

Port F data

IP

Data bus

RD (Port F)

Port/AD select

A/D converter

Input multiplexer

From amplifier circuit

IP

Input multiplexer

A/D converter

Analog output control

IP

Input multiplexer

A/D converter

Port F

RD (Port F)

Data bus

IP

Input multiplexer

A/D converter

Port F

DA gate output or PWM output

Data bus

Port/DA/PWM select

Port E data

RD (Port E)

MPX

Hi-Z control

– 11 –

CXP88616/88624

When reset

Circuit format

RD (Port G)

Data bus

IP

Input multiplexer

A/D converter

Port I data

IP

Data bus

RD (Port I)

Port I direction

RD (Port I direction)

Standby release

Data bus

Edge detection

Hi-Z

PG0/AN12

to

PG1/AN13

2 pins

8 pins

6 pins

Hi-Z

PH0

to

PH7

Data bus

RD (Port H)

AAA

Port H data

Large current 12mA

Medium drive voltage12 V

Port H

PI0/INT0/ EVN-DET

PI1/EC/INT2

Port I data

IP

Data bus

RD (Port I)

Port I direction

RD (Port I direction)

Standby release

Interruption circuit

Data bus

Edge detection

2 pins

PI2

to

PI7

Port I

Port G

Port I

– 12 –

CXP88616/88624

When resetPin

Circuit format

Input pin charge control

IP

CTLAMP (–)

CTLAMP (+)

CTLFAMPO

CTLAG

2 pins

3 pins

1/2AMPVDD

CTLAMP (+) CTLAMP (–) CTLFAMPO

CTLAG VREFOUT

CTLSAMPI

1 pin

3 pins

1/2AMPVDD

CFG DFG DPG

IP

LPF circuit

VREFOUT

Input pin charge control

AMPVDD

IP

AMPVSS

VREFOUT...

CTLAG........

CFG, DFG, DPG amplifiers CTL amplifier

IP

LPF circuit

CTLAG

Input pin charge control

– 13 –

CXP88616/88624

1 pin

Hi-Z

Low level

When reset

RECCTL (+)

CTLCIN (–)

RECCAP

RECCTL (–)

1 pin

Hi-Z

CTLCIN (+)

Circuit format

IP

AMPVSS

RTG control permission

RTO3

From RECCTL (+) pin

RTG control permission

RTO5

Recording current control circuit

IP

CTLCIN (–) pin

Recording current control circuit

AMPV

SS

Write current select

RTG control permission

RTO7

RTO6

RTO3

AMPV

DD

Write current select

RTO6

RTO7

RTO3

RTG control permission

DD

AMPV

Recording current control circuit

AMPV

SS

IP

CTLCIN (+) pin

From RECCTL (–) pin

RTO3

RTG control permission

IP

AMPVSS

– 14 –

CXP88616/88624

2 pins

Oscillation

EXTAL XTAL

IP

EXTAL

XTAL

• Shows the circuit composition during oscillation.

• Feedback resistor is removed and XTAL becomes High level during stop.

1 pin

Low level

RST

IP

Schmitt input

Pull up resistor

OP

Mask option

When resetPin

Circuit format

– 15 –

CXP88616/88624

∗

1) AVDD and VDD must not exceed +0.3V.

∗

2) AMPVDD and VDD must not exceed +0.3V.

∗

3) VIN and VOUT must not exceed VDD +0.3V.

∗

4) The large current output port is port H (PH).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.

Supply voltage

Input voltage Output voltage Medium drive output voltage High level output current High level total output current

Low level output current

Low level total output current Operating temperature Storage temperature Allowable power dissipation

VDD AVDD AVSS AMPVDD AMPVSS VIN VOUT VOUTP IOH ∑IOH

IOL

IOLC ∑IOL

Topr Tstg PD

–0.3 to +7.0

AVss to +7.0

∗

1

–0.3 to +0.3

AMPVSS to +7.0

∗

2

–0.3 to +0.3

–0.3 to +7.0

∗

3

–0.3 to +7.0

∗

3

–0.3 to +15.0

–5

–50

15

20

130

–20 to +75

–55 to +150

600

V V V V V V V

V mA mA

mA

°C °C

mW

Port H

Total of output pins Other than large current output

ports (value per pin) Large current output port

∗

4

(value per pin) Total of output pins

QFP package type

Item Symbol Rating Unit Remarks

Absolute Maximum Ratings (Vss = 0V reference)

– 16 –

CXP88616/88624

Analog power supply

High level input voltage

Low level input voltage

Operating temperature

Supply voltage

5.5

5.5 VDD VDD VDD

VDD + 0.3

0.3VDD

0.2VDD

0.8

0.4 +75

V V V V V V V V V V

°C

V

Item Symbol Min. Max. Unit Remarks

4.5

3.5

2.5

4.5

0.7VDD

0.8VDD

2.2

VDD – 0.4

0 0 0

–0.3

–20

AVDD AMPVDD VIH VIHS VIHTS VIHEX VIL VILS VILTS VILEX Topr

Guaranteed operation range for 1/2 and 1/4 frequency dividing clock

Guaranteed operation range for 1/16 frequency dividing clock or during SLEEP mode

Guaranteed data hold operation range during STOP

∗

1

∗

2

∗

3

CMOS schmitt input

∗

4

TTL schmitt input

∗

5

EXTAL pin

∗

6

∗

3

CMOS schmitt input

∗

4

TTL schmitt input

∗

5

EXTAL pin

∗

6

VDD

∗

1) AVDD and VDD should be set to the same voltage.

∗

2) AMPVDD and VDD should be set to the same voltage.

∗

3) Normal input port (each pin of PC, PD2, PD3, PD6, PF0 to PF3, PG and PI2 to PI7), MP pin

∗

4) Each pin of RST, PD0/INT1/NMI, PD1/RMC, PD4/CS0, PD5/SCK0, PD7/SI0, PE2, PE3/SYNC, PE4/EXI0, PE5/EXI1, PI0/INT0, PI1/EC/INT2 (For PE3/SYNC, when CMOS schmitt input is selected with mask option.)

∗

5) PE3/SYNC (when TTL schmitt input is selected with mask option.)

∗

6) Specifies only during external clock input.

Recommended Operating Conditions (Vss = 0V reference)

– 17 –

CXP88616/88624

VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA

VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V

High level output voltage

4.0

3.5

0.5 –0.5 –1.5

V V V V

V µA µA µA

µA

PH

EXTAL

RST

∗

1

Item Symbol Pins Conditions Min.

Clock 1MHz 0V other than the measured pins

VDD, VSS

IDD1

IIZ

ILOH

IDDS1 IDD2 IDDS2

IDDS3

CIN

VOH

VOL

IIHE IILE IILR

Low level output voltage

Input current

Typ.

0.4

0.6

1.5 40

–40

–400

±10

50

Max. Unit

DC Characteristics (VDD = 4.5 to 5.5V)

Electrical Characteristics

(Ta = –20 to +75°C, Vss = 0V reference)

∗

1) RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when no resistor is selected.

∗

2) When entire output pins are open.

∗

3) When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEH) to "00" and operating in high speed mode (1/2 frequency dividing clock).

VDD = 5.5V

∗

3

SLEEP mode

VDD = 5.5V

VDD = 5V±0.5V

Supply current

∗

2

Input capacity

VDD = 5.5V, VIL = 0.4V

VDD = 5.5V, VI = 0, 5.5V

VDD = 5.5V VOH = 12V

16MHz crystal oscillation (C1 = C2 = 15pF)

STOP mode (EXTAL pin oscillation stop)

I/O leakage current

Open drain output leakage current (N-CH Tr off state)

PA to PG, PI, MP, AN0 to AN3, RST

∗

1

PH

27

1.8

10

45

8

10

20

mA

µA

pF

PA to PD, PE0 to PE1, PE6 to PE7, PF4 to PF7, PH

(VOL only)

PI

PC, PD, PE2 to PE5 PF, PG, PI, RECCTL (+), RECCTL (–), CTLAMP (+), CTLAMP (–), CTLSAMPI, CFG, DFG, DPG

– 18 –

CXP88616/88624

EC

t

EH tELtEF tER

0.2VDD

0.8VDD

tTH tTLtTF tTR

Fig. 3. Event count clock timing

∗

1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits

(CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

EXTAL

XTAL

t

XH tXLtCF tCR

0.4V

V

DD – 0.4V

1/fc

A

External clock

EXTAL

XTAL

74HC04

A

Crystal oscillation Ceramic oscillation

EXTAL

XTAL

C

1 C2

AC Characteristics (1) Clock timing

System clock frequency

System clock input pulse width System clock input rise and

fall times Event count clock input

pulse width Event count clock input

rise and fall times

fC

tXL, tXH

tCR, tCF

tEH, tEL

tER, tEF

XTAL EXTAL

EC

MHz

ns

ms

Item Symbol Pin Condition Unit

Fig. 1, Fig. 2 Fig. 1, Fig. 2

External clock drive Fig. 1, Fig. 2

External clock drive Fig. 3

Fig. 3

Typ.Min.

1

28

tsys + 200

∗

1

Max.

16

200

20

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Fig. 1. Clock timing

Fig. 2. Clock applied condition

AA

AAA

– 19 –

CXP88616/88624

Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode

Chip select transfer mode (SCK0 = output mode)

Chip select transfer mode

Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper

2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

CS0 ↓ → SCK0 delay time

CS0 ↑ → SCK0 floating delay time

CS0 ↓ → SO0 delay time

CS0 ↑ → SO0 floating delay time

CS0 high level width

SCK0 cycle time

SCK0 high and low level widths

SI0 input set-up time (against SCK0 ↑)

SI0 input hold time (against SCK0 ↑)

SCK0 ↓ → SO0 delay time

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH tKL

tSIK

tKSI

tKSO

SCK0

SO0

CS0

SCK0

SI0

SO0

ns

Symbol Pin Min.

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc – 50

100 200

tsys + 200

100

ns ns ns ns ns ns ns ns ns ns

tsys + 200

100

Max. UnitCondition

– 20 –

CXP88616/88624

Fig. 4. Serial transfer timing (CH0)

CS0

SCK0

0.2V

DD

0.8VDD

tWHCS

tDCSK

tDCSKF

0.8VDD

0.2VDD

0.8VDD

tKCY

tKL tKH

0.8VDD

0.2VDD

SI0

tSIK

tKSI

Input data

t

DCSO tKSO

tDCSOF

Output data

0.8V

DD

0.2VDD

SO0

– 21 –

CXP88616/88624

Conversion time Sampling time Reference input voltage Analog input voltage

tCONV tSAMP

VREF VIAN

IREF

Only for A/D converter operation Ta = 25°C V

DD = AVDD = AVREF = 5.0V

V

DD = AVss = 0V

Operation mode

SLEEP mode STOP mode 32kHz operation mode

Linearity error

Absolute error

Resolution

AVREF current

AVREF

µs µs

V V

AVDD

AVREF

1.0

mA

10

µA

0.6

160/fADC

∗

1

12/fADC

∗

1

AVDD – 0.5

0

Item Symbol Pin

Condition Min.

Typ.

Max. Unit

Bits

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V reference)

8

±1

±2

LSB

Analog input

Linearity error

V

FTVZT

00H

01H

FEH

FFH

Digital conversion value

Fig. 5. Definitions of A/D converter terms

AVREF

AN0 to AN7

∗

1) fADC indicates the below values due to the contents of bit 0 (ADCCK) of the ADC operation clock selection register (MSC: 01FFH), bits 7 (PCK1) and 6 (PCK0) of the clock control register (address: 00FEH).

00 (φ = fEX/2) 01 (φ = fEX/4) 11 (φ = fEX/16)

fADC = fc/2 fADC = fc/4 fADC = fc/16

fADC = fc fADC = fc/2 fADC = fc/8

0 (φ/2 selection) 1 (φ selection)

PCK1, PCK0

ADCCK

– 22 –

CXP88616/88624

External interruption high and low level widths

Reset input low level width

INT0 INT1 INT2 NMI

RST

1

32/fc

µs

Item Symbol Pin Condition Min. Max. Unit

tIH tIL

tRSL

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

0.2VDD

0.8VDD

tIH tIL

INT0 INT1 INT2 NMI (Falling edge)

Fig. 6. Interruption input timing

tRSL

0.2VDD

RST

Fig. 7. Reset input timing

– 23 –

CXP88616/88624

Voltage gain

∗1

Offset voltage

Input resistance

Charge switch ON resistance

RECCTL and CTLCIN connection switch ON resistance

CTLCIN 0V fix switch ON resistance

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

dB

mV

kΩ

Ω

(2) CTL 1st amplifier characteristics

(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, CTLAG reference)

Gain = 16dB RECCTL (–) = 0V

Gain = 27dB RECCTL (–) = 0V

Gain = 42dB RECCTL (–) = 0V

Gain = 58dB RECCTL (–) = 0V

CTLAMP (+) and CTLAMP (–)

= open

Charge switch OFF CTLAMP (+) = +0.2V

Charge switch OFF CTLAMP (–) = +0.2V

Charge switch ON CTLAMP (+) = +0.5V

Charge switch ON CTLAMP (–) = +0.5V

During CTL read operation, CTLCIN (+) – RECCTL (+) = 0.2V

During CTL read operation, CTLCIN (–) – RECCTL (–) = 0.2V

During CTL write operation, CTLCIN (+) = AMPVSS + 0.2V

During CTL write operation, CTLCIN (–) = AMPVSS + 0.2V

AVCTL1

VOSCTL

1

RINCTL

1

RCCTL

1

R

READ

RWRITE

RECCTL (+) CTLFAMPO

∗

2

CTLAMP (+)

CTLAMP (–)

CTLAMP (+)

CTLAMP (–) RECCTL (+)

CTLCIN (+) RECCTL (–)

CTLCIN (–) CTLCIN (+)

CTLCIN (–)

12.5

23.5

39.0

54.5

–40

26.0

1.20

315

14.5

25.5

41.5

57.0

0

44.5

2.0

560

400

250

16.5

27.5

44.0

59.5

+40

1010

770

310

∗

1) When CTLCIN (+), CTLAMP (+) pins and CTLCIN (–), CTLAMP (–) pins are AC coupled, and then the signal is input from RECCTL (+) pin.

∗

2) The result after measuring the CTLFAMPO output waveform or voltage gain.

Note) The gain increases by approximately 1.5dB when the AC coupling capacitor (47µF) is connected to

CTLAMP (+) and CTLAMP (–) pins, and the signal is input from CTLAMP (+) and CTLAMP (–) pins.

Reference level output voltage

Reference level output current

VOR

IOR

VREFOUT CTLAG

VREFOUT

CTLAG

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

V

V mA mA mA mA

Analog Circuit Characteristics

(1) Amplifier circuit reference voltage characteristics

(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)

2.6

2.55 VREFOUT = VREFOUT + 0.5V VREFOUT = VREFOUT – 0.5V CTLAG = CTLAG + 0.5V CTLAG = CTLAG – 0.5V

2.2

2.15

3.50

–0.30

2.80

–0.30

2.4

2.35

6.5

–0.85

5.5

–0.85

– 24 –

CXP88616/88624

Voltage gain

∗1, ∗2

LPF cut-off frequency

∗1, ∗2

Offset voltage

∗2

Comparator level

∗2

Input resistance

Charge switch ON resistance

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

dB dB dB dB

kHz

mV mV0-p mV0-p mV0-p mV0-p mV0-p mV0-

p

kΩ

Ω

(3) CTL 2nd amplifier characteristics

(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, CTLAG reference)

Gain = 5dB Gain = 11dB Gain = 16dB Gain = 20dB

fDC – 3dB CTLSAMPI = open

Comparator level = +100mV0-p Comparator level = +250mV0-p Comparator level = +400mV0-p Comparator level = –100mV0-p Comparator level = –250mV0-p Comparator level = –400mV0-p Charge switch OFF

CTLSAMPI = +0.2V Charge switch ON

CTLSAMPI = +0.5V

AVCTL2

fCCTL

VOSCTL2

VCCTL

RINCTL2

RCCTL2

CTLSAMPI

4.8

10.4

15.3

19.3

15.0 –50

70.0 215 370

–70.0

–220 –370

10.0

5.8

11.5

16.5

20.5

25.0 0

100 245

400 –100 –250 –400

18.0

770

6.8

12.6

17.7

21.7

40.0 +50

130 275 430

–130 –280 –430

1140

∗

1) When the signal is input with the AC coupling capacitor (47µF) connected to CTLSAMPI pin.

∗

2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.

Voltage gain

∗1

Input amplitude

(peak value)

Input sensitivity

Input dead band

Item Symbol Pin

Conditions Min.

Typ.

Max. Unit

dB

mV0-p

(4) CTLAMP characteristics (1st amplifier + 2nd amplifier)

(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)

CTL 1st amplifier gain = 16dB CTL 2nd amplifier gain = 20dB RECCTL (–) = 0V

RECCTL (–) = 0V CTL 1st amplifier gain = 58dB

CTL 2nd amplifier gain = 20dB Comparator level = +400mV0-p

–400mV0-p

RECCTL (–) = 0V

AVCTL

VPKCTL

VSCTL

VNSCTL

RECCTL (+)

31.8

0.015

35.0

0.08

0.04

38.2

±300

0.10

∗

1) As for other combinations of the amplifier gains, CTL 1st amplifier and CTL 2nd amplifier are added respectively.

Note) The result when the signal is input from RECCTL (+) pin with CTL 1st amplifier + CTL 2nd amplifier after

performing AC coupling of CTLCIN (+), CTLAMP (+) pins and CTLCIN (–), CTLAMP (–) pins, and CTLFAMPO, CTLSAMPI pins.

– 25 –

CXP88616/88624

Voltage gain

∗1,∗2

LPF cut-off frequency

∗1,∗2

Offset voltage

∗2

Comparator judgment level width

∗2

Input sensitivity

∗1

Input dead band

∗1

Input resistance Charge switch ON

resistance Digital output

waveform duty

∗1, ∗3

Input amplitude (peak value)

∗1

Item Symbol Pins

Conditions Min.

Typ.

Max. Unit

dB dB dB dB

kHz

mV

mVp-p

kΩ

Ω

%

V0-p

(5) CFGAMP characteristics

(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVDD = 0V, VREFOUT reference)

Gain = 0dB Gain = 20dB Gain = 34dB Gain = 38dB

fDC – 3dB CFG = open

Comparator schimitt width

= 320mV

p-p

Comparator schimitt width

= 160mV

p-p

Gain = 38dB Comparator level = 320mV

p-p

Gain = 38dB Comparator level = 160mV

p-p

Gain = 38dB Comparator level = 320mV

p-p

Gain = 38dB Comparator level = 160mV

p-p

Charge switch OFF CFG = +0.2V

Charge switch ON CFG = +0.5V

CFG = sine wave with 50% duty

AVCFG

fCCFG VOSCFG

VCCFG

VSCFG

VNSCFG

RINCFG

RCCFG

DTYCFG

VPKCFG

CFG

–0.3

19.2

33.2

37.0

30.0 –50 260

110

3.40

1.50

5.5

48.0

0.6

20.8

34.8

38.7

55.0 0

320

155

4.20

2.10

4.10

2.00

8.3

455

50.0

2.2

22.4

36.4

40.4

80.0 +50 360

200

5.00

2.40

710

52.0

±2.4

∗

1) When the signal is input with the AC coupling capacitor (47µF) connected to CFG pin.

∗

2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.

∗

3) The result after measuring the digital signal waveform output from the amplifier circuit.

– 26 –

CXP88616/88624

Voltage gain

∗1, ∗2

LPF cut-off frequency

∗1, ∗2

Offset voltage

∗2

Comparator judgment level width

∗2

Input sensitivity

∗1

Input dead band

∗1

Input resistance Charge switch ON

resistance Digital output

waveform duty

∗1, ∗3

Input amplitude (peak value)

∗1

Item Symbol Pins

Conditions Min.

Typ.

Max. Unit

dB dB dB dB

kHz

mV

mVp-p

kΩ

Ω

%

V0-p

(6) DFGAMP characteristics

(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, VREFOUT reference)

Gain = 0dB Gain = 20dB Gain = 34dB Gain = 38dB

fDC – 3dB DFG = open

Comparator schmitt width

= 320mV

p-p

Comparator schmitt width

= 160mV

p-p

Gain = 38dB Comparator level = 320mV

p-p

Gain = 38dB Comparator level = 160mV

p-p

Gain = 38dB Comparator level = 320mV

p-p

Gain = 38dB Comparator level = 160mV

p-p

Charge switch OFF DFG = +0.2V

Charge switch ON DFG = +0.5V

DFG = sine wave of 50% duty

AVDFG

fCDFG VOSDFG

VCDFG

VSDFG

VNSDFG

RINDFG

RCDFG

DTYDFG

VPKDFG

DFG

–0.3

19.2

33.2

37.0

30.0 –50 260

110

3.40

1.50

5.5

48.0

0.6

20.8

34.8

38.7

55.0 0

320

155

4.20

2.10

4.10

2.00

8.3

455

50.0

2.2

22.4

36.4

40.4

80.0 +50 360

200

5.00

2.40

710

52.0

±2.4

∗

1) When the signal is input with the AC coupling capacitor (47µF) connected to DFG pin.

∗

2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.

∗

3) The result after measuring the digital signal waveform output from the amplifier circuit.

– 27 –

CXP88616/88624

Voltage gain

∗1, ∗2

LPF cut-off frequency

∗1, ∗2

Offset voltage

∗2

Comparator level

∗2

Input sensitivity

∗1

Input dead band

∗1

Input resistance Charge switch ON

resistance Input amplitude

(peak value)

∗1

Item Symbol Pins

Conditions Min.

Typ.

Max. Unit

dB kHz mV

mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p

mV0-p

kΩ

Ω

V

(7) DPGAMP characteristics

(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, VREFOUT reference)

fDC – 3dB DFG = open

Comparator level = 600mV0-p Comparator level = 400mV0-p Comparator level = 200mV0-p Comparator level = 100mV0-p Comparator level = –600mV0-p Comparator level = –400mV0-p Comparator level = –200mV0-p Comparator level = –100mV0-p Comparator level

= 600mV0-p, 200mV0-p Comparator level

= 400mV0-p, 100mV0-p Comparator level

= –600mV0-p, –200mV0-p Comparator level

= –400mV0-p, –100mV0-p Comparator level

= 600mV0-p, 200mV0-p Comparator level

= 400mV0-p, 100mV0-p Comparator level

= –600mV0-p, –200mV0-p Comparator level

= –400mV0-p, –100mV0-p Charge switch OFF

DPG = +0.2V Charge switch ON

DPG = +0.5V

AVDPG fCDPG VOSDPG

VCDPG

VSDPG

VNSDPG

RINDPG

RCDPG

VPKDPG

DPG

11.1

30.0 –35

570 370 175

72 –572 –368 –174

–71

113

70

–120

–80

24.0

12.0

55.0 0

605 400 200

100 –605 –400 –200 –100

150

100

–155

–109

142

90

–150

–103

44.5

450

13.2

85.0 +35

640 432 220 125

–643 –438 –223 –124

180

120

–185

–130

860

±2.4

∗

1) When the signal is input with the AC coupling capacitor (47µF) connected to DPG pin.

∗

2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.

– 28 –

CXP88616/88624

Output resistance

Output current

∗1

Item Symbol Pins

Conditions Min.

Typ.

Max. Unit

Ω Ω

mA mA mA mA mA mA mA mA mA

(8) CTL write circuit characteristics

(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)

RECCAP = AMPVDD – 0.5V RECCAP = AMPVDD + 0.5V Write current = 2.0mA Write current = 2.5mA Write current = 3.0mA Write current = 3.5mA Write current = 4.0mA Write current = 4.5mA Write current = 5.0mA Write current = 5.5mA Write current = 6.0mA

ROH ROL

IOREC

RECCAP

RECCTL (+) RECCTL (–)

450 410

1.3

1.7

2.1

2.6

2.9

3.3

3.7

4.0

4.4

625 555

2.0

2.5

3.1

3.6

4.0

4.6

5.1

5.6

6.1

1005

840

2.9

3.7

4.5

5.2

5.9

6.6

7.2

8.0

8.9

∗

1) The current value which flows when RECCTL (+) pin and RECCTL (–) pin are shorted.

Amplifier operating current

IAMP AMPVDD

Item Symbol Pins

Conditions Min.

Typ.

Max. Unit

mA

µA

(9) Amplifier operating current characteristics

(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)

12.0 10

When the amplifier is operating

∗

1

When the amplifier is not operating

7.6

∗

1) The CTL recording current is added during CTL write.

Note) The amplifier operation and NOT-operation is controlled according to the contents of amplifier power

supply control register (ASWC: 05E2H) bits 5, 4, 1 and 0.

– 29 –

CXP88616/88624

Supplement

Fig. 8. Recommended oscillation circuit

A

AAAA

EXTAL

XTAL

C

1 C2

Rd

Manufacturer

RIVER ELETEC CO., LTD.

KINSEKI LTD.

Model

HC-49/U03

HC-49/U (-S)

fc (MHz)

8.00

10.00

12.00

8.00

10.00

16.00

12

10

5

16 (12) 16 (12)

10

16.00

5

16 (12) 16 (12)

0

C1 (pF) C2 (pF) Rd (Ω)

Mask option table

12.00 12

12

∗

1) The input circuit format can be selected for PE3/SYNC pin.

Item

Content Reset pin pull-up resistor Input circuit format

∗

1

Non-existent

CMOS schmitt

Existent

TTL schmitt

AA

– 30 –

CXP88616/88624

3 4 5 6

1

20

10

0.1 1 72

0.2

0.5

2

5

50

5 10

0

5

10

15

20

25

30

16

15

IDD vs. VDD

(fc = 16MHz, Ta = 25°C, Typical)

I

DD

– Supply current [mA]

VDD – Supply voltage [V]

IDD vs. fc

(VDD = 5.0V, Ta = 25°C, Typical)

fc – System clock [MHz]

SLEEP mode

1/16 dividing mode

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

1/4 dividing mode

I

DD

– Supply current [mA]

Characteristics Curve

– 31 –

CXP88616/88624

Package Outline Unit: mm

SONY CODE EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL PACKAGE MASS

EPOXY RESIN SOLDER PLATING

42/COPPER ALLOY

PACKAGE STRUCTURE

23.9 ± 0.4

QFP-100P-L01

100PIN QFP (PLASTIC)

20.0 – 0.1

+ 0.4

0.15 – 0.05

+ 0.1

15.8 ± 0.4

17.9 ± 0.4

14.0 – 0.1

+ 0.4

2.75 – 0.15

+ 0.35

A

0.65 M

0.13

QFP100-P-1420

1.7g

1

100

81

80 51

50

31

30

0.3 – 0.1

+ 0.15

DETAIL A

0° to 10°

0.8 ± 0.2

(16.3)

0.15

0.1 – 0.05

+ 0.2